1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.cache._ 28import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 29 30trait HasL1PrefetchSourceParameter { 31 // l1 prefetch source related 32 def L1PfSourceBits = 3 33 def L1_HW_PREFETCH_NULL = 0.U 34 def L1_HW_PREFETCH_CLEAR = 1.U // used to be a prefetch, clear by demand request 35 def L1_HW_PREFETCH_STRIDE = 2.U 36 def L1_HW_PREFETCH_STREAM = 3.U 37 def L1_HW_PREFETCH_STORE = 4.U 38 39 // ------------------------------------------------------------------------------------------------------------------------ 40 // timeline: L1_HW_PREFETCH_NULL --(pf by stream)--> L1_HW_PREFETCH_STREAM --(pf hit by load)--> L1_HW_PREFETCH_CLEAR 41 // ------------------------------------------------------------------------------------------------------------------------ 42 43 def isPrefetchRelated(value: UInt) = value >= L1_HW_PREFETCH_CLEAR 44 def isFromL1Prefetch(value: UInt) = value > L1_HW_PREFETCH_CLEAR 45 def isFromStride(value: UInt) = value === L1_HW_PREFETCH_STRIDE 46 def isFromStream(value: UInt) = value === L1_HW_PREFETCH_STREAM 47} 48 49class L1PrefetchSource(implicit p: Parameters) extends XSBundle with HasL1PrefetchSourceParameter { 50 val value = UInt(L1PfSourceBits.W) 51} 52 53class L1PrefetchReq(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 54 val paddr = UInt(PAddrBits.W) 55 val alias = UInt(2.W) 56 val confidence = UInt(1.W) 57 val is_store = Bool() 58 val pf_source = new L1PrefetchSource 59 60 // only index bit is used, do not use tag 61 def getVaddr(): UInt = { 62 Cat(alias, paddr(DCacheSameVPAddrLength-1, 0)) 63 } 64 65 // when l1 cache prefetch req arrives at load unit: 66 // if (confidence == 1) 67 // override load unit 2 load req 68 // else if (load unit 1/2 is available) 69 // send prefetch req 70 // else 71 // report prefetch !ready 72} 73 74class L1PrefetchHint(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 75 val loadbusy = Bool() 76 val missqbusy = Bool() 77} 78 79class L1PrefetchFuzzer(implicit p: Parameters) extends DCacheModule{ 80 val io = IO(new Bundle() { 81 // prefetch req interface 82 val req = Decoupled(new L1PrefetchReq()) 83 // for fuzzer address gen 84 val vaddr = Input(UInt(VAddrBits.W)) 85 val paddr = Input(UInt(PAddrBits.W)) 86 }) 87 88 // prefetch req queue is not provided, prefetcher must maintain its 89 // own prefetch req queue. 90 val rand_offset = LFSR64(seed=Some(123L))(5,0) << 6 91 val rand_addr_select = LFSR64(seed=Some(567L))(3,0) === 0.U 92 93 // use valid vaddr and paddr 94 val rand_vaddr = DelayN(io.vaddr, 2) 95 val rand_paddr = DelayN(io.paddr, 2) 96 97 io.req.bits.paddr := PmemRanges.map(_.lower).min.U + rand_offset 98 io.req.bits.alias := io.req.bits.paddr(13,12) 99 io.req.bits.confidence := LFSR64(seed=Some(789L))(4,0) === 0.U 100 io.req.bits.is_store := LFSR64(seed=Some(890L))(4,0) === 0.U 101 io.req.valid := LFSR64(seed=Some(901L))(3,0) === 0.U 102} 103