xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala (revision dcd58560d0a04f86ddbf73a98bd16c41d4a8e205) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils._
23import xiangshan.ExceptionNO._
24import xiangshan._
25import xiangshan.backend.fu.PMPRespBundle
26import xiangshan.cache._
27import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp}
28
29class L1PrefetchReq (implicit p: Parameters) extends XSBundle with HasDCacheParameters{
30  val paddr = UInt(PAddrBits.W)
31  val alias = UInt(2.W)
32  val confidence = UInt(1.W)
33  val is_store = Bool()
34
35  // only index bit is used, do not use tag
36  def getVaddr(): UInt = {
37    Cat(alias, paddr(DCacheSameVPAddrLength-1, 0))
38  }
39
40  // when l1 cache prefetch req arrives at load unit:
41  // if (confidence == 1)
42  //   override load unit 2 load req
43  // else if (load unit 1/2 is available)
44  //   send prefetch req
45  // else
46  //   report prefetch !ready
47}
48
49class L1PrefetchHint (implicit p: Parameters) extends XSBundle with HasDCacheParameters{
50  val loadbusy = Bool()
51  val missqbusy = Bool()
52}
53
54class L1PrefetchFuzzer(implicit p: Parameters) extends DCacheModule{
55  val io = IO(new Bundle() {
56    // prefetch req interface
57    val req = Decoupled(new L1PrefetchReq())
58    // for fuzzer address gen
59    val vaddr = Input(UInt(VAddrBits.W))
60    val paddr = Input(UInt(PAddrBits.W))
61  })
62
63  // prefetch req queue is not provided, prefetcher must maintain its
64  // own prefetch req queue.
65  val rand_offset = LFSR64()(3,0) << 6
66  val rand_addr_select = LFSR64()(3,0) === 0.U
67
68  // use valid vaddr and paddr
69  val rand_vaddr = DelayN(io.vaddr, 2)
70  val rand_paddr = DelayN(io.paddr, 2)
71
72  io.req.bits.paddr := 0x80000000L.U + rand_offset
73  io.req.bits.alias := io.req.bits.paddr(13,12)
74  io.req.bits.confidence := LFSR64()(4,0) === 0.U
75  io.req.bits.is_store := LFSR64()(4,0) === 0.U
76  io.req.valid := LFSR64()(3,0) === 0.U
77}