1package xiangshan.utils 2 3import chisel3.emitVerilog 4import chisel3.util.ValidIO 5import top.ArgParser 6import utils.PipeWithFlush 7import xiangshan.{Redirect, XSCoreParamsKey, XSTileKey} 8import xiangshan.backend.Bundles.DynInst 9 10object GenPipeWithFlush extends App { 11 println("Generating the VerilogPipeWithFlush hardware") 12 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) 13 val p = config.alterPartial({ case XSCoreParamsKey => config(XSTileKey).head }) 14 15// emitVerilog( 16// new PipeWithFlush[DynInst, ValidIO[Redirect]]( 17// new DynInst()(p), 18// ValidIO(new Redirect()(p)), 19// 2, 20// (dynInst: DynInst, flush: ValidIO[Redirect], stage: Int) => dynInst.robIdx.needFlush(flush) 21// ), 22// Array("--target-dir", "build/vifu")) 23} 24