1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_EXYNOS_DRM_H_ 8 #define _UAPI_EXYNOS_DRM_H_ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 struct drm_exynos_gem_create { 14 __u64 size; 15 __u32 flags; 16 __u32 handle; 17 }; 18 struct drm_exynos_gem_map { 19 __u32 handle; 20 __u32 reserved; 21 __u64 offset; 22 }; 23 struct drm_exynos_gem_info { 24 __u32 handle; 25 __u32 flags; 26 __u64 size; 27 }; 28 struct drm_exynos_vidi_connection { 29 __u32 connection; 30 __u32 extensions; 31 __u64 edid; 32 }; 33 enum e_drm_exynos_gem_mem_type { 34 EXYNOS_BO_CONTIG = 0 << 0, 35 EXYNOS_BO_NONCONTIG = 1 << 0, 36 EXYNOS_BO_NONCACHABLE = 0 << 1, 37 EXYNOS_BO_CACHABLE = 1 << 1, 38 EXYNOS_BO_WC = 1 << 2, 39 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | EXYNOS_BO_WC 40 }; 41 struct drm_exynos_g2d_get_ver { 42 __u32 major; 43 __u32 minor; 44 }; 45 struct drm_exynos_g2d_cmd { 46 __u32 offset; 47 __u32 data; 48 }; 49 enum drm_exynos_g2d_buf_type { 50 G2D_BUF_USERPTR = 1 << 31, 51 }; 52 enum drm_exynos_g2d_event_type { 53 G2D_EVENT_NOT, 54 G2D_EVENT_NONSTOP, 55 G2D_EVENT_STOP, 56 }; 57 struct drm_exynos_g2d_userptr { 58 unsigned long userptr; 59 unsigned long size; 60 }; 61 struct drm_exynos_g2d_set_cmdlist { 62 __u64 cmd; 63 __u64 cmd_buf; 64 __u32 cmd_nr; 65 __u32 cmd_buf_nr; 66 __u64 event_type; 67 __u64 user_data; 68 }; 69 struct drm_exynos_g2d_exec { 70 __u64 async; 71 }; 72 struct drm_exynos_ioctl_ipp_get_res { 73 __u32 count_ipps; 74 __u32 reserved; 75 __u64 ipp_id_ptr; 76 }; 77 enum drm_exynos_ipp_format_type { 78 DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01, 79 DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02, 80 }; 81 struct drm_exynos_ipp_format { 82 __u32 fourcc; 83 __u32 type; 84 __u64 modifier; 85 }; 86 enum drm_exynos_ipp_capability { 87 DRM_EXYNOS_IPP_CAP_CROP = 0x01, 88 DRM_EXYNOS_IPP_CAP_ROTATE = 0x02, 89 DRM_EXYNOS_IPP_CAP_SCALE = 0x04, 90 DRM_EXYNOS_IPP_CAP_CONVERT = 0x08, 91 }; 92 struct drm_exynos_ioctl_ipp_get_caps { 93 __u32 ipp_id; 94 __u32 capabilities; 95 __u32 reserved; 96 __u32 formats_count; 97 __u64 formats_ptr; 98 }; 99 enum drm_exynos_ipp_limit_type { 100 DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001, 101 DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002, 102 DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16, 103 DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16, 104 DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16, 105 DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f, 106 DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16, 107 }; 108 struct drm_exynos_ipp_limit_val { 109 __u32 min; 110 __u32 max; 111 __u32 align; 112 __u32 reserved; 113 }; 114 struct drm_exynos_ipp_limit { 115 __u32 type; 116 __u32 reserved; 117 struct drm_exynos_ipp_limit_val h; 118 struct drm_exynos_ipp_limit_val v; 119 }; 120 struct drm_exynos_ioctl_ipp_get_limits { 121 __u32 ipp_id; 122 __u32 fourcc; 123 __u64 modifier; 124 __u32 type; 125 __u32 limits_count; 126 __u64 limits_ptr; 127 }; 128 enum drm_exynos_ipp_task_id { 129 DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001, 130 DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002, 131 DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003, 132 DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004, 133 DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16, 134 DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16, 135 }; 136 struct drm_exynos_ipp_task_buffer { 137 __u32 id; 138 __u32 fourcc; 139 __u32 width, height; 140 __u32 gem_id[4]; 141 __u32 offset[4]; 142 __u32 pitch[4]; 143 __u64 modifier; 144 }; 145 struct drm_exynos_ipp_task_rect { 146 __u32 id; 147 __u32 reserved; 148 __u32 x; 149 __u32 y; 150 __u32 w; 151 __u32 h; 152 }; 153 struct drm_exynos_ipp_task_transform { 154 __u32 id; 155 __u32 rotation; 156 }; 157 struct drm_exynos_ipp_task_alpha { 158 __u32 id; 159 __u32 value; 160 }; 161 enum drm_exynos_ipp_flag { 162 DRM_EXYNOS_IPP_FLAG_EVENT = 0x01, 163 DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02, 164 DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04, 165 }; 166 #define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT | DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK) 167 struct drm_exynos_ioctl_ipp_commit { 168 __u32 ipp_id; 169 __u32 flags; 170 __u32 reserved; 171 __u32 params_size; 172 __u64 params_ptr; 173 __u64 user_data; 174 }; 175 #define DRM_EXYNOS_GEM_CREATE 0x00 176 #define DRM_EXYNOS_GEM_MAP 0x01 177 #define DRM_EXYNOS_GEM_GET 0x04 178 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 179 #define DRM_EXYNOS_G2D_GET_VER 0x20 180 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 181 #define DRM_EXYNOS_G2D_EXEC 0x22 182 #define DRM_EXYNOS_IPP_GET_RESOURCES 0x40 183 #define DRM_EXYNOS_IPP_GET_CAPS 0x41 184 #define DRM_EXYNOS_IPP_GET_LIMITS 0x42 185 #define DRM_EXYNOS_IPP_COMMIT 0x43 186 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 187 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) 188 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 189 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 190 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 191 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 192 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 193 #define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_RESOURCES, struct drm_exynos_ioctl_ipp_get_res) 194 #define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps) 195 #define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_LIMITS, struct drm_exynos_ioctl_ipp_get_limits) 196 #define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit) 197 #define DRM_EXYNOS_G2D_EVENT 0x80000000 198 #define DRM_EXYNOS_IPP_EVENT 0x80000002 199 struct drm_exynos_g2d_event { 200 struct drm_event base; 201 __u64 user_data; 202 __u32 tv_sec; 203 __u32 tv_usec; 204 __u32 cmdlist_no; 205 __u32 reserved; 206 }; 207 struct drm_exynos_ipp_event { 208 struct drm_event base; 209 __u64 user_data; 210 __u32 tv_sec; 211 __u32 tv_usec; 212 __u32 ipp_id; 213 __u32 sequence; 214 __u64 reserved; 215 }; 216 #ifdef __cplusplus 217 } 218 #endif 219 #endif 220