1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __UAPI_IVPU_DRM_H__ 8 #define __UAPI_IVPU_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_IVPU_DRIVER_MAJOR 1 14 #define DRM_IVPU_DRIVER_MINOR 0 15 #define DRM_IVPU_GET_PARAM 0x00 16 #define DRM_IVPU_SET_PARAM 0x01 17 #define DRM_IVPU_BO_CREATE 0x02 18 #define DRM_IVPU_BO_INFO 0x03 19 #define DRM_IVPU_SUBMIT 0x05 20 #define DRM_IVPU_BO_WAIT 0x06 21 #define DRM_IVPU_METRIC_STREAMER_START 0x07 22 #define DRM_IVPU_METRIC_STREAMER_STOP 0x08 23 #define DRM_IVPU_METRIC_STREAMER_GET_DATA 0x09 24 #define DRM_IVPU_METRIC_STREAMER_GET_INFO 0x0a 25 #define DRM_IOCTL_IVPU_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param) 26 #define DRM_IOCTL_IVPU_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param) 27 #define DRM_IOCTL_IVPU_BO_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create) 28 #define DRM_IOCTL_IVPU_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info) 29 #define DRM_IOCTL_IVPU_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit) 30 #define DRM_IOCTL_IVPU_BO_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait) 31 #define DRM_IOCTL_IVPU_METRIC_STREAMER_START DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_START, struct drm_ivpu_metric_streamer_start) 32 #define DRM_IOCTL_IVPU_METRIC_STREAMER_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_STOP, struct drm_ivpu_metric_streamer_stop) 33 #define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_DATA, struct drm_ivpu_metric_streamer_get_data) 34 #define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_INFO, struct drm_ivpu_metric_streamer_get_data) 35 #define DRM_IVPU_PARAM_DEVICE_ID 0 36 #define DRM_IVPU_PARAM_DEVICE_REVISION 1 37 #define DRM_IVPU_PARAM_PLATFORM_TYPE 2 38 #define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3 39 #define DRM_IVPU_PARAM_NUM_CONTEXTS 4 40 #define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5 41 #define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6 42 #define DRM_IVPU_PARAM_CONTEXT_ID 7 43 #define DRM_IVPU_PARAM_FW_API_VERSION 8 44 #define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9 45 #define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10 46 #define DRM_IVPU_PARAM_TILE_CONFIG 11 47 #define DRM_IVPU_PARAM_SKU 12 48 #define DRM_IVPU_PARAM_CAPABILITIES 13 49 #define DRM_IVPU_PLATFORM_TYPE_SILICON 0 50 #define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0 51 #define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1 52 #define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2 53 #define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3 54 #define DRM_IVPU_JOB_PRIORITY_DEFAULT 0 55 #define DRM_IVPU_JOB_PRIORITY_IDLE 1 56 #define DRM_IVPU_JOB_PRIORITY_NORMAL 2 57 #define DRM_IVPU_JOB_PRIORITY_FOCUS 3 58 #define DRM_IVPU_JOB_PRIORITY_REALTIME 4 59 #define DRM_IVPU_CAP_METRIC_STREAMER 1 60 #define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2 61 struct drm_ivpu_param { 62 __u32 param; 63 __u32 index; 64 __u64 value; 65 }; 66 #define DRM_IVPU_BO_SHAVE_MEM 0x00000001 67 #define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM 68 #define DRM_IVPU_BO_MAPPABLE 0x00000002 69 #define DRM_IVPU_BO_DMA_MEM 0x00000004 70 #define DRM_IVPU_BO_CACHED 0x00000000 71 #define DRM_IVPU_BO_UNCACHED 0x00010000 72 #define DRM_IVPU_BO_WC 0x00020000 73 #define DRM_IVPU_BO_CACHE_MASK 0x00030000 74 #define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_DMA_MEM | DRM_IVPU_BO_CACHE_MASK) 75 struct drm_ivpu_bo_create { 76 __u64 size; 77 __u32 flags; 78 __u32 handle; 79 __u64 vpu_addr; 80 }; 81 struct drm_ivpu_bo_info { 82 __u32 handle; 83 __u32 flags; 84 __u64 vpu_addr; 85 __u64 mmap_offset; 86 __u64 size; 87 }; 88 #define DRM_IVPU_ENGINE_COMPUTE 0 89 #define DRM_IVPU_ENGINE_COPY 1 90 struct drm_ivpu_submit { 91 __u64 buffers_ptr; 92 __u32 buffer_count; 93 __u32 engine; 94 __u32 flags; 95 __u32 commands_offset; 96 __u32 priority; 97 }; 98 #define DRM_IVPU_JOB_STATUS_SUCCESS 0 99 #define DRM_IVPU_JOB_STATUS_ABORTED 256 100 struct drm_ivpu_bo_wait { 101 __u32 handle; 102 __u32 flags; 103 __s64 timeout_ns; 104 __u32 job_status; 105 __u32 pad; 106 }; 107 struct drm_ivpu_metric_streamer_start { 108 __u64 metric_group_mask; 109 __u64 sampling_period_ns; 110 __u32 read_period_samples; 111 __u32 sample_size; 112 __u32 max_data_size; 113 }; 114 struct drm_ivpu_metric_streamer_get_data { 115 __u64 metric_group_mask; 116 __u64 buffer_ptr; 117 __u64 buffer_size; 118 __u64 data_size; 119 }; 120 struct drm_ivpu_metric_streamer_stop { 121 __u64 metric_group_mask; 122 }; 123 #ifdef __cplusplus 124 } 125 #endif 126 #endif 127