1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __MSM_DRM_H__ 8 #define __MSM_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define MSM_PIPE_NONE 0x00 14 #define MSM_PIPE_2D0 0x01 15 #define MSM_PIPE_2D1 0x02 16 #define MSM_PIPE_3D0 0x10 17 #define MSM_PIPE_ID_MASK 0xffff 18 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 19 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 20 struct drm_msm_timespec { 21 __s64 tv_sec; 22 __s64 tv_nsec; 23 }; 24 #define MSM_PARAM_GPU_ID 0x01 25 #define MSM_PARAM_GMEM_SIZE 0x02 26 #define MSM_PARAM_CHIP_ID 0x03 27 #define MSM_PARAM_MAX_FREQ 0x04 28 #define MSM_PARAM_TIMESTAMP 0x05 29 #define MSM_PARAM_GMEM_BASE 0x06 30 #define MSM_PARAM_PRIORITIES 0x07 31 #define MSM_PARAM_PP_PGTABLE 0x08 32 #define MSM_PARAM_FAULTS 0x09 33 #define MSM_PARAM_SUSPENDS 0x0a 34 #define MSM_PARAM_SYSPROF 0x0b 35 #define MSM_PARAM_COMM 0x0c 36 #define MSM_PARAM_CMDLINE 0x0d 37 #define MSM_PARAM_VA_START 0x0e 38 #define MSM_PARAM_VA_SIZE 0x0f 39 #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 40 #define MSM_PARAM_RAYTRACING 0x11 41 #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES 42 struct drm_msm_param { 43 __u32 pipe; 44 __u32 param; 45 __u64 value; 46 __u32 len; 47 __u32 pad; 48 }; 49 #define MSM_BO_SCANOUT 0x00000001 50 #define MSM_BO_GPU_READONLY 0x00000002 51 #define MSM_BO_CACHE_MASK 0x000f0000 52 #define MSM_BO_CACHED 0x00010000 53 #define MSM_BO_WC 0x00020000 54 #define MSM_BO_UNCACHED 0x00040000 55 #define MSM_BO_CACHED_COHERENT 0x080000 56 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHE_MASK) 57 struct drm_msm_gem_new { 58 __u64 size; 59 __u32 flags; 60 __u32 handle; 61 }; 62 #define MSM_INFO_GET_OFFSET 0x00 63 #define MSM_INFO_GET_IOVA 0x01 64 #define MSM_INFO_SET_NAME 0x02 65 #define MSM_INFO_GET_NAME 0x03 66 #define MSM_INFO_SET_IOVA 0x04 67 #define MSM_INFO_GET_FLAGS 0x05 68 #define MSM_INFO_SET_METADATA 0x06 69 #define MSM_INFO_GET_METADATA 0x07 70 struct drm_msm_gem_info { 71 __u32 handle; 72 __u32 info; 73 __u64 value; 74 __u32 len; 75 __u32 pad; 76 }; 77 #define MSM_PREP_READ 0x01 78 #define MSM_PREP_WRITE 0x02 79 #define MSM_PREP_NOSYNC 0x04 80 #define MSM_PREP_BOOST 0x08 81 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC | MSM_PREP_BOOST | 0) 82 struct drm_msm_gem_cpu_prep { 83 __u32 handle; 84 __u32 op; 85 struct drm_msm_timespec timeout; 86 }; 87 struct drm_msm_gem_cpu_fini { 88 __u32 handle; 89 }; 90 struct drm_msm_gem_submit_reloc { 91 __u32 submit_offset; 92 #ifdef __cplusplus 93 __u32 _or; 94 #else 95 __u32 or; 96 #endif 97 __s32 shift; 98 __u32 reloc_idx; 99 __u64 reloc_offset; 100 }; 101 #define MSM_SUBMIT_CMD_BUF 0x0001 102 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 103 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 104 struct drm_msm_gem_submit_cmd { 105 __u32 type; 106 __u32 submit_idx; 107 __u32 submit_offset; 108 __u32 size; 109 __u32 pad; 110 __u32 nr_relocs; 111 __u64 relocs; 112 }; 113 #define MSM_SUBMIT_BO_READ 0x0001 114 #define MSM_SUBMIT_BO_WRITE 0x0002 115 #define MSM_SUBMIT_BO_DUMP 0x0004 116 #define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008 117 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP | MSM_SUBMIT_BO_NO_IMPLICIT) 118 struct drm_msm_gem_submit_bo { 119 __u32 flags; 120 __u32 handle; 121 __u64 presumed; 122 }; 123 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 124 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 125 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 126 #define MSM_SUBMIT_SUDO 0x10000000 127 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 128 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 129 #define MSM_SUBMIT_FENCE_SN_IN 0x02000000 130 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | MSM_SUBMIT_SYNCOBJ_IN | MSM_SUBMIT_SYNCOBJ_OUT | MSM_SUBMIT_FENCE_SN_IN | 0) 131 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 132 #define MSM_SUBMIT_SYNCOBJ_FLAGS (MSM_SUBMIT_SYNCOBJ_RESET | 0) 133 struct drm_msm_gem_submit_syncobj { 134 __u32 handle; 135 __u32 flags; 136 __u64 point; 137 }; 138 struct drm_msm_gem_submit { 139 __u32 flags; 140 __u32 fence; 141 __u32 nr_bos; 142 __u32 nr_cmds; 143 __u64 bos; 144 __u64 cmds; 145 __s32 fence_fd; 146 __u32 queueid; 147 __u64 in_syncobjs; 148 __u64 out_syncobjs; 149 __u32 nr_in_syncobjs; 150 __u32 nr_out_syncobjs; 151 __u32 syncobj_stride; 152 __u32 pad; 153 }; 154 #define MSM_WAIT_FENCE_BOOST 0x00000001 155 #define MSM_WAIT_FENCE_FLAGS (MSM_WAIT_FENCE_BOOST | 0) 156 struct drm_msm_wait_fence { 157 __u32 fence; 158 __u32 flags; 159 struct drm_msm_timespec timeout; 160 __u32 queueid; 161 }; 162 #define MSM_MADV_WILLNEED 0 163 #define MSM_MADV_DONTNEED 1 164 #define __MSM_MADV_PURGED 2 165 struct drm_msm_gem_madvise { 166 __u32 handle; 167 __u32 madv; 168 __u32 retained; 169 }; 170 #define MSM_SUBMITQUEUE_FLAGS (0) 171 struct drm_msm_submitqueue { 172 __u32 flags; 173 __u32 prio; 174 __u32 id; 175 }; 176 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 177 struct drm_msm_submitqueue_query { 178 __u64 data; 179 __u32 id; 180 __u32 param; 181 __u32 len; 182 __u32 pad; 183 }; 184 #define DRM_MSM_GET_PARAM 0x00 185 #define DRM_MSM_SET_PARAM 0x01 186 #define DRM_MSM_GEM_NEW 0x02 187 #define DRM_MSM_GEM_INFO 0x03 188 #define DRM_MSM_GEM_CPU_PREP 0x04 189 #define DRM_MSM_GEM_CPU_FINI 0x05 190 #define DRM_MSM_GEM_SUBMIT 0x06 191 #define DRM_MSM_WAIT_FENCE 0x07 192 #define DRM_MSM_GEM_MADVISE 0x08 193 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 194 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 195 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 196 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 197 #define DRM_IOCTL_MSM_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) 198 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 199 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 200 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 201 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 202 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 203 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 204 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 205 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 206 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 207 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 208 #ifdef __cplusplus 209 } 210 #endif 211 #endif 212