1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _V3D_DRM_H_ 8 #define _V3D_DRM_H_ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_V3D_SUBMIT_CL 0x00 14 #define DRM_V3D_WAIT_BO 0x01 15 #define DRM_V3D_CREATE_BO 0x02 16 #define DRM_V3D_MMAP_BO 0x03 17 #define DRM_V3D_GET_PARAM 0x04 18 #define DRM_V3D_GET_BO_OFFSET 0x05 19 #define DRM_V3D_SUBMIT_TFU 0x06 20 #define DRM_V3D_SUBMIT_CSD 0x07 21 #define DRM_V3D_PERFMON_CREATE 0x08 22 #define DRM_V3D_PERFMON_DESTROY 0x09 23 #define DRM_V3D_PERFMON_GET_VALUES 0x0a 24 #define DRM_V3D_SUBMIT_CPU 0x0b 25 #define DRM_V3D_PERFMON_GET_COUNTER 0x0c 26 #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) 27 #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) 28 #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo) 29 #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) 30 #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) 31 #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) 32 #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) 33 #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd) 34 #define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, struct drm_v3d_perfmon_create) 35 #define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, struct drm_v3d_perfmon_destroy) 36 #define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, struct drm_v3d_perfmon_get_values) 37 #define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu) 38 #define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, struct drm_v3d_perfmon_get_counter) 39 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01 40 #define DRM_V3D_SUBMIT_EXTENSION 0x02 41 struct drm_v3d_extension { 42 __u64 next; 43 __u32 id; 44 #define DRM_V3D_EXT_ID_MULTI_SYNC 0x01 45 #define DRM_V3D_EXT_ID_CPU_INDIRECT_CSD 0x02 46 #define DRM_V3D_EXT_ID_CPU_TIMESTAMP_QUERY 0x03 47 #define DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY 0x04 48 #define DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY 0x05 49 #define DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY 0x06 50 #define DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY 0x07 51 __u32 flags; 52 }; 53 struct drm_v3d_sem { 54 __u32 handle; 55 __u32 flags; 56 __u64 point; 57 __u64 mbz[2]; 58 }; 59 enum v3d_queue { 60 V3D_BIN, 61 V3D_RENDER, 62 V3D_TFU, 63 V3D_CSD, 64 V3D_CACHE_CLEAN, 65 V3D_CPU, 66 }; 67 struct drm_v3d_multi_sync { 68 struct drm_v3d_extension base; 69 __u64 in_syncs; 70 __u64 out_syncs; 71 __u32 in_sync_count; 72 __u32 out_sync_count; 73 __u32 wait_stage; 74 __u32 pad; 75 }; 76 struct drm_v3d_submit_cl { 77 __u32 bcl_start; 78 __u32 bcl_end; 79 __u32 rcl_start; 80 __u32 rcl_end; 81 __u32 in_sync_bcl; 82 __u32 in_sync_rcl; 83 __u32 out_sync; 84 __u32 qma; 85 __u32 qms; 86 __u32 qts; 87 __u64 bo_handles; 88 __u32 bo_handle_count; 89 __u32 flags; 90 __u32 perfmon_id; 91 __u32 pad; 92 __u64 extensions; 93 }; 94 struct drm_v3d_wait_bo { 95 __u32 handle; 96 __u32 pad; 97 __u64 timeout_ns; 98 }; 99 struct drm_v3d_create_bo { 100 __u32 size; 101 __u32 flags; 102 __u32 handle; 103 __u32 offset; 104 }; 105 struct drm_v3d_mmap_bo { 106 __u32 handle; 107 __u32 flags; 108 __u64 offset; 109 }; 110 enum drm_v3d_param { 111 DRM_V3D_PARAM_V3D_UIFCFG, 112 DRM_V3D_PARAM_V3D_HUB_IDENT1, 113 DRM_V3D_PARAM_V3D_HUB_IDENT2, 114 DRM_V3D_PARAM_V3D_HUB_IDENT3, 115 DRM_V3D_PARAM_V3D_CORE0_IDENT0, 116 DRM_V3D_PARAM_V3D_CORE0_IDENT1, 117 DRM_V3D_PARAM_V3D_CORE0_IDENT2, 118 DRM_V3D_PARAM_SUPPORTS_TFU, 119 DRM_V3D_PARAM_SUPPORTS_CSD, 120 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH, 121 DRM_V3D_PARAM_SUPPORTS_PERFMON, 122 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT, 123 DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE, 124 DRM_V3D_PARAM_MAX_PERF_COUNTERS, 125 }; 126 struct drm_v3d_get_param { 127 __u32 param; 128 __u32 pad; 129 __u64 value; 130 }; 131 struct drm_v3d_get_bo_offset { 132 __u32 handle; 133 __u32 offset; 134 }; 135 struct drm_v3d_submit_tfu { 136 __u32 icfg; 137 __u32 iia; 138 __u32 iis; 139 __u32 ica; 140 __u32 iua; 141 __u32 ioa; 142 __u32 ios; 143 __u32 coef[4]; 144 __u32 bo_handles[4]; 145 __u32 in_sync; 146 __u32 out_sync; 147 __u32 flags; 148 __u64 extensions; 149 struct { 150 __u32 ioc; 151 __u32 pad; 152 } v71; 153 }; 154 struct drm_v3d_submit_csd { 155 __u32 cfg[7]; 156 __u32 coef[4]; 157 __u64 bo_handles; 158 __u32 bo_handle_count; 159 __u32 in_sync; 160 __u32 out_sync; 161 __u32 perfmon_id; 162 __u64 extensions; 163 __u32 flags; 164 __u32 pad; 165 }; 166 struct drm_v3d_indirect_csd { 167 struct drm_v3d_extension base; 168 struct drm_v3d_submit_csd submit; 169 __u32 indirect; 170 __u32 offset; 171 __u32 wg_size; 172 __u32 wg_uniform_offsets[3]; 173 }; 174 struct drm_v3d_timestamp_query { 175 struct drm_v3d_extension base; 176 __u64 offsets; 177 __u64 syncs; 178 __u32 count; 179 __u32 pad; 180 }; 181 struct drm_v3d_reset_timestamp_query { 182 struct drm_v3d_extension base; 183 __u64 syncs; 184 __u32 offset; 185 __u32 count; 186 }; 187 struct drm_v3d_copy_timestamp_query { 188 struct drm_v3d_extension base; 189 __u8 do_64bit; 190 __u8 do_partial; 191 __u8 availability_bit; 192 __u8 pad; 193 __u32 offset; 194 __u32 stride; 195 __u32 count; 196 __u64 offsets; 197 __u64 syncs; 198 }; 199 struct drm_v3d_reset_performance_query { 200 struct drm_v3d_extension base; 201 __u64 syncs; 202 __u32 count; 203 __u32 nperfmons; 204 __u64 kperfmon_ids; 205 }; 206 struct drm_v3d_copy_performance_query { 207 struct drm_v3d_extension base; 208 __u8 do_64bit; 209 __u8 do_partial; 210 __u8 availability_bit; 211 __u8 pad; 212 __u32 offset; 213 __u32 stride; 214 __u32 nperfmons; 215 __u32 ncounters; 216 __u32 count; 217 __u64 syncs; 218 __u64 kperfmon_ids; 219 }; 220 struct drm_v3d_submit_cpu { 221 __u64 bo_handles; 222 __u32 bo_handle_count; 223 __u32 flags; 224 __u64 extensions; 225 }; 226 enum { 227 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS, 228 V3D_PERFCNT_FEP_VALID_PRIMS, 229 V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS, 230 V3D_PERFCNT_FEP_VALID_QUADS, 231 V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL, 232 V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL, 233 V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS, 234 V3D_PERFCNT_TLB_QUADS_ZERO_COV, 235 V3D_PERFCNT_TLB_QUADS_NONZERO_COV, 236 V3D_PERFCNT_TLB_QUADS_WRITTEN, 237 V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD, 238 V3D_PERFCNT_PTB_PRIM_CLIP, 239 V3D_PERFCNT_PTB_PRIM_REV, 240 V3D_PERFCNT_QPU_IDLE_CYCLES, 241 V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER, 242 V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG, 243 V3D_PERFCNT_QPU_CYCLES_VALID_INSTR, 244 V3D_PERFCNT_QPU_CYCLES_TMU_STALL, 245 V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL, 246 V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL, 247 V3D_PERFCNT_QPU_IC_HIT, 248 V3D_PERFCNT_QPU_IC_MISS, 249 V3D_PERFCNT_QPU_UC_HIT, 250 V3D_PERFCNT_QPU_UC_MISS, 251 V3D_PERFCNT_TMU_TCACHE_ACCESS, 252 V3D_PERFCNT_TMU_TCACHE_MISS, 253 V3D_PERFCNT_VPM_VDW_STALL, 254 V3D_PERFCNT_VPM_VCD_STALL, 255 V3D_PERFCNT_BIN_ACTIVE, 256 V3D_PERFCNT_RDR_ACTIVE, 257 V3D_PERFCNT_L2T_HITS, 258 V3D_PERFCNT_L2T_MISSES, 259 V3D_PERFCNT_CYCLE_COUNT, 260 V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER, 261 V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT, 262 V3D_PERFCNT_PTB_PRIMS_BINNED, 263 V3D_PERFCNT_AXI_WRITES_WATCH_0, 264 V3D_PERFCNT_AXI_READS_WATCH_0, 265 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0, 266 V3D_PERFCNT_AXI_READ_STALLS_WATCH_0, 267 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0, 268 V3D_PERFCNT_AXI_READ_BYTES_WATCH_0, 269 V3D_PERFCNT_AXI_WRITES_WATCH_1, 270 V3D_PERFCNT_AXI_READS_WATCH_1, 271 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1, 272 V3D_PERFCNT_AXI_READ_STALLS_WATCH_1, 273 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1, 274 V3D_PERFCNT_AXI_READ_BYTES_WATCH_1, 275 V3D_PERFCNT_TLB_PARTIAL_QUADS, 276 V3D_PERFCNT_TMU_CONFIG_ACCESSES, 277 V3D_PERFCNT_L2T_NO_ID_STALL, 278 V3D_PERFCNT_L2T_COM_QUE_STALL, 279 V3D_PERFCNT_L2T_TMU_WRITES, 280 V3D_PERFCNT_TMU_ACTIVE_CYCLES, 281 V3D_PERFCNT_TMU_STALLED_CYCLES, 282 V3D_PERFCNT_CLE_ACTIVE, 283 V3D_PERFCNT_L2T_TMU_READS, 284 V3D_PERFCNT_L2T_CLE_READS, 285 V3D_PERFCNT_L2T_VCD_READS, 286 V3D_PERFCNT_L2T_TMUCFG_READS, 287 V3D_PERFCNT_L2T_SLC0_READS, 288 V3D_PERFCNT_L2T_SLC1_READS, 289 V3D_PERFCNT_L2T_SLC2_READS, 290 V3D_PERFCNT_L2T_TMU_W_MISSES, 291 V3D_PERFCNT_L2T_TMU_R_MISSES, 292 V3D_PERFCNT_L2T_CLE_MISSES, 293 V3D_PERFCNT_L2T_VCD_MISSES, 294 V3D_PERFCNT_L2T_TMUCFG_MISSES, 295 V3D_PERFCNT_L2T_SLC0_MISSES, 296 V3D_PERFCNT_L2T_SLC1_MISSES, 297 V3D_PERFCNT_L2T_SLC2_MISSES, 298 V3D_PERFCNT_CORE_MEM_WRITES, 299 V3D_PERFCNT_L2T_MEM_WRITES, 300 V3D_PERFCNT_PTB_MEM_WRITES, 301 V3D_PERFCNT_TLB_MEM_WRITES, 302 V3D_PERFCNT_CORE_MEM_READS, 303 V3D_PERFCNT_L2T_MEM_READS, 304 V3D_PERFCNT_PTB_MEM_READS, 305 V3D_PERFCNT_PSE_MEM_READS, 306 V3D_PERFCNT_TLB_MEM_READS, 307 V3D_PERFCNT_GMP_MEM_READS, 308 V3D_PERFCNT_PTB_W_MEM_WORDS, 309 V3D_PERFCNT_TLB_W_MEM_WORDS, 310 V3D_PERFCNT_PSE_R_MEM_WORDS, 311 V3D_PERFCNT_TLB_R_MEM_WORDS, 312 V3D_PERFCNT_TMU_MRU_HITS, 313 V3D_PERFCNT_COMPUTE_ACTIVE, 314 V3D_PERFCNT_NUM, 315 }; 316 #define DRM_V3D_MAX_PERF_COUNTERS 32 317 struct drm_v3d_perfmon_create { 318 __u32 id; 319 __u32 ncounters; 320 __u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 321 }; 322 struct drm_v3d_perfmon_destroy { 323 __u32 id; 324 }; 325 struct drm_v3d_perfmon_get_values { 326 __u32 id; 327 __u32 pad; 328 __u64 values_ptr; 329 }; 330 #define DRM_V3D_PERFCNT_MAX_NAME 64 331 #define DRM_V3D_PERFCNT_MAX_CATEGORY 32 332 #define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256 333 struct drm_v3d_perfmon_get_counter { 334 __u8 counter; 335 __u8 name[DRM_V3D_PERFCNT_MAX_NAME]; 336 __u8 category[DRM_V3D_PERFCNT_MAX_CATEGORY]; 337 __u8 description[DRM_V3D_PERFCNT_MAX_DESCRIPTION]; 338 __u8 reserved[7]; 339 }; 340 #ifdef __cplusplus 341 } 342 #endif 343 #endif 344