xref: /aosp_15_r20/external/coreboot/Documentation/arch/x86/index.md (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1# x86 architecture documentation
2
3This section contains documentation about coreboot on x86 architecture.
4
5```{toctree}
6:maxdepth: 1
7
8x86 PAE support <pae.md>
9```
10
11## State of x86_64 support
12Some SOCs now support 64bit mode. Search for HAVE_X86_64_SUPPORT in Kconfig.
13
14In order to add support for x86_64 the following assumptions were made:
15* The CPU supports long mode
16* All memory returned by malloc must be below 4GiB in physical memory
17* All code that is to be run must be below 4GiB in physical memory
18* The high dword of pointers is always zero
19* The reference implementation is qemu
20* x86 payloads are loaded below 4GiB in physical memory and are jumped
21  to in *protected mode*
22
23## Assumptions for all stages using the reference implementation
24* 0-4GiB are identity mapped using 2MiB-pages as WB
25* Memory above 4GiB isn't accessible
26* page tables reside in memory mapped ROM
27* A stage can install new page tables in RAM
28
29## Page tables
30A `pagetables` cbfs file is generated based on an assembly file.
31
32To generate the static page tables it must know the physical address where to
33place the file.
34
35The page tables contains the following structure:
36* PML4E pointing to PDPE
37* PDPE with *$n* entries each pointing to PDE
38* *$n* PDEs with 512 entries each
39
40At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
41
42## Basic x86_64 support
43Basic support for x86_64 has been implemented for QEMU mainboard target.
44
45## Reference implementation
46The reference implementation is
47```{toctree}
48:maxdepth: 1
49
50QEMU i440fx <../../mainboard/emulation/qemu-i440fx.md>
51QEMU Q35 <../../mainboard/emulation/qemu-q35.md>
52```
53
54## TODO
55* Identity map memory above 4GiB in ramstage
56
57## Future work
58
591. Fine grained page tables for SMM:
60   * Must not have execute and write permissions for the same page.
61   * Must allow only that TSEG pages can be marked executable
622. Support 64bit PCI BARs above 4GiB
633. Place and run code above 4GiB
64
65## Porting other boards
66* Fix compilation errors
67* Test how well CAR works with x86_64 and paging
68* Improve mode switches
69
70## Known problems on real hardware
71
72Running VGA rom directly fails. Yabel works fine though.
73
74## Known bugs on KVM enabled qemu
75
76The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues
77when using KVM mode on some machines. The workaround is to *not* place
78page-tables in ROM, as done in
79[CB:49228](https://review.coreboot.org/c/coreboot/+/49228).
80
81Here's a list of known issues:
82
83* After entering long mode, the FPU doesn't work anymore, including accessing
84  MMX registers. It works fine before entering long mode. It works fine when
85  switching back to protected mode. Other registers, like SSE registers, are
86  working fine.
87* Reading from virtual memory, when the page tables are stored in ROM, causes
88  the MMU to abort the "page table walking" mechanism when the lower address
89  bits of the virtual address to be translated have a specific pattern.
90  Instead of loading the correct physical page, the one containing the
91  page tables in ROM will be loaded and used, which breaks code and data as
92  the page table doesn't contain the expected data. This in turn leads to
93  undefined behaviour whenever the 'wrong' address is being read.
94* Disabling paging in compatibility mode crashes the CPU.
95* Returning from long mode to compatibility mode crashes the CPU.
96* Entering long mode crashes on AMD host platforms.
97