1# Cavium bootflow 2 3The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller. 4It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get 5the position of the bootstage in flash. It then loads 192KiB from flash into 6L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as 7the signature of the bootstage isn't verified. 8The **BOOTROM** can do AES decryption for obfuscation or verify the signature 9of the bootstage. Both features aren't used and won't be described any further. 10 11* The typical position of bootstage in flash is at address **0x20000**. 12* The entry point in physical DRAM is at address **0x100000**. 13 14## Layout 15 16![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow] 17 18[cavium_bootflow]: cavium_bootflow.png 19 20
