1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/cache.h>
4 #include <arch/lib_helpers.h>
5 #include <arch/smc.h>
6 #include <smbios.h>
7 #include <stdio.h>
8
smbios_processor_id(u32 * processor_id)9 static void smbios_processor_id(u32 *processor_id)
10 {
11 uint32_t jep106code, soc_revision;
12 uint64_t midr_el1;
13
14 if (smccc_supports_arch_soc_id()) {
15 smccc_arch_soc_id(&jep106code, &soc_revision);
16 processor_id[0] = jep106code;
17 processor_id[1] = soc_revision;
18 } else {
19 midr_el1 = raw_read_midr_el1();
20 processor_id[0] = midr_el1;
21 processor_id[1] = 0;
22 }
23 }
24
smbios_processor_manufacturer(u8 * start)25 static int smbios_processor_manufacturer(u8 *start)
26 {
27 char midr_el1_implementer;
28 char buf[32];
29
30 // [31:24] - Implementer code
31 midr_el1_implementer = (raw_read_midr_el1() & 0xff000000) >> 24;
32
33 snprintf(buf, sizeof(buf), "CPU implementer %x", midr_el1_implementer);
34 return smbios_add_string(start, buf);
35 }
36
smbios_processor_name(u8 * start)37 static int smbios_processor_name(u8 *start)
38 {
39 uint16_t midr_el1_partnumber;
40 char buf[32];
41
42 // [15:4] - PartNum
43 midr_el1_partnumber = (raw_read_midr_el1() & 0xfff0) >> 4;
44
45 snprintf(buf, sizeof(buf), "ARMv8 Processor rev %d", midr_el1_partnumber);
46 return smbios_add_string(start, buf);
47 }
48
49 #define MAX_CPUS_ENABLED(cpus) (cpus > 0xff ? 0xff : cpus)
50
51 /* NOTE: Not handling big.LITTLE clusters. Consider using MP services (not yet) or the DSU. */
smbios_write_type4(unsigned long * current,int handle)52 int smbios_write_type4(unsigned long *current, int handle)
53 {
54 static unsigned int cnt = 0;
55 char buf[8];
56 uint16_t characteristics = 0;
57 unsigned int cpu_voltage;
58
59 struct smbios_type4 *t = smbios_carve_table(*current, SMBIOS_PROCESSOR_INFORMATION,
60 sizeof(*t), handle);
61
62 snprintf(buf, sizeof(buf), "CPU%d", cnt++);
63 t->socket_designation = smbios_add_string(t->eos, buf);
64
65 smbios_processor_id(t->processor_id);
66 t->processor_manufacturer = smbios_processor_manufacturer(t->eos);
67 t->processor_version = smbios_processor_name(t->eos);
68 t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2;
69 t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8;
70 t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
71
72 smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2);
73 t->core_count = MAX_CPUS_ENABLED(t->core_count2);
74 t->thread_count = MAX_CPUS_ENABLED(t->thread_count2);
75 /* Assume we always enable all cores */
76 t->core_enabled = t->core_count;
77 t->core_enabled2 = t->core_count2;
78 t->l1_cache_handle = 0xffff;
79 t->l2_cache_handle = 0xffff;
80 t->l3_cache_handle = 0xffff;
81 t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number());
82 t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED;
83 t->processor_upgrade = PROCESSOR_UPGRADE_UNKNOWN;
84
85 t->external_clock = smbios_processor_external_clock();
86 if (t->external_clock == 0)
87 t->external_clock = (raw_read_cntfrq_el0() / 1000 / 1000);
88
89 t->current_speed = smbios_cpu_get_current_speed_mhz();
90
91 /* This field identifies a capability for the system, not the processor itself. */
92 t->max_speed = smbios_cpu_get_max_speed_mhz();
93
94 /* TODO: Are "Enhanced Virtualization" (by EL2) and "Power/Performance Control" supported? */
95 characteristics |= PROCESSOR_64BIT_CAPABLE;
96 characteristics |= BIT(5); /* Execute Protection */
97
98 if (t->core_count > 1)
99 characteristics |= PROCESSOR_MULTI_CORE;
100 if (t->thread_count > 1)
101 characteristics |= BIT(4); /* BIT4: Hardware Thread */
102 if (smccc_supports_arch_soc_id())
103 characteristics |= BIT(9); /* Arm64 SoC ID */
104
105 t->processor_characteristics = characteristics | smbios_processor_characteristics();
106
107 cpu_voltage = smbios_cpu_get_voltage();
108 if (cpu_voltage > 0)
109 t->voltage = 0x80 | cpu_voltage;
110
111 const int len = smbios_full_table_len(&t->header, t->eos);
112 *current += len;
113 return len;
114 }
115
smbios_write_type7_cache_parameters(unsigned long * current,int * handle,int * max_struct_size,struct smbios_type4 * type4)116 int smbios_write_type7_cache_parameters(unsigned long *current,
117 int *handle,
118 int *max_struct_size,
119 struct smbios_type4 *type4)
120 {
121 enum cache_level level = CACHE_L1;
122 int h;
123 int len = 0;
124
125 while (1) {
126 enum smbios_cache_type type;
127 struct cache_info info;
128
129 const u8 cache_type = cpu_get_cache_type(level);
130 /* No more caches in the system */
131 if (!cache_type)
132 break;
133
134 switch (cache_type) {
135 case CACHE_INSTRUCTION:
136 type = SMBIOS_CACHE_TYPE_INSTRUCTION;
137 cpu_get_cache_info(level, cache_type, &info);
138 break;
139 case CACHE_DATA:
140 type = SMBIOS_CACHE_TYPE_DATA;
141 cpu_get_cache_info(level, cache_type, &info);
142 break;
143 case CACHE_SEPARATE:
144 type = SMBIOS_CACHE_TYPE_DATA;
145 cpu_get_cache_info(level, CACHE_DATA, &info);
146 h = (*handle)++;
147 update_max(len, *max_struct_size, smbios_write_type7(current, h,
148 level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity),
149 type, info.size, info.size));
150
151 type = SMBIOS_CACHE_TYPE_INSTRUCTION;
152 cpu_get_cache_info(level, CACHE_INSTRUCTION, &info);
153 break;
154 case CACHE_UNIFIED:
155 type = SMBIOS_CACHE_TYPE_UNIFIED;
156 cpu_get_cache_info(level, cache_type, &info);
157 break;
158 default:
159 type = SMBIOS_CACHE_TYPE_UNKNOWN;
160 info.size = info.associativity = 0;
161 break;
162 }
163
164 h = (*handle)++;
165 update_max(len, *max_struct_size, smbios_write_type7(current, h,
166 level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity),
167 type, info.size, info.size));
168
169 if (type4) {
170 switch (level) {
171 case 1:
172 type4->l1_cache_handle = h;
173 break;
174 case 2:
175 type4->l2_cache_handle = h;
176 break;
177 case 3:
178 type4->l3_cache_handle = h;
179 break;
180 default:
181 break;
182 }
183 }
184
185 level++;
186 }
187
188 return len;
189 }
190