1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * coreboot ACPI support - headers and defines.
5 */
6
7 #ifndef __ACPI_ACPI_H__
8 #define __ACPI_ACPI_H__
9
10 /*
11 * The type and enable fields are common in ACPI, but the
12 * values themselves are hardware implementation defined.
13 */
14 #if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES)
15 #define SLP_EN (1 << 13)
16 #define SLP_TYP_SHIFT 10
17 #define SLP_TYP (7 << SLP_TYP_SHIFT)
18 #define SLP_TYP_S0 0
19 #define SLP_TYP_S1 1
20 #define SLP_TYP_S3 5
21 #define SLP_TYP_S4 6
22 #define SLP_TYP_S5 7
23 #elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
24 #define SLP_EN (1 << 13)
25 #define SLP_TYP_SHIFT 10
26 #define SLP_TYP (7 << SLP_TYP_SHIFT)
27 #define SLP_TYP_S0 0
28 #define SLP_TYP_S1 1
29 #define SLP_TYP_S3 3
30 #define SLP_TYP_S4 4
31 #define SLP_TYP_S5 5
32 #endif
33
34 #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */
35 #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */
36 #define ACPI_DSDT_REV_1 0x01 /* DSDT revision: ACPI v1 */
37 #define ACPI_DSDT_REV_2 0x02 /* DSDT revision: ACPI v2.0 and greater */
38
39 #if !defined(__ASSEMBLER__) && !defined(__ACPI__)
40 #include <commonlib/helpers.h>
41 #include <device/device.h>
42 #include <uuid.h>
43 #include <cper.h>
44 #include <romstage_handoff.h>
45 #include <types.h>
46
47 enum acpi_device_sleep_states {
48 ACPI_DEVICE_SLEEP_D0 = 0,
49 ACPI_DEVICE_SLEEP_D1 = 1,
50 ACPI_DEVICE_SLEEP_D2 = 2,
51 ACPI_DEVICE_SLEEP_D3 = 3,
52 ACPI_DEVICE_SLEEP_D3_HOT = ACPI_DEVICE_SLEEP_D3,
53 ACPI_DEVICE_SLEEP_D3_COLD = 4,
54 ACPI_DEVICE_SLEEP_NONE = 5,
55 };
56
57 #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
58 #define ASLC "CORE" /* Must be exactly 4 bytes long! */
59
60 #define ACPI_NAME_BUFFER_SIZE 5 /* 4 chars + 1 NUL */
61
62 /*
63 * The assigned ACPI ID for the coreboot project is 'BOOT'
64 * http://www.uefi.org/acpi_id_list
65 */
66 #define COREBOOT_ACPI_ID "BOOT" /* ACPI ID for coreboot HIDs */
67
68 /* List of ACPI HID that use the coreboot ACPI ID */
69 enum coreboot_acpi_ids {
70 COREBOOT_ACPI_ID_CBTABLE = 0x0000, /* BOOT0000 */
71 COREBOOT_ACPI_ID_IGD_GMBUS_ARB = 0x0001, /* BOOT0001 */
72 COREBOOT_ACPI_ID_IGD_GMBUS_LINK = 0x0002, /* BOOT0002 */
73 COREBOOT_ACPI_ID_AMDGFX_ACP = 0x0003, /* BOOT0003 */
74 COREBOOT_ACPI_ID_MAX = 0xFFFF, /* BOOTFFFF */
75 };
76
77 enum acpi_tables {
78 /* Alphabetic list of Tables defined by ACPI and used by coreboot */
79 BERT, /* Boot Error Record Table */
80 CEDT, /* CXL Early Discovery Table */
81 DBG2, /* Debug Port Table 2 */
82 DMAR, /* DMA Remapping Table */
83 DSDT, /* Differentiated System Description Table */
84 ECDT, /* Embedded Controller Boot Resources Table */
85 EINJ, /* Error Injection Table */
86 FACS, /* Firmware ACPI Control Structure */
87 FADT, /* Fixed ACPI Description Table */
88 GTDT, /* Generic Timer Description Table */
89 HEST, /* Hardware Error Source Table */
90 HMAT, /* Heterogeneous Memory Attribute Table */
91 HPET, /* High Precision Event Timer Table */
92 IVRS, /* I/O Virtualization Reporting Structure */
93 LPIT, /* Low Power Idle Table */
94 MADT, /* Multiple APIC Description Table */
95 MCFG, /* PCI Express Memory Mapped Configuration */
96 PPTT, /* Processor Properties Topology Table */
97 RSDP, /* Root System Description Pointer */
98 RSDT, /* Root System Description Table */
99 SLIT, /* System Locality Distance Information Table */
100 SPCR, /* Serial Port Console Redirection Table */
101 SRAT, /* System Resource Affinity Table */
102 SSDT, /* Secondary System Description Table */
103 TCPA, /* Trusted Computing Platform Alliance Table */
104 TPM2, /* Trusted Platform Module 2.0 Table */
105 WDAT, /* Watchdog Action Table */
106 XSDT, /* Extended System Description Table */
107 /* Additional proprietary tables used by coreboot */
108 CRAT, /* Component Resource Attribute Table */
109 IORT, /* Input Output Remapping Table */
110 NHLT, /* Non HD audio Link Table */
111 SPMI, /* Server Platform Management Interface table */
112 VFCT /* VBIOS Fetch Table */
113 };
114
115 /* RSDP (Root System Description Pointer) */
116 typedef struct acpi_rsdp {
117 char signature[8]; /* RSDP signature */
118 u8 checksum; /* Checksum of the first 20 bytes */
119 char oem_id[6]; /* OEM ID */
120 u8 revision; /* RSDP revision */
121 u32 rsdt_address; /* Physical address of RSDT (32 bits) */
122 u32 length; /* Total RSDP length (incl. extended part) */
123 u64 xsdt_address; /* Physical address of XSDT (64 bits) */
124 u8 ext_checksum; /* Checksum of the whole table */
125 u8 reserved[3];
126 } __packed acpi_rsdp_t;
127
128 /* GAS (Generic Address Structure) */
129 typedef struct acpi_gen_regaddr {
130 u8 space_id; /* Address space ID */
131 u8 bit_width; /* Register size in bits */
132 u8 bit_offset; /* Register bit offset */
133 u8 access_size; /* Access size since ACPI 2.0c */
134 u32 addrl; /* Register address, low 32 bits */
135 u32 addrh; /* Register address, high 32 bits */
136 } __packed acpi_addr_t;
137
138 #define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */
139 #define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */
140 #define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */
141 #define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */
142 #define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */
143 #define ACPI_ADDRESS_SPACE_CMOS 5 /* SystemCMOS */
144 #define ACPI_ADDRESS_SPACE_PCI_BAR_TARGET 6 /* PciBarTarget */
145 #define ACPI_ADDRESS_SPACE_IPMI 7 /* IPMI */
146 #define ACPI_ADDRESS_SPACE_GENERAL_PURPOSE_IO 8 /* GeneralPurposeIO */
147 #define ACPI_ADDRESS_SPACE_GENERIC_SERIAL_BUS 9 /* GenericSerialBus */
148 #define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */
149 #define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */
150 #define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */
151 #define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */
152 #define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */
153 #define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */
154 #define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */
155 #define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */
156 /* 0x80-0xbf: Reserved */
157 /* 0xc0-0xff: OEM defined */
158
159 /* Access size definitions for Generic address structure */
160 #define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */
161 #define ACPI_ACCESS_SIZE_BYTE_ACCESS 1
162 #define ACPI_ACCESS_SIZE_WORD_ACCESS 2
163 #define ACPI_ACCESS_SIZE_DWORD_ACCESS 3
164 #define ACPI_ACCESS_SIZE_QWORD_ACCESS 4
165
166 /* Macros for common resource types */
167 #define ACPI_REG_MSR(address, offset, width) \
168 (acpi_addr_t){ \
169 .space_id = ACPI_ADDRESS_SPACE_FIXED, \
170 .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \
171 .addrl = address, \
172 .bit_offset = offset, \
173 .bit_width = width, \
174 }
175
176 #define ACPI_REG_UNSUPPORTED (acpi_addr_t){0}
177
178 /* Common ACPI HIDs */
179 #define ACPI_HID_FDC "PNP0700"
180 #define ACPI_HID_KEYBOARD "PNP0303"
181 #define ACPI_HID_MOUSE "PNP0F03"
182 #define ACPI_HID_COM "PNP0501"
183 #define ACPI_HID_LPT "PNP0400"
184 #define ACPI_HID_PNP "PNP0C02"
185 #define ACPI_HID_CONTAINER "PNP0A05"
186
187 /* Generic ACPI header, provided by (almost) all tables */
188 typedef struct acpi_table_header {
189 char signature[4]; /* ACPI signature (4 ASCII characters) */
190 u32 length; /* Table length in bytes (incl. header) */
191 u8 revision; /* Table version (not ACPI version!) */
192 u8 checksum; /* To make sum of entire table == 0 */
193 char oem_id[6]; /* OEM identification */
194 char oem_table_id[8]; /* OEM table identification */
195 u32 oem_revision; /* OEM revision number */
196 char asl_compiler_id[4]; /* ASL compiler vendor ID */
197 u32 asl_compiler_revision; /* ASL compiler revision number */
198 } __packed acpi_header_t;
199
200 /* A maximum number of 32 ACPI tables ought to be enough for now. */
201 #define MAX_ACPI_TABLES 32
202
203 /* RSDT (Root System Description Table) */
204 typedef struct acpi_rsdt {
205 acpi_header_t header;
206 u32 entry[MAX_ACPI_TABLES];
207 } __packed acpi_rsdt_t;
208
209 /* XSDT (Extended System Description Table) */
210 typedef struct acpi_xsdt {
211 acpi_header_t header;
212 u64 entry[MAX_ACPI_TABLES];
213 } __packed acpi_xsdt_t;
214
215 /* HPET timers */
216 typedef struct acpi_hpet {
217 acpi_header_t header;
218 u32 id;
219 acpi_addr_t addr;
220 u8 number;
221 u16 min_tick;
222 u8 attributes;
223 } __packed acpi_hpet_t;
224
225 /* MCFG (PCI Express MMIO config space BAR description table) */
226 typedef struct acpi_mcfg {
227 acpi_header_t header;
228 u8 reserved[8];
229 } __packed acpi_mcfg_t;
230
231 typedef struct acpi_tcpa {
232 acpi_header_t header;
233 u16 platform_class;
234 u32 laml;
235 u64 lasa;
236 } __packed acpi_tcpa_t;
237
238 typedef struct acpi_tpm2 {
239 acpi_header_t header;
240 u16 platform_class;
241 u8 reserved[2];
242 u64 control_area;
243 u32 start_method;
244 u8 msp[12];
245 u32 laml;
246 u64 lasa;
247 } __packed acpi_tpm2_t;
248
249 typedef struct acpi_mcfg_mmconfig {
250 u64 base_address;
251 u16 pci_segment_group_number;
252 u8 start_bus_number;
253 u8 end_bus_number;
254 u8 reserved[4];
255 } __packed acpi_mcfg_mmconfig_t;
256
257 /*
258 * CEDT (CXL Early Discovery Table)
259 * CXL spec 2.0 section 9.14.1
260 */
261 typedef struct acpi_cedt {
262 acpi_header_t header;
263 /* Followed by CEDT structures[n] */
264 } __packed acpi_cedt_t;
265
266 #define ACPI_CEDT_STRUCTURE_CHBS 0
267 #define ACPI_CEDT_STRUCTURE_CFMWS 1
268
269 #define ACPI_CEDT_CHBS_CXL_VER_1_1 0x00
270 #define ACPI_CEDT_CHBS_CXL_VER_2_0 0x01
271
272 /* CHBS: CXL Host Bridge Structure */
273 typedef struct acpi_cedt_chbs {
274 u8 type; /* Always 0, other values reserved */
275 u8 resv1;
276 u16 length; /* Length in bytes (32) */
277 u32 uid; /* CXL Host Bridge Unique ID */
278 u32 cxl_ver;
279 u32 resv2;
280 /*
281 * For CXL 1.1, the base is Downstream Port Root Complex Resource Block;
282 * For CXL 2.0, the base is CXL Host Bridge Component Registers.
283 */
284 u64 base;
285 u64 len;
286 } __packed acpi_cedt_chbs_t;
287
288 #define ACPI_CEDT_CFMWS_RESTRICTION_TYPE_2_MEM (1 << 0)
289 #define ACPI_CEDT_CFMWS_RESTRICTION_TYPE_3_MEM (1 << 1)
290 #define ACPI_CEDT_CFMWS_RESTRICTION_VOLATIL (1 << 2)
291 #define ACPI_CEDT_CFMWS_RESTRICTION_PERSISTENT (1 << 3)
292 #define ACPI_CEDT_CFMWS_RESTRICTION_FIXED (1 << 4)
293
294 /* CFMWS: CXL Fixed Memory Window Structure */
295 typedef struct acpi_cedt_cfmws {
296 u8 type; /* Type (0) */
297 u8 resv1;
298 u16 length; /* Length in bytes (32) */
299 u32 resv2;
300 u64 base_hpa; /* Base of the HPA range, 256MB aligned */
301 u64 window_size; /* Number of bytes this window represents */
302 u8 eniw; /* Encoded Number of Interleave Ways */
303 u8 interleave_arithmetic; /* Standard Modulo arithmetic (0) */
304 u16 resv3;
305 u32 hbig; /* Host Bridge Interleave Granularity */
306 u16 restriction;
307 u16 qtg_id;
308 u32 interleave_target[]; /* Interleave Target List */
309 } __packed acpi_cedt_cfmws_t;
310
311 /*
312 * HMAT (Heterogeneous Memory Attribute Table)
313 * ACPI spec 6.4 section 5.2.27
314 */
315 typedef struct acpi_hmat {
316 acpi_header_t header;
317 u32 resv;
318 /* Followed by HMAT table structure[n] */
319 } __packed acpi_hmat_t;
320
321 /* HMAT: Memory Proximity Domain Attributes structure */
322 typedef struct acpi_hmat_mpda {
323 u16 type; /* Type (0) */
324 u16 resv;
325 u32 length; /* Length in bytes (40) */
326 u16 flags;
327 u16 resv1;
328 u32 proximity_domain_initiator;
329 u32 proximity_domain_memory;
330 u32 resv2;
331 u64 resv3;
332 u64 resv4;
333 } __packed acpi_hmat_mpda_t;
334
335 /* HMAT: System Locality Latency and Bandwidth Information structure */
336 typedef struct acpi_hmat_sllbi {
337 u16 type; /* Type (1) */
338 u16 resv;
339 u32 length; /* Length in bytes */
340 u8 flags;
341 u8 data_type;
342 /*
343 * Transfer size defined as a 5-biased power of 2 exponent,
344 * when the bandwidth/latency value is achieved.
345 */
346 u8 min_transfer_size;
347 u8 resv1;
348 u32 num_initiator_domains;
349 u32 num_target_domains;
350 u32 resv2;
351 u64 entry_base_unit;
352 /* Followed by initiator proximity domain list */
353 /* Followed by target proximity domain list */
354 /* Followed by latency / bandwidth values */
355 } __packed acpi_hmat_sllbi_t;
356
357 /* HMAT: Memory Side Cache Information structure */
358 typedef struct acpi_hmat_msci {
359 u16 type; /* Type (2) */
360 u16 resv;
361 u32 length; /* Length in bytes */
362 u32 domain; /* Proximity domain for the memory */
363 u32 resv1;
364 u64 cache_size;
365 /* Describes level, associativity, write policy, cache line size */
366 u32 cache_attributes;
367 u16 resv2;
368 /*
369 * Number of SMBIOS handlers that contribute to the
370 * memory side cache physical devices
371 */
372 u16 num_handlers;
373 /* Followed by SMBIOS handlers*/
374 } __packed acpi_hmat_msci_t;
375
376 /* SRAT (System Resource Affinity Table) */
377 typedef struct acpi_srat {
378 acpi_header_t header;
379 u32 resv;
380 u64 resv1;
381 /* Followed by static resource allocation structure[n] */
382 } __packed acpi_srat_t;
383
384 #define ACPI_SRAT_STRUCTURE_LAPIC 0
385 #define ACPI_SRAT_STRUCTURE_MEM 1
386 #define ACPI_SRAT_STRUCTURE_GIA 5
387
388 /* SRAT: Processor x2APIC Structure */
389 typedef struct acpi_srat_x2apic {
390 u8 type; /* Type (0) */
391 u8 length; /* Length in bytes (16) */
392 u16 reserved; /* Reserved - Must be zero */
393 u32 proximity_domain; /* Proximity domain */
394 u32 x2apic_id; /* x2APIC ID */
395 u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */
396 u32 clock_domain; /* _CDM Clock Domain */
397 u32 reserved1; /* Reserved */
398 } __packed acpi_srat_x2apic_t;
399
400 /* SRAT: Processor Local APIC/SAPIC Affinity Structure */
401 typedef struct acpi_srat_lapic {
402 u8 type; /* Type (0) */
403 u8 length; /* Length in bytes (16) */
404 u8 proximity_domain_7_0; /* Proximity domain bits[7:0] */
405 u8 apic_id; /* Local APIC ID */
406 u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */
407 u8 local_sapic_eid; /* Local SAPIC EID */
408 u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */
409 u32 clock_domain; /* _CDM Clock Domain */
410 } __packed acpi_srat_lapic_t;
411
412 #define ACPI_SRAT_MEMORY_ENABLED (1 << 0)
413 #define ACPI_SRAT_MEMORY_HOT_PLUGGABLE (1 << 1)
414 #define ACPI_SRAT_MEMORY_NONVOLATILE (1 << 2)
415
416 /* SRAT: Memory Affinity Structure */
417 typedef struct acpi_srat_mem {
418 u8 type; /* Type (1) */
419 u8 length; /* Length in bytes (40) */
420 u32 proximity_domain; /* Proximity domain */
421 u16 resv;
422 u32 base_address_low; /* Mem range base address, low */
423 u32 base_address_high; /* Mem range base address, high */
424 u32 length_low; /* Mem range length, low */
425 u32 length_high; /* Mem range length, high */
426 u32 resv1;
427 u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2,
428 * other bits reserved to 0
429 */
430 u32 resv2[2];
431 } __packed acpi_srat_mem_t;
432
433 /* SRAT: Generic Initiator Affinity Structure (ACPI spec 6.4 section 5.2.16.6) */
434 typedef struct acpi_srat_gia {
435 u8 type; /* Type (5) */
436 u8 length; /* Length in bytes (32) */
437 u8 resv;
438 u8 dev_handle_type; /* Device handle type */
439 u32 proximity_domain; /*Proximity domain */
440 u8 dev_handle[16]; /* Device handle */
441 u32 flags;
442 u32 resv1;
443 } __packed acpi_srat_gia_t;
444
445 #define ACPI_SRAT_GIA_DEV_HANDLE_ACPI 0
446 #define ACPI_SRAT_GIA_DEV_HANDLE_PCI 1
447
448 /* SLIT (System Locality Distance Information Table) */
449 typedef struct acpi_slit {
450 acpi_header_t header;
451 /* Followed by static resource allocation 8+byte[num*num] */
452 } __packed acpi_slit_t;
453
454 /* MADT (Multiple APIC Description Table) */
455 typedef struct acpi_madt {
456 acpi_header_t header;
457 u32 lapic_addr; /* Local APIC address */
458 u32 flags; /* Multiple APIC flags */
459 } __packed acpi_madt_t;
460
461 /* MADT Feature Flags */
462 #define ACPI_MADT_PCAT_COMPAT (1 << 0)
463
464 /*
465 * LPIT (Low Power Idle Table)
466 * Conforms to "Intel Low Power S0 Idle" specification, rev 002 from July 2017.
467 */
468 typedef struct acpi_lpit {
469 acpi_header_t header;
470 } __packed acpi_lpit_t;
471
472 /* LPIT: LPI descriptor flags */
473 typedef struct acpi_lpi_flags {
474 uint32_t disabled : 1;
475 uint32_t counter_not_available : 1;
476 uint32_t reserved : 30;
477 } __packed acpi_lpi_desc_flags_t;
478
479 /* LPIT: LPI descriptor types */
480 enum acpi_lpi_desc_type {
481 ACPI_LPI_DESC_TYPE_NATIVE_CSTATE = 0x00,
482 /* type >= 1 reserved */
483 };
484
485 /* LPIT: LPI descriptor header */
486 typedef struct acpi_lpi_desc_hdr {
487 uint32_t type;
488 uint32_t length;
489 uint16_t uid;
490 uint16_t reserved;
491 } __packed acpi_lpi_desc_hdr_t;
492
493 #define ACPI_LPIT_CTR_FREQ_TSC 0
494
495
496 /* LPIT: Native C-state instruction based LPI structure */
497 typedef struct acpi_lpi_desc_ncst {
498 acpi_lpi_desc_hdr_t header;
499 acpi_lpi_desc_flags_t flags;
500 acpi_addr_t entry_trigger; /* Entry trigger C-state */
501 uint32_t min_residency; /* Minimum residency or "break-even" in microseconds */
502 uint32_t max_latency; /* Worst case exit latency in microseconds */
503 acpi_addr_t residency_counter;
504 uint64_t counter_frequency; /* Frequency in cycles per second - 0 means TSC freq */
505 } __packed acpi_lpi_desc_ncst_t;
506
507 #define VFCT_VBIOS_CHECKSUM_OFFSET 0x21
508
509 /* VFCT image header */
510 typedef struct acpi_vfct_image_hdr {
511 u32 PCIBus;
512 u32 PCIDevice;
513 u32 PCIFunction;
514 u16 VendorID;
515 u16 DeviceID;
516 u16 SSVID;
517 u16 SSID;
518 u32 Revision;
519 u32 ImageLength;
520 u8 VbiosContent[]; // dummy - copy VBIOS here
521 } __packed acpi_vfct_image_hdr_t;
522
523 /* VFCT (VBIOS Fetch Table) */
524 typedef struct acpi_vfct {
525 acpi_header_t header;
526 u8 TableUUID[16];
527 u32 VBIOSImageOffset;
528 u32 Lib1ImageOffset;
529 u32 Reserved[4];
530 acpi_vfct_image_hdr_t image_hdr;
531 } __packed acpi_vfct_t;
532
533 typedef struct acpi_ivrs_info {
534 } __packed acpi_ivrs_info_t;
535
536 /* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 10h */
537 typedef struct acpi_ivrs_ivhd {
538 uint8_t type;
539 uint8_t flags;
540 uint16_t length;
541 uint16_t device_id;
542 uint16_t capability_offset;
543 uint32_t iommu_base_low;
544 uint32_t iommu_base_high;
545 uint16_t pci_segment_group;
546 uint16_t iommu_info;
547 uint32_t iommu_feature_info;
548 uint8_t entry[];
549 } __packed acpi_ivrs_ivhd_t;
550
551 /* IVRS (I/O Virtualization Reporting Structure) Type 10h */
552 typedef struct acpi_ivrs {
553 acpi_header_t header;
554 uint32_t iv_info;
555 uint32_t reserved[2];
556 struct acpi_ivrs_ivhd ivhd;
557 } __packed acpi_ivrs_t;
558
559 /* CRAT (Component Resource Affinity Table Structure) */
560 struct acpi_crat_header {
561 acpi_header_t header;
562 uint32_t total_entries;
563 uint16_t num_nodes;
564 uint8_t reserved[6];
565 } __packed;
566
567 /* IVHD Type 11h IOMMU Attributes */
568 typedef struct ivhd11_iommu_attr {
569 uint32_t reserved1 : 13;
570 uint32_t perf_counters : 4;
571 uint32_t perf_counter_banks : 6;
572 uint32_t msi_num_ppr : 5;
573 uint32_t reserved2 : 4;
574 } __packed ivhd11_iommu_attr_t;
575
576 /* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 11h */
577 typedef struct acpi_ivrs_ivhd_11 {
578 uint8_t type;
579 uint8_t flags;
580 uint16_t length;
581 uint16_t device_id;
582 uint16_t capability_offset;
583 uint32_t iommu_base_low;
584 uint32_t iommu_base_high;
585 uint16_t pci_segment_group;
586 uint16_t iommu_info;
587 struct ivhd11_iommu_attr iommu_attributes;
588 uint32_t efr_reg_image_low;
589 uint32_t efr_reg_image_high;
590 uint32_t reserved[2];
591 uint8_t entry[];
592 } __packed acpi_ivrs_ivhd11_t;
593
594 enum dev_scope_type {
595 SCOPE_PCI_ENDPOINT = 1,
596 SCOPE_PCI_SUB = 2,
597 SCOPE_IOAPIC = 3,
598 SCOPE_MSI_HPET = 4,
599 SCOPE_ACPI_NAMESPACE_DEVICE = 5
600 };
601
602 typedef struct dev_scope {
603 u8 type;
604 u8 length;
605 u8 reserved[2];
606 u8 enumeration;
607 u8 start_bus;
608 struct {
609 u8 dev;
610 u8 fn;
611 } __packed path[];
612 } __packed dev_scope_t;
613
614 enum dmar_type {
615 DMAR_DRHD = 0,
616 DMAR_RMRR = 1,
617 DMAR_ATSR = 2,
618 DMAR_RHSA = 3,
619 DMAR_ANDD = 4,
620 DMAR_SATC = 5
621 };
622
623 enum {
624 DRHD_INCLUDE_PCI_ALL = 1
625 };
626
627 enum {
628 ATC_REQUIRED = 1
629 };
630
631 enum dmar_flags {
632 DMAR_INTR_REMAP = 1 << 0,
633 DMAR_X2APIC_OPT_OUT = 1 << 1,
634 DMA_CTRL_PLATFORM_OPT_IN_FLAG = 1 << 2,
635 };
636
637 typedef struct dmar_entry {
638 u16 type;
639 u16 length;
640 u8 flags;
641 u8 size;
642 u16 segment;
643 u64 bar;
644 } __packed dmar_entry_t;
645
646 typedef struct dmar_rmrr_entry {
647 u16 type;
648 u16 length;
649 u16 reserved;
650 u16 segment;
651 u64 bar;
652 u64 limit;
653 } __packed dmar_rmrr_entry_t;
654
655 typedef struct dmar_atsr_entry {
656 u16 type;
657 u16 length;
658 u8 flags;
659 u8 reserved;
660 u16 segment;
661 } __packed dmar_atsr_entry_t;
662
663 typedef struct dmar_rhsa_entry {
664 u16 type;
665 u16 length;
666 u32 reserved;
667 u64 base_address;
668 u32 proximity_domain;
669 } __packed dmar_rhsa_entry_t;
670
671 typedef struct dmar_andd_entry {
672 u16 type;
673 u16 length;
674 u8 reserved[3];
675 u8 device_number;
676 u8 device_name[];
677 } __packed dmar_andd_entry_t;
678
679 typedef struct dmar_satc_entry {
680 u16 type;
681 u16 length;
682 u8 flags;
683 u8 reserved;
684 u16 segment_number;
685 } __packed dmar_satc_entry_t;
686
687 /* DMAR (DMA Remapping Reporting Structure) */
688 typedef struct acpi_dmar {
689 acpi_header_t header;
690 u8 host_address_width;
691 u8 flags;
692 u8 reserved[10];
693 dmar_entry_t structure[];
694 } __packed acpi_dmar_t;
695
696 /* MADT: APIC Structure Types */
697 enum acpi_apic_types {
698 LOCAL_APIC, /* Processor local APIC */
699 IO_APIC, /* I/O APIC */
700 IRQ_SOURCE_OVERRIDE, /* Interrupt source override */
701 NMI_TYPE, /* NMI source */
702 LOCAL_APIC_NMI, /* Local APIC NMI */
703 LAPIC_ADDRESS_OVERRIDE, /* Local APIC address override */
704 IO_SAPIC, /* I/O SAPIC */
705 LOCAL_SAPIC, /* Local SAPIC */
706 PLATFORM_IRQ_SOURCES, /* Platform interrupt sources */
707 LOCAL_X2APIC, /* Processor local x2APIC */
708 LOCAL_X2APIC_NMI, /* Local x2APIC NMI */
709 GICC, /* GIC CPU Interface */
710 GICD, /* GIC Distributor */
711 GIC_MSI_FRAME, /* GIC MSI Frame */
712 GICR, /* GIC Redistributor */
713 GIC_ITS, /* Interrupt Translation Service */
714 /* 0x10-0x7f: Reserved */
715 /* 0x80-0xff: Reserved for OEM use */
716 };
717
718 /* MADT: Processor Local APIC Structure */
719 typedef struct acpi_madt_lapic {
720 u8 type; /* Type (0) */
721 u8 length; /* Length in bytes (8) */
722 u8 processor_id; /* ACPI processor ID */
723 u8 apic_id; /* Local APIC ID */
724 u32 flags; /* Local APIC flags */
725 } __packed acpi_madt_lapic_t;
726
727 #define ACPI_MADT_MAX_LAPIC_ID 0xfe
728
729 /* MADT Local APIC Feature Flags */
730 #define ACPI_MADT_LAPIC_ENABLED (1 << 0)
731 #define ACPI_MADT_LAPIC_ONLINE_CAPABLE (1 << 1)
732
733 /* MADT: Local APIC NMI Structure */
734 typedef struct acpi_madt_lapic_nmi {
735 u8 type; /* Type (4) */
736 u8 length; /* Length in bytes (6) */
737 u8 processor_id; /* ACPI processor ID */
738 u16 flags; /* MPS INTI flags */
739 u8 lint; /* Local APIC LINT# */
740 } __packed acpi_madt_lapic_nmi_t;
741
742 #define ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS 0xff
743 #define ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS ((u32)-1)
744
745 /* MADT: I/O APIC Structure */
746 typedef struct acpi_madt_ioapic {
747 u8 type; /* Type (1) */
748 u8 length; /* Length in bytes (12) */
749 u8 ioapic_id; /* I/O APIC ID */
750 u8 reserved;
751 u32 ioapic_addr; /* I/O APIC address */
752 u32 gsi_base; /* Global system interrupt base */
753 } __packed acpi_madt_ioapic_t;
754
755 #define MP_IRQ_POLARITY_DEFAULT 0x0
756 #define MP_IRQ_POLARITY_HIGH 0x1
757 #define MP_IRQ_POLARITY_LOW 0x3
758 #define MP_IRQ_POLARITY_MASK 0x3
759 #define MP_IRQ_TRIGGER_DEFAULT 0x0
760 #define MP_IRQ_TRIGGER_EDGE 0x4
761 #define MP_IRQ_TRIGGER_LEVEL 0xc
762 #define MP_IRQ_TRIGGER_MASK 0xc
763
764 /* MADT: Interrupt Source Override Structure */
765 typedef struct acpi_madt_irqoverride {
766 u8 type; /* Type (2) */
767 u8 length; /* Length in bytes (10) */
768 u8 bus; /* ISA (0) */
769 u8 source; /* Bus-relative int. source (IRQ) */
770 u32 gsirq; /* Global system interrupt */
771 u16 flags; /* MPS INTI flags */
772 } __packed acpi_madt_irqoverride_t;
773
774 /* MADT: Processor Local x2APIC Structure */
775 typedef struct acpi_madt_lx2apic {
776 u8 type; /* Type (9) */
777 u8 length; /* Length in bytes (16) */
778 u16 reserved;
779 u32 x2apic_id; /* Local x2APIC ID */
780 u32 flags; /* Same as Local APIC flags */
781 u32 processor_id; /* ACPI processor ID */
782 } __packed acpi_madt_lx2apic_t;
783
784 /* MADT: Processor Local x2APIC NMI Structure */
785 typedef struct acpi_madt_lx2apic_nmi {
786 u8 type; /* Type (10) */
787 u8 length; /* Length in bytes (12) */
788 u16 flags; /* Same as MPS INTI flags */
789 u32 processor_id; /* ACPI processor ID */
790 u8 lint; /* Local APIC LINT# */
791 u8 reserved[3];
792 } __packed acpi_madt_lx2apic_nmi_t;
793
794 /* MADT: GIC CPU Interface (GICC) Structure 6.5 */
795 struct gicc_flags {
796 uint32_t enabled : 1;
797 /* 0 - Level-triggered | 1 - Edge-Triggered */
798 uint32_t performance_interrupt_mode : 1;
799 uint32_t vgic_maintenance_interrupt_mode : 1;
800 uint32_t online_capable : 1;
801 uint32_t reserved : 28;
802 };
803 _Static_assert(sizeof(struct gicc_flags) == sizeof(uint32_t), "Wrong gicc_flags size\n");
804
805 typedef struct acpi_gicc {
806 uint8_t type;
807 uint8_t length;
808 uint16_t reserved;
809 uint32_t cpu_interface_number;
810 uint32_t acpi_processor_uid;
811 struct gicc_flags flags;
812 uint32_t parking_protocol_version;
813 uint32_t performance_interrupt_gsiv;
814 uint64_t parked_address;
815 uint64_t physical_base_address; /* GIC v1/v2 or GIC v3/v4 in v2 compat mode */
816 uint64_t gicv;
817 uint64_t gich;
818 uint32_t vgic_maintenance_interrupt;
819 uint64_t gicr_base_address; /* Only GIC v3 and above */
820 uint64_t mpidr;
821 uint8_t processor_power_efficiency_class;
822 uint8_t reserved1;
823 uint16_t spe_overflow_interrupt;
824 uint16_t trbe_interrupt;
825 } __packed acpi_madt_gicc_t;
826 _Static_assert(sizeof(acpi_madt_gicc_t) == 82, "Wrong acpi_madt_gicc_t size\n");
827
828 /* MADT: GIC Distributor (GICD) Structure */
829 typedef struct acpi_gicd {
830 uint8_t type;
831 uint8_t length;
832 uint16_t reserved1;
833 uint32_t gic_id;
834 uint64_t physical_base_address;
835 uint32_t system_vector_base;
836 uint8_t gic_version;
837 uint8_t reserved2[3];
838 } __packed acpi_madt_gicd_t;
839 _Static_assert(sizeof(acpi_madt_gicd_t) == 24, "Wrong acpi_madt_gicd_t size\n");
840
841 /* MADT: GIC MSI Frame Structure */
842 struct gic_msi_flags {
843 uint32_t spi_count_select : 1;
844 uint32_t reserved : 31;
845 };
846 _Static_assert(sizeof(struct gic_msi_flags) == sizeof(uint32_t), "Wrong gic_msi_flags size\n");
847
848 typedef struct acpi_gic_msi {
849 uint8_t type;
850 uint8_t length;
851 uint16_t reserved;
852 uint32_t gic_msi_frame_id;
853 uint64_t physical_base_address;
854 struct gic_msi_flags flags;
855 uint16_t spi_count;
856 uint16_t spi_base;
857 } __packed acpi_gic_msi_t;
858 _Static_assert(sizeof(acpi_gic_msi_t) == 24, "Wrong acpi_gic_msi_t size\n");
859
860 /* MADT: GIC Redistributor (GICR) Structure */
861 typedef struct acpi_girr {
862 uint8_t type;
863 uint8_t length;
864 uint16_t reserved;
865 uint64_t discovery_range_base_address;
866 uint32_t discovery_range_length;
867 } __packed acpi_madt_gicr_t;
868 _Static_assert(sizeof(acpi_madt_gicr_t) == 16, "Wrong acpi_madt_gicr_t size\n");
869
870 /* MADT: GIC Interrupt Translation Service (ITS) Structure */
871 typedef struct acpi_gic_its {
872 uint8_t type;
873 uint8_t length;
874 uint16_t reserved;
875 uint32_t gic_its_id;
876 uint64_t physical_base_address;
877 uint32_t reserved2;
878 } __packed acpi_madt_gic_its_t;
879 _Static_assert(sizeof(acpi_madt_gic_its_t) == 20, "Wrong MADT acpi_madt_gic_its_t size\n");
880
881 #define ACPI_DBG2_PORT_SERIAL 0x8000
882 #define ACPI_DBG2_PORT_SERIAL_16550_IO_ONLY 0x0000
883 #define ACPI_DBG2_PORT_SERIAL_16550_DBGP 0x0001
884 #define ACPI_DBG2_PORT_SERIAL_ARM_PL011 0x0003
885 #define ACPI_DBG2_PORT_SERIAL_ARM_SBSA 0x000e
886 #define ACPI_DBG2_PORT_SERIAL_ARM_DDC 0x000f
887 #define ACPI_DBG2_PORT_SERIAL_BCM2835 0x0010
888 #define ACPI_DBG2_PORT_SERIAL_16550 0x0012
889 #define ACPI_DBG2_PORT_IEEE1394 0x8001
890 #define ACPI_DBG2_PORT_IEEE1394_STANDARD 0x0000
891 #define ACPI_DBG2_PORT_USB 0x8002
892 #define ACPI_DBG2_PORT_USB_XHCI 0x0000
893 #define ACPI_DBG2_PORT_USB_EHCI 0x0001
894 #define ACPI_DBG2_PORT_NET 0x8003
895
896 /* DBG2: Microsoft Debug Port Table 2 header */
897 typedef struct acpi_dbg2_header {
898 acpi_header_t header;
899 uint32_t devices_offset;
900 uint32_t devices_count;
901 } __packed acpi_dbg2_header_t;
902
903 /* DBG2: Microsoft Debug Port Table 2 device entry */
904 typedef struct acpi_dbg2_device {
905 uint8_t revision;
906 uint16_t length;
907 uint8_t address_count;
908 uint16_t namespace_string_length;
909 uint16_t namespace_string_offset;
910 uint16_t oem_data_length;
911 uint16_t oem_data_offset;
912 uint16_t port_type;
913 uint16_t port_subtype;
914 uint8_t reserved[2];
915 uint16_t base_address_offset;
916 uint16_t address_size_offset;
917 } __packed acpi_dbg2_device_t;
918
919 /* FADT (Fixed ACPI Description Table) */
920 typedef struct acpi_fadt {
921 acpi_header_t header;
922 u32 firmware_ctrl;
923 u32 dsdt;
924 u8 reserved; /* Should be 0 */
925 u8 preferred_pm_profile;
926 u16 sci_int;
927 u32 smi_cmd;
928 u8 acpi_enable;
929 u8 acpi_disable;
930 u8 s4bios_req;
931 u8 pstate_cnt;
932 u32 pm1a_evt_blk;
933 u32 pm1b_evt_blk;
934 u32 pm1a_cnt_blk;
935 u32 pm1b_cnt_blk;
936 u32 pm2_cnt_blk;
937 u32 pm_tmr_blk;
938 u32 gpe0_blk;
939 u32 gpe1_blk;
940 u8 pm1_evt_len;
941 u8 pm1_cnt_len;
942 u8 pm2_cnt_len;
943 u8 pm_tmr_len;
944 u8 gpe0_blk_len;
945 u8 gpe1_blk_len;
946 u8 gpe1_base;
947 u8 cst_cnt;
948 u16 p_lvl2_lat;
949 u16 p_lvl3_lat;
950 u16 flush_size;
951 u16 flush_stride;
952 u8 duty_offset;
953 u8 duty_width;
954 u8 day_alrm;
955 u8 mon_alrm;
956 u8 century;
957 u16 iapc_boot_arch;
958 u8 res2;
959 u32 flags;
960 acpi_addr_t reset_reg;
961 u8 reset_value;
962 u16 ARM_boot_arch; /* Must be zero if ACPI Revision <= 5.0 */
963 u8 FADT_MinorVersion; /* Must be zero if ACPI Revision <= 5.0 */
964 u32 x_firmware_ctl_l;
965 u32 x_firmware_ctl_h;
966 u32 x_dsdt_l;
967 u32 x_dsdt_h;
968 acpi_addr_t x_pm1a_evt_blk;
969 acpi_addr_t x_pm1b_evt_blk;
970 acpi_addr_t x_pm1a_cnt_blk;
971 acpi_addr_t x_pm1b_cnt_blk;
972 acpi_addr_t x_pm2_cnt_blk;
973 acpi_addr_t x_pm_tmr_blk;
974 acpi_addr_t x_gpe0_blk;
975 acpi_addr_t x_gpe1_blk;
976 /* Revision 5 */
977 acpi_addr_t sleep_control_reg;
978 acpi_addr_t sleep_status_reg;
979 /* Revision 6 */
980 u64 hypervisor_vendor_identity;
981 } __packed acpi_fadt_t;
982
983 /* FADT TABLE Revision values */
984 #define ACPI_FADT_REV_ACPI_1 1
985 #define ACPI_FADT_REV_ACPI_2 3
986 #define ACPI_FADT_REV_ACPI_3 4
987 #define ACPI_FADT_REV_ACPI_4 4
988 #define ACPI_FADT_REV_ACPI_5 5
989 #define ACPI_FADT_REV_ACPI_6 6
990
991 /* FADT Minor Version value:
992 * Bits 0-3: minor version
993 * Bits 4-7: Errata
994 * value of 1 means this is compatible with Errata A,
995 * value of 2 would be compatible with Errata B, and so on
996 * Version 6.3 Errata A would be: (1 << 4) | 3
997 */
998 #define ACPI_FADT_MINOR_VERSION_0 0 /* coreboot currently use this version */
999
1000 /* Flags for p_lvl2_lat and p_lvl3_lat */
1001 #define ACPI_FADT_C2_NOT_SUPPORTED 101
1002 #define ACPI_FADT_C3_NOT_SUPPORTED 1001
1003
1004 /* FADT Feature Flags */
1005 #define ACPI_FADT_WBINVD (1 << 0)
1006 #define ACPI_FADT_WBINVD_FLUSH (1 << 1)
1007 #define ACPI_FADT_C1_SUPPORTED (1 << 2)
1008 #define ACPI_FADT_C2_MP_SUPPORTED (1 << 3)
1009 #define ACPI_FADT_POWER_BUTTON (1 << 4)
1010 #define ACPI_FADT_SLEEP_BUTTON (1 << 5)
1011 #define ACPI_FADT_FIXED_RTC (1 << 6)
1012 #define ACPI_FADT_S4_RTC_WAKE (1 << 7)
1013 #define ACPI_FADT_32BIT_TIMER (1 << 8)
1014 #define ACPI_FADT_DOCKING_SUPPORTED (1 << 9)
1015 #define ACPI_FADT_RESET_REGISTER (1 << 10)
1016 #define ACPI_FADT_SEALED_CASE (1 << 11)
1017 #define ACPI_FADT_HEADLESS (1 << 12)
1018 #define ACPI_FADT_SLEEP_TYPE (1 << 13)
1019 #define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14)
1020 #define ACPI_FADT_PLATFORM_CLOCK (1 << 15)
1021 #define ACPI_FADT_S4_RTC_VALID (1 << 16)
1022 #define ACPI_FADT_REMOTE_POWER_ON (1 << 17)
1023 #define ACPI_FADT_APIC_CLUSTER (1 << 18)
1024 #define ACPI_FADT_APIC_PHYSICAL (1 << 19)
1025 /* Bits 20-31: reserved ACPI 3.0 & 4.0 */
1026 #define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
1027 #define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
1028 /* bits 22-31: reserved since ACPI 5.0 */
1029
1030 /* FADT Boot Architecture Flags */
1031 #define ACPI_FADT_LEGACY_DEVICES (1 << 0)
1032 #define ACPI_FADT_8042 (1 << 1)
1033 #define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
1034 #define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
1035 #define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
1036 #define ACPI_FADT_NO_CMOS_RTC (1 << 5)
1037 #define ACPI_FADT_LEGACY_FREE 0x00 /* No legacy devices (including 8042) */
1038
1039 /* FADT ARM Boot Architecture Flags */
1040 #define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
1041 #define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
1042 /* bits 2-16: reserved since ACPI 5.1 */
1043
1044 /* FADT Preferred Power Management Profile */
1045 enum acpi_preferred_pm_profiles {
1046 PM_UNSPECIFIED = 0,
1047 PM_DESKTOP = 1,
1048 PM_MOBILE = 2,
1049 PM_WORKSTATION = 3,
1050 PM_ENTERPRISE_SERVER = 4,
1051 PM_SOHO_SERVER = 5,
1052 PM_APPLIANCE_PC = 6,
1053 PM_PERFORMANCE_SERVER = 7,
1054 PM_TABLET = 8, /* ACPI 5.0 & greater */
1055 };
1056
1057 /* FACS (Firmware ACPI Control Structure) */
1058 typedef struct acpi_facs {
1059 char signature[4]; /* "FACS" */
1060 u32 length; /* Length in bytes (>= 64) */
1061 u32 hardware_signature; /* Hardware signature */
1062 u32 firmware_waking_vector; /* Firmware waking vector */
1063 u32 global_lock; /* Global lock */
1064 u32 flags; /* FACS flags */
1065 u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
1066 u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
1067 u8 version; /* FACS version */
1068 u8 resv1[3]; /* This value is 0 */
1069 u32 ospm_flags; /* 64BIT_WAKE_F */
1070 u8 resv2[24]; /* This value is 0 */
1071 } __packed acpi_facs_t;
1072
1073 /* FACS flags */
1074 #define ACPI_FACS_S4BIOS_F (1 << 0)
1075 #define ACPI_FACS_64BIT_WAKE_F (1 << 1)
1076 /* Bits 31..2: reserved */
1077
1078 /* ECDT (Embedded Controller Boot Resources Table) */
1079 typedef struct acpi_ecdt {
1080 acpi_header_t header;
1081 acpi_addr_t ec_control; /* EC control register */
1082 acpi_addr_t ec_data; /* EC data register */
1083 u32 uid; /* UID */
1084 u8 gpe_bit; /* GPE bit */
1085 u8 ec_id[]; /* EC ID */
1086 } __packed acpi_ecdt_t;
1087
1088 /* HEST (Hardware Error Source Table) */
1089 typedef struct acpi_hest {
1090 acpi_header_t header;
1091 u32 error_source_count;
1092 /* error_source_struct(s) */
1093 } __packed acpi_hest_t;
1094
1095 /* Error Source Descriptors */
1096 typedef struct acpi_hest_esd {
1097 u16 type;
1098 u16 source_id;
1099 u16 resv;
1100 u8 flags;
1101 u8 enabled;
1102 u32 prealloc_erecords; /* The number of error records to
1103 * pre-allocate for this error source.
1104 */
1105 u32 max_section_per_record;
1106 } __packed acpi_hest_esd_t;
1107
1108 /* Hardware Error Notification */
1109 typedef struct acpi_hest_hen {
1110 u8 type;
1111 u8 length;
1112 u16 conf_we; /* Configuration Write Enable */
1113 u32 poll_interval;
1114 u32 vector;
1115 u32 sw2poll_threshold_val;
1116 u32 sw2poll_threshold_win;
1117 u32 error_threshold_val;
1118 u32 error_threshold_win;
1119 } __packed acpi_hest_hen_t;
1120
1121 /* BERT (Boot Error Record Table) */
1122 typedef struct acpi_bert {
1123 acpi_header_t header;
1124 u32 region_length;
1125 u64 error_region;
1126 } __packed acpi_bert_t;
1127
1128 /* Generic Error Data Entry */
1129 typedef struct acpi_hest_generic_data {
1130 guid_t section_type;
1131 u32 error_severity;
1132 u16 revision;
1133 u8 validation_bits;
1134 u8 flags;
1135 u32 data_length;
1136 guid_t fru_id;
1137 u8 fru_text[20];
1138 /* error data */
1139 } __packed acpi_hest_generic_data_t;
1140
1141 /* Generic Error Data Entry v300 */
1142 typedef struct acpi_hest_generic_data_v300 {
1143 guid_t section_type;
1144 u32 error_severity;
1145 u16 revision;
1146 u8 validation_bits;
1147 u8 flags; /* see CPER Section Descriptor, Flags field */
1148 u32 data_length;
1149 guid_t fru_id;
1150 u8 fru_text[20];
1151 cper_timestamp_t timestamp;
1152 /* error data */
1153 } __packed acpi_hest_generic_data_v300_t;
1154 #define HEST_GENERIC_ENTRY_V300 0x300
1155
1156 /* Both Generic Error Status & Generic Error Data Entry, Error Severity field */
1157 #define ACPI_GENERROR_SEV_RECOVERABLE 0
1158 #define ACPI_GENERROR_SEV_FATAL 1
1159 #define ACPI_GENERROR_SEV_CORRECTED 2
1160 #define ACPI_GENERROR_SEV_NONE 3
1161
1162 /* Generic Error Data Entry, Validation Bits field */
1163 #define ACPI_GENERROR_VALID_FRUID BIT(0)
1164 #define ACPI_GENERROR_VALID_FRUID_TEXT BIT(1)
1165 #define ACPI_GENERROR_VALID_TIMESTAMP BIT(2)
1166
1167 /*
1168 * Generic Error Status Block
1169 *
1170 * If there is a raw data section at the end of the generic error status block after the
1171 * zero or more generic error data entries, raw_data_length indicates the length of the raw
1172 * section and raw_data_offset is the offset of the beginning of the raw data section from
1173 * the start of the acpi_generic_error_status block it is contained in. So if raw_data_length
1174 * is non-zero, raw_data_offset must be at least sizeof(acpi_generic_error_status_t).
1175 */
1176 typedef struct acpi_generic_error_status {
1177 u32 block_status;
1178 u32 raw_data_offset; /* must follow any generic entries */
1179 u32 raw_data_length;
1180 u32 data_length; /* generic data */
1181 u32 error_severity;
1182 /* Generic Error Data structures, zero or more entries */
1183 } __packed acpi_generic_error_status_t;
1184
1185 /* Generic Status Block, Block Status values */
1186 #define GENERIC_ERR_STS_UNCORRECTABLE_VALID BIT(0)
1187 #define GENERIC_ERR_STS_CORRECTABLE_VALID BIT(1)
1188 #define GENERIC_ERR_STS_MULT_UNCORRECTABLE BIT(2)
1189 #define GENERIC_ERR_STS_MULT_CORRECTABLE BIT(3)
1190 #define GENERIC_ERR_STS_ENTRY_COUNT_SHIFT 4
1191 #define GENERIC_ERR_STS_ENTRY_COUNT_MAX 0x3ff
1192 #define GENERIC_ERR_STS_ENTRY_COUNT_MASK \
1193 (GENERIC_ERR_STS_ENTRY_COUNT_MAX \
1194 << GENERIC_ERR_STS_ENTRY_COUNT_SHIFT)
1195
1196 typedef struct acpi_cstate {
1197 u8 ctype;
1198 u16 latency;
1199 u32 power;
1200 acpi_addr_t resource;
1201 } __packed acpi_cstate_t;
1202
1203 struct acpi_sw_pstate {
1204 u32 core_freq;
1205 u32 power;
1206 u32 transition_latency;
1207 u32 bus_master_latency;
1208 u32 control_value;
1209 u32 status_value;
1210 } __packed;
1211
1212 struct acpi_xpss_sw_pstate {
1213 u64 core_freq;
1214 u64 power;
1215 u64 transition_latency;
1216 u64 bus_master_latency;
1217 u64 control_value;
1218 u64 status_value;
1219 u64 control_mask;
1220 u64 status_mask;
1221 } __packed;
1222
1223 typedef struct acpi_tstate {
1224 u32 percent;
1225 u32 power;
1226 u32 latency;
1227 u32 control;
1228 u32 status;
1229 } __packed acpi_tstate_t;
1230
1231 enum acpi_lpi_state_flags {
1232 ACPI_LPI_STATE_DISABLED = 0,
1233 ACPI_LPI_STATE_ENABLED
1234 };
1235
1236 /* Low Power Idle State */
1237 struct acpi_lpi_state {
1238 u32 min_residency_us;
1239 u32 worst_case_wakeup_latency_us;
1240 u32 flags;
1241 u32 arch_context_lost_flags;
1242 u32 residency_counter_frequency_hz;
1243 u32 enabled_parent_state;
1244 acpi_addr_t entry_method;
1245 acpi_addr_t residency_counter_register;
1246 acpi_addr_t usage_counter_register;
1247 const char *state_name;
1248 };
1249
1250 /* Port types for ACPI _UPC object */
1251 enum acpi_upc_type {
1252 UPC_TYPE_A,
1253 UPC_TYPE_MINI_AB,
1254 UPC_TYPE_EXPRESSCARD,
1255 UPC_TYPE_USB3_A,
1256 UPC_TYPE_USB3_B,
1257 UPC_TYPE_USB3_MICRO_B,
1258 UPC_TYPE_USB3_MICRO_AB,
1259 UPC_TYPE_USB3_POWER_B,
1260 UPC_TYPE_C_USB2_ONLY,
1261 UPC_TYPE_C_USB2_SS_SWITCH,
1262 UPC_TYPE_C_USB2_SS,
1263 UPC_TYPE_PROPRIETARY = 0xff,
1264 /*
1265 * The following types are not directly defined in the ACPI
1266 * spec but are used by coreboot to identify a USB device type.
1267 */
1268 UPC_TYPE_INTERNAL = 0xff,
1269 UPC_TYPE_UNUSED,
1270 UPC_TYPE_HUB
1271 };
1272
1273 enum acpi_ipmi_interface_type {
1274 IPMI_INTERFACE_RESERVED = 0,
1275 IPMI_INTERFACE_KCS,
1276 IPMI_INTERFACE_SMIC,
1277 IPMI_INTERFACE_BT,
1278 IPMI_INTERFACE_SSIF,
1279 };
1280
1281 #define ACPI_IPMI_PCI_DEVICE_FLAG (1 << 0)
1282 #define ACPI_IPMI_INT_TYPE_SCI (1 << 0)
1283 #define ACPI_IPMI_INT_TYPE_APIC (1 << 1)
1284
1285 /* ACPI IPMI 2.0 */
1286 struct acpi_spmi {
1287 acpi_header_t header;
1288 u8 interface_type;
1289 u8 reserved;
1290 u16 specification_revision;
1291 u8 interrupt_type;
1292 u8 gpe;
1293 u8 reserved2;
1294 u8 pci_device_flag;
1295
1296 u32 global_system_interrupt;
1297 acpi_addr_t base_address;
1298 union {
1299 struct {
1300 u8 pci_segment_group;
1301 u8 pci_bus;
1302 u8 pci_device;
1303 u8 pci_function;
1304 };
1305 u8 uid[4];
1306 };
1307 u8 reserved3;
1308 } __packed;
1309
1310 /* EINJ APEI Standard Definitions */
1311 /* EINJ Error Types
1312 Refer to the ACPI spec, EINJ section, for more info on bit definitions
1313 */
1314 #define ACPI_EINJ_CPU_CE (1 << 0)
1315 #define ACPI_EINJ_CPU_UCE (1 << 1)
1316 #define ACPI_EINJ_CPU_UCE_FATAL (1 << 2)
1317 #define ACPI_EINJ_MEM_CE (1 << 3)
1318 #define ACPI_EINJ_MEM_UCE (1 << 4)
1319 #define ACPI_EINJ_MEM_UCE_FATAL (1 << 5)
1320 #define ACPI_EINJ_PCIE_CE (1 << 6)
1321 #define ACPI_EINJ_PCIE_UCE_NON_FATAL (1 << 7)
1322 #define ACPI_EINJ_PCIE_UCE_FATAL (1 << 8)
1323 #define ACPI_EINJ_PLATFORM_CE (1 << 9)
1324 #define ACPI_EINJ_PLATFORM_UCE (1 << 10)
1325 #define ACPI_EINJ_PLATFORM_UCE_FATAL (1 << 11)
1326 #define ACPI_EINJ_VENDOR_DEFINED (1 << 31)
1327 #define ACPI_EINJ_DEFAULT_CAP (ACPI_EINJ_MEM_CE | ACPI_EINJ_MEM_UCE | \
1328 ACPI_EINJ_PCIE_CE | ACPI_EINJ_PCIE_UCE_FATAL)
1329
1330 /* EINJ actions */
1331 #define ACTION_COUNT 9
1332 #define BEGIN_INJECT_OP 0x00
1333 #define GET_TRIGGER_ACTION_TABLE 0x01
1334 #define SET_ERROR_TYPE 0x02
1335 #define GET_ERROR_TYPE 0x03
1336 #define END_INJECT_OP 0x04
1337 #define EXECUTE_INJECT_OP 0x05
1338 #define CHECK_BUSY_STATUS 0x06
1339 #define GET_CMD_STATUS 0x07
1340 #define SET_ERROR_TYPE_WITH_ADDRESS 0x08
1341 #define TRIGGER_ERROR 0xFF
1342
1343 /* EINJ Instructions */
1344 #define READ_REGISTER 0x00
1345 #define READ_REGISTER_VALUE 0x01
1346 #define WRITE_REGISTER 0x02
1347 #define WRITE_REGISTER_VALUE 0x03
1348 #define NO_OP 0x04
1349
1350 /* EINJ (Error Injection Table) */
1351 typedef struct acpi_gen_regaddr1 {
1352 u8 space_id; /* Address space ID */
1353 u8 bit_width; /* Register size in bits */
1354 u8 bit_offset; /* Register bit offset */
1355 u8 access_size; /* Access size since ACPI 2.0c */
1356 u64 addr; /* Register address */
1357 } __packed acpi_addr64_t;
1358
1359 /* Instruction entry */
1360 typedef struct acpi_einj_action_table {
1361 u8 action;
1362 u8 instruction;
1363 u16 flags;
1364 acpi_addr64_t reg;
1365 u64 value;
1366 u64 mask;
1367 } __packed acpi_einj_action_table_t;
1368
1369 typedef struct acpi_injection_header {
1370 u32 einj_header_size;
1371 u32 flags;
1372 u32 entry_count;
1373 } __packed acpi_injection_header_t;
1374
1375 typedef struct acpi_einj_trigger_table {
1376 u32 header_size;
1377 u32 revision;
1378 u32 table_size;
1379 u32 entry_count;
1380 acpi_einj_action_table_t trigger_action[];
1381 } __packed acpi_einj_trigger_table_t;
1382
1383 typedef struct set_error_type {
1384 u32 errtype;
1385 u32 vendorerrortype;
1386 u32 flags;
1387 u32 apicid;
1388 u64 memaddr;
1389 u64 memrange;
1390 u32 pciesbdf;
1391 } __packed set_error_type_t;
1392
1393 #define EINJ_PARAM_NUM 6
1394 typedef struct acpi_einj_smi {
1395 u64 op_state;
1396 u64 err_inject[EINJ_PARAM_NUM];
1397 u64 trigger_action_table;
1398 u64 err_inj_cap;
1399 u64 op_status;
1400 u64 cmd_sts;
1401 u64 einj_addr;
1402 u64 einj_addr_msk;
1403 set_error_type_t setaddrtable;
1404 u64 reserved[50];
1405 } __packed acpi_einj_smi_t;
1406
1407 /* EINJ Flags */
1408 #define EINJ_DEF_TRIGGER_PORT 0xb2
1409 #define FLAG_PRESERVE 0x01
1410 #define FLAG_IGNORE 0x00
1411
1412 /* EINJ Registers */
1413 #define EINJ_REG_MEMORY(address) \
1414 { \
1415 .space_id = ACPI_ADDRESS_SPACE_MEMORY, \
1416 .bit_width = 64, \
1417 .bit_offset = 0, \
1418 .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \
1419 .addr = address}
1420
1421 #define EINJ_REG_IO() \
1422 { \
1423 .space_id = ACPI_ADDRESS_SPACE_IO, \
1424 .bit_width = 0x10, \
1425 .bit_offset = 0, \
1426 .access_size = ACPI_ACCESS_SIZE_WORD_ACCESS, \
1427 .addr = EINJ_DEF_TRIGGER_PORT} /* HW dependent code can override this also */
1428
1429 typedef struct acpi_einj {
1430 acpi_header_t header;
1431 acpi_injection_header_t inj_header;
1432 acpi_einj_action_table_t action_table[ACTION_COUNT];
1433 } __packed acpi_einj_t;
1434
1435 /* PPTT definitions */
1436
1437 #define PPTT_NODE_TYPE_CPU 0
1438 #define PPTT_NODE_TYPE_CACHE 1
1439
1440 /* PPTT structures for ACPI generation */
1441
1442 typedef struct acpi_pptt_cpu_node {
1443 u8 type; // type = 0 (processor structure specification)
1444 u8 length; // in bytes
1445 u8 reserved[2]; // reserved, must be zero
1446 u32 flags; // processor hierarchy node structure flags
1447 u32 parent; // reference (delta of pptt-start and node) to parent node, must be zero if no parent
1448 u32 processor_id; // must match id in MADT, if actual processor
1449 u32 n_resources; // number of resource structure references
1450 u32 resources[]; // resource structure references
1451 } acpi_pptt_cpu_node_t;
1452
1453 typedef struct acpi_pptt_cache_node {
1454 u8 type; // type = 1 (cache type structure)
1455 u8 length; // length = 28
1456 u8 reserved[2]; // reserved, must be zero
1457 u32 flags; // cache structure flags
1458 u32 next_level; // reference to next level cache, null if last cache level
1459 u32 size; // cache size in bytes
1460 u32 n_sets; // number of sets in the cache
1461 u8 associativity; // integer number of ways
1462 u8 attributes; // bits[7:5] reserved, must be zero
1463 u16 line_size; // in bytes
1464 u32 cache_id; // unique, non-zero
1465 } acpi_pptt_cache_node_t;
1466
1467 union acpi_pptt_body {
1468 acpi_pptt_cpu_node_t cpu;
1469 acpi_pptt_cache_node_t cache;
1470 };
1471
1472 typedef struct acpi_pptt {
1473 acpi_header_t header;
1474
1475 /*
1476 * followed by a variable length body
1477 * consisting of processor topology structures.
1478 *
1479 * see acpi_pptt_cpu_node and
1480 * acpi_pptt_cache_node.
1481 */
1482 union acpi_pptt_body body[];
1483 } __packed acpi_pptt_t;
1484
1485 /* PPTT structures for topology description */
1486
1487 union pptt_cache_flags {
1488 struct {
1489 u32 size_valid : 1;
1490 u32 n_sets_valid : 1;
1491 u32 associativity_valid : 1;
1492 u32 alloc_type_valid : 1;
1493 u32 cache_type_valid : 1;
1494 u32 write_policy_valid : 1;
1495 u32 line_size_valid : 1;
1496 u32 cache_id_valid : 1;
1497 u32 reserved : 24;
1498 };
1499
1500 u32 raw;
1501 };
1502
1503 union pptt_cpu_flags {
1504 struct {
1505 u32 is_physical_package : 1;
1506 u32 processor_id_valid : 1;
1507 u32 is_thread : 1;
1508 u32 is_leaf : 1;
1509 u32 is_identical_impl : 1;
1510 u32 reserved : 27;
1511 };
1512
1513 u32 raw;
1514 };
1515
1516 struct pptt_cache {
1517 u32 size;
1518 u32 numsets;
1519 u8 associativity;
1520 u8 attributes;
1521 u16 line_size;
1522 union pptt_cache_flags flags;
1523 struct pptt_cache *next_level;
1524 };
1525
1526 struct pptt_cpu_resources {
1527 struct pptt_cache *cache;
1528 struct pptt_cpu_resources *next;
1529 };
1530
1531 struct pptt_topology {
1532 u32 processor_id;
1533 union pptt_cpu_flags flags;
1534 struct pptt_cpu_resources *resources;
1535 struct pptt_topology *sibling;
1536 struct pptt_topology *child;
1537 };
1538
1539 /* SPCR (Serial Port Console Redirection Table) */
1540 typedef struct acpi_spcr {
1541 acpi_header_t header;
1542 uint8_t interface_type;
1543 uint8_t reserved[3];
1544 acpi_addr_t base_address;
1545 uint8_t interrupt_type;
1546 uint8_t irq;
1547 uint32_t global_system_interrupt;
1548 uint8_t configured_baudrate;
1549 uint8_t parity;
1550 uint8_t stop_bits;
1551 uint8_t flow_control;
1552 uint8_t terminal_type;
1553 uint8_t language;
1554 uint16_t pci_did;
1555 uint16_t pci_vid;
1556 uint8_t pci_bus;
1557 uint8_t pci_dev;
1558 uint8_t pci_fun;
1559 uint32_t pci_flags;
1560 uint8_t pci_segment;
1561 uint32_t uart_clock;
1562 uint32_t precise_baud_rate;
1563 uint16_t namespace_string_length;
1564 uint16_t namespace_string_offset;
1565 char namespacestring[];
1566 } __packed acpi_spcr_t;
1567 _Static_assert(sizeof(acpi_spcr_t) == 88, "acpi_spcr_t must have an 88 byte size\n");
1568
1569 #define PC_AT_COMPATIBLE_INTERRUPT (1 << 0)
1570 #define IO_APIC_COMPATIBLE_INTERRUPT (1 << 1)
1571 #define IO_SAPIC_COMPATIBLE_INTERRUPT (1 << 2)
1572 #define ARMH_GIC_COMPATIBLE_INTERRUPT (1 << 3)
1573 #define RISCV_PLIC_COMPATIBLE_INTERRUPT (1 << 4)
1574
1575 /* GTDT - Generic Timer Description Table (ACPI 5.1) Version 2 */
1576 typedef struct acpi_table_gtdt {
1577 acpi_header_t header; /* Common ACPI table header */
1578 u64 counter_block_address;
1579 u32 reserved;
1580 u32 secure_el1_interrupt;
1581 u32 secure_el1_flags;
1582 u32 non_secure_el1_interrupt;
1583 u32 non_secure_el1_flags;
1584 u32 virtual_timer_interrupt;
1585 u32 virtual_timer_flags;
1586 u32 non_secure_el2_interrupt;
1587 u32 non_secure_el2_flags;
1588 u64 counter_read_block_address;
1589 u32 platform_timer_count;
1590 u32 platform_timer_offset;
1591 } __packed acpi_gtdt_t;
1592
1593 /* Flag Definitions: Timer Block Physical Timers and Virtual timers */
1594
1595 #define ACPI_GTDT_INTERRUPT_MODE (1)
1596 #define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
1597 #define ACPI_GTDT_ALWAYS_ON (1<<2)
1598
1599 struct acpi_gtdt_el2 {
1600 u32 virtual_el2_timer_gsiv;
1601 u32 virtual_el2_timer_flags;
1602 };
1603
1604 /* Common GTDT subtable header */
1605
1606 struct acpi_gtdt_header {
1607 u8 type;
1608 u16 length;
1609 } __packed;
1610
1611 /* Values for GTDT subtable type above */
1612
1613 enum acpi_gtdt_type {
1614 ACPI_GTDT_TYPE_TIMER_BLOCK = 0,
1615 ACPI_GTDT_TYPE_WATCHDOG = 1,
1616 ACPI_GTDT_TYPE_RESERVED = 2 /* 2 and greater are reserved */
1617 };
1618
1619 /* GTDT Subtables, correspond to Type in struct acpi_gtdt_header */
1620
1621 /* 0: Generic Timer Block */
1622
1623 struct acpi_gtdt_timer_block {
1624 struct acpi_gtdt_header header;
1625 u8 reserved;
1626 u64 block_address;
1627 u32 timer_count;
1628 u32 timer_offset;
1629 } __packed;
1630
1631 /* Timer Sub-Structure, one per timer */
1632
1633 struct acpi_gtdt_timer_entry {
1634 u8 frame_number;
1635 u8 reserved[3];
1636 u64 base_address;
1637 u64 el0_base_address;
1638 u32 timer_interrupt;
1639 u32 timer_flags;
1640 u32 virtual_timer_interrupt;
1641 u32 virtual_timer_flags;
1642 u32 common_flags;
1643 } __packed;
1644
1645 /* Flag Definitions: timer_flags and virtual_timer_flags above */
1646
1647 #define ACPI_GTDT_GT_IRQ_MODE (1)
1648 #define ACPI_GTDT_GT_IRQ_POLARITY (1<<1)
1649
1650 /* Flag Definitions: common_flags above */
1651
1652 #define ACPI_GTDT_GT_IS_SECURE_TIMER (1)
1653 #define ACPI_GTDT_GT_ALWAYS_ON (1<<1)
1654
1655 /* 1: SBSA Generic Watchdog Structure */
1656
1657 struct acpi_gtdt_watchdog {
1658 struct acpi_gtdt_header header;
1659 u8 reserved;
1660 u64 refresh_frame_address;
1661 u64 control_frame_address;
1662 u32 timer_interrupt;
1663 u32 timer_flags;
1664 } __packed;
1665
1666 /* Flag Definitions: timer_flags above */
1667
1668 #define ACPI_GTDT_WATCHDOG_IRQ_MODE (1)
1669 #define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1)
1670 #define ACPI_GTDT_WATCHDOG_SECURE (1<<2)
1671
1672 enum acpi_wdat_actions {
1673 ACPI_WDAT_RESET = 1,
1674 ACPI_WDAT_GET_CURRENT_COUNTDOWN = 4,
1675 ACPI_WDAT_GET_COUNTDOWN = 5,
1676 ACPI_WDAT_SET_COUNTDOWN = 6,
1677 ACPI_WDAT_GET_RUNNING_STATE = 8,
1678 ACPI_WDAT_SET_RUNNING_STATE = 9,
1679 ACPI_WDAT_GET_STOPPED_STATE = 10,
1680 ACPI_WDAT_SET_STOPPED_STATE = 11,
1681 ACPI_WDAT_GET_REBOOT = 16,
1682 ACPI_WDAT_SET_REBOOT = 17,
1683 ACPI_WDAT_GET_SHUTDOWN = 18,
1684 ACPI_WDAT_SET_SHUTDOWN = 19,
1685 ACPI_WDAT_GET_STATUS = 32,
1686 ACPI_WDAT_SET_STATUS = 33,
1687 ACPI_WDAT_ACTION_RESERVED = 34 /* 34 and greater are reserved */
1688 };
1689
1690 enum acpi_wdat_instructions {
1691 ACPI_WDAT_READ_VALUE = 0,
1692 ACPI_WDAT_READ_COUNTDOWN = 1,
1693 ACPI_WDAT_WRITE_VALUE = 2,
1694 ACPI_WDAT_WRITE_COUNTDOWN = 3,
1695 ACPI_WDAT_INSTRUCTION_RESERVED = 4, /* 4 and greater are reserved */
1696 ACPI_WDAT_PRESERVE_REGISTER = 0x80 /* Except for this value */
1697 };
1698
1699 enum acpi_wdat_flags {
1700 ACPI_WDAT_FLAG_DISABLED = 0,
1701 ACPI_WDAT_FLAG_ENABLED = 1
1702 };
1703
1704 enum acpi_wdat_access_size {
1705 ACPI_WDAT_ACCESS_SIZE_BYTE = 1,
1706 ACPI_WDAT_ACCESS_SIZE_WORD = 2,
1707 ACPI_WDAT_ACCESS_SIZE_DWORD = 3
1708 };
1709
1710 /* ACPI WDAT */
1711 typedef struct acpi_wdat_entry {
1712 u8 action;
1713 u8 instruction;
1714 u16 reserved;
1715 struct acpi_gen_regaddr register_region;
1716 u32 value;
1717 u32 mask;
1718 } __packed acpi_wdat_entry_t;
1719
1720 typedef struct acpi_table_wdat {
1721 acpi_header_t header; /* Common ACPI table header */
1722 u32 header_length;
1723 u16 pci_segment;
1724 u8 pci_bus;
1725 u8 pci_device;
1726 u8 pci_function;
1727 u8 reserved[3];
1728 u32 timer_period;
1729 u32 max_count;
1730 u32 min_count;
1731 u8 flags;
1732 u8 reserved2[3];
1733 u32 entries;
1734 } __packed acpi_wdat_t;
1735
1736 uintptr_t get_coreboot_rsdp(void);
1737 void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions);
1738
1739 unsigned long fw_cfg_acpi_tables(unsigned long start);
1740
1741 /* These are implemented by the target port or north/southbridge. */
1742 void preload_acpi_dsdt(void);
1743 unsigned long write_acpi_tables(const unsigned long addr);
1744 unsigned long acpi_fill_madt(unsigned long current);
1745 unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current);
1746
1747 void acpi_fill_fadt(acpi_fadt_t *fadt);
1748 void arch_fill_fadt(acpi_fadt_t *fadt);
1749 void soc_fill_fadt(acpi_fadt_t *fadt);
1750 void mainboard_fill_fadt(acpi_fadt_t *fadt);
1751
1752 void fill_fadt_extended_pm_io(acpi_fadt_t *fadt);
1753
1754 void acpi_fill_gnvs(void);
1755 void acpi_fill_cnvs(void);
1756
1757 unsigned long acpi_fill_lpit(unsigned long current);
1758
1759 /* These can be used by the target port. */
1760 u8 acpi_checksum(u8 *table, u32 length);
1761
1762 void acpi_add_table(acpi_rsdp_t *rsdp, void *table);
1763
1764 /* Create CXL Early Discovery Table */
1765 void acpi_create_cedt(acpi_cedt_t *cedt,
1766 unsigned long (*acpi_fill_cedt)(unsigned long current));
1767 /* Create a CXL Host Bridge Structure for CEDT */
1768 int acpi_create_cedt_chbs(acpi_cedt_chbs_t *chbs, u32 uid, u32 cxl_ver, u64 base);
1769 /* Create a CXL Fixed Memory Window Structure for CEDT */
1770 int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size,
1771 u8 eniw, u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target);
1772
1773 /* PPTT related functions */
1774 void acpi_create_pptt_body(acpi_pptt_t *pptt);
1775 struct pptt_topology *acpi_get_pptt_topology(void);
1776
1777 int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr);
1778
1779 unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 cpu, u32 apic);
1780
1781 unsigned long acpi_create_madt_lapic_nmis(unsigned long current);
1782
1783 uintptr_t platform_get_gicd_base(void);
1784 uintptr_t platform_get_gicr_base(void);
1785 int platform_get_gic_its(uintptr_t **base);
1786
1787 int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic);
1788 int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic);
1789 int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
1790 u32 flags);
1791 /*
1792 * Given the Generic Initiator device's BDF, the proximity domain's ID
1793 * and flag, create Generic Initiator Affinity structure in SRAT.
1794 */
1795 int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain,
1796 struct device *dev, u32 flags);
1797 unsigned long acpi_create_srat_lapics(unsigned long current);
1798 void acpi_create_srat(acpi_srat_t *srat,
1799 unsigned long (*acpi_fill_srat)(unsigned long current));
1800
1801 void acpi_create_slit(acpi_slit_t *slit,
1802 unsigned long (*acpi_fill_slit)(unsigned long current));
1803
1804 /*
1805 * Create a Memory Proximity Domain Attributes structure for HMAT,
1806 * given proximity domain for the attached initiator, and
1807 * proximity domain for the memory.
1808 */
1809 int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory);
1810 /* Create Heterogeneous Memory Attribute Table */
1811 void acpi_create_hmat(acpi_hmat_t *hmat,
1812 unsigned long (*acpi_fill_hmat)(unsigned long current));
1813
1814 void acpi_create_vfct(const struct device *device,
1815 acpi_vfct_t *vfct,
1816 unsigned long (*acpi_fill_vfct)(const struct device *device,
1817 acpi_vfct_t *vfct_struct,
1818 unsigned long current));
1819
1820 void acpi_create_ipmi(const struct device *device,
1821 struct acpi_spmi *spmi,
1822 const u16 ipmi_revision,
1823 const acpi_addr_t *addr,
1824 const enum acpi_ipmi_interface_type type,
1825 const s8 gpe_interrupt,
1826 const u32 apic_interrupt,
1827 const u32 uid);
1828
1829 void acpi_create_ivrs(acpi_ivrs_t *ivrs,
1830 unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
1831 unsigned long current));
1832
1833 void acpi_create_crat(struct acpi_crat_header *crat,
1834 unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct,
1835 unsigned long current));
1836
1837 unsigned long acpi_write_hpet(const struct device *device, unsigned long start,
1838 acpi_rsdp_t *rsdp);
1839
1840 /* cpu/intel/speedstep/acpi.c */
1841 void generate_cpu_entries(const struct device *device);
1842
1843 unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
1844 const struct device *dev, uint8_t access_size);
1845 unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current,
1846 uint64_t base, const char *name);
1847 unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current,
1848 uint64_t base, const char *name);
1849
1850 void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
1851 unsigned long (*acpi_fill_dmar)(unsigned long));
1852 unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags,
1853 u16 segment, u64 bar);
1854 unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags,
1855 u16 segment, u64 bar, size_t size);
1856 unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment,
1857 u64 bar, u64 limit);
1858 unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags,
1859 u16 segment);
1860 unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr,
1861 u32 proximity_domain);
1862 unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number,
1863 const char *device_name);
1864 unsigned long acpi_create_dmar_satc(unsigned long current, u8 flags,
1865 u16 segment);
1866 void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current);
1867 void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current);
1868 void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current);
1869 void acpi_dmar_satc_fixup(unsigned long base, unsigned long current);
1870 unsigned long acpi_create_dmar_ds_pci_br(unsigned long current,
1871 u8 bus, u8 dev, u8 fn);
1872 unsigned long acpi_create_dmar_ds_pci(unsigned long current,
1873 u8 bus, u8 dev, u8 fn);
1874 unsigned long acpi_create_dmar_ds_ioapic(unsigned long current,
1875 u8 enumeration_id,
1876 u8 bus, u8 dev, u8 fn);
1877 unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current,
1878 u32 addr, u8 bus, u8 dev, u8 fn);
1879 unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current,
1880 u8 enumeration_id,
1881 u8 bus, u8 dev, u8 fn);
1882 void acpi_write_hest(acpi_hest_t *hest,
1883 unsigned long (*acpi_fill_hest)(acpi_hest_t *hest));
1884
1885 unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
1886 acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
1887
1888 unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid);
1889
1890 /* chipsets that select ACPI_BERT must implement this function */
1891 enum cb_err acpi_soc_get_bert_region(void **region, size_t *length);
1892
1893 void acpi_soc_fill_gtdt(acpi_gtdt_t *gtdt);
1894 unsigned long acpi_soc_gtdt_add_timers(uint32_t *count, unsigned long current);
1895 unsigned long acpi_gtdt_add_timer_block(unsigned long current, const uint64_t address,
1896 struct acpi_gtdt_timer_entry *timers, size_t number);
1897 unsigned long acpi_gtdt_add_watchdog(unsigned long current, uint64_t refresh_frame,
1898 uint64_t control_frame, uint32_t gsiv, uint32_t flags);
1899
1900 /*
1901 * Populate primary acpi_wdat_t struct to provide basic information about watchdog and
1902 * associated acpi_wdat_entry_t structures, which correspond to watchdog-related
1903 * actions such as start/stop watchdog, set timeout, ping watchdog, get remaining time,
1904 * etc. Each acpi_wdat_entry_t entry indicates what needs to be written to a specific
1905 * address to perform a specific action or at which address the watchdog-related
1906 * information is stored.
1907 *
1908 * The acpi_wdat_entry_t structures follow the acpi_wdat_t, so the table layout is as
1909 * follows:
1910 * +---------------------+
1911 * | acpi_wdat_t { |
1912 * | ... |
1913 * | } |
1914 * | acpi_wdat_entry_t { |
1915 * | ... |
1916 * | } |
1917 * | acpi_wdat_entry_t { |
1918 * | ... |
1919 * | } |
1920 * +---------------------+
1921 *
1922 * @param wdat Pointer to populate acpi_wdat_t struct
1923 * @param current Position in memory after the acpi_wdat_t struct which also indicates
1924 * the position where the first acpi_wdat_entry_t must be placed.
1925 * @return Position after last acpi_wdat_entry_t struct
1926 */
1927 unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current);
1928
1929 /* For ACPI S3 support. */
1930 void __noreturn acpi_resume(void *wake_vec);
1931 void mainboard_suspend_resume(void);
1932 void *acpi_find_wakeup_vector(void);
1933
1934 /* ACPI_Sn assignments are defined to always equal the sleep state numbers */
1935 enum {
1936 ACPI_S0 = 0,
1937 ACPI_S1 = 1,
1938 ACPI_S2 = 2,
1939 ACPI_S3 = 3,
1940 ACPI_S4 = 4,
1941 ACPI_S5 = 5,
1942 };
1943
1944 #if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
1945 || CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
1946 /* Given the provided PM1 control register return the ACPI sleep type. */
acpi_sleep_from_pm1(uint32_t pm1_cnt)1947 static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt)
1948 {
1949 switch (((pm1_cnt) & SLP_TYP) >> SLP_TYP_SHIFT) {
1950 case SLP_TYP_S0: return ACPI_S0;
1951 case SLP_TYP_S1: return ACPI_S1;
1952 case SLP_TYP_S3: return ACPI_S3;
1953 case SLP_TYP_S4: return ACPI_S4;
1954 case SLP_TYP_S5: return ACPI_S5;
1955 }
1956 return -1;
1957 }
1958 #endif
1959
1960 uint8_t acpi_get_preferred_pm_profile(void);
1961
1962 /* Returns ACPI_Sx values. */
1963 int acpi_get_sleep_type(void);
1964
1965 /* Read and clear GPE status */
1966 int acpi_get_gpe(int gpe);
1967
1968 /* Once we enter payload, is SMI handler installed and capable of
1969 responding to APM_CNT Advanced Power Management Control commands. */
permanent_smi_handler(void)1970 static inline int permanent_smi_handler(void)
1971 {
1972 return CONFIG(HAVE_SMI_HANDLER);
1973 }
1974
acpi_s3_resume_allowed(void)1975 static inline int acpi_s3_resume_allowed(void)
1976 {
1977 return CONFIG(HAVE_ACPI_RESUME);
1978 }
1979
acpi_is_wakeup_s3(void)1980 static inline int acpi_is_wakeup_s3(void)
1981 {
1982 if (!acpi_s3_resume_allowed())
1983 return 0;
1984
1985 if (ENV_ROMSTAGE_OR_BEFORE)
1986 return (acpi_get_sleep_type() == ACPI_S3);
1987
1988 return romstage_handoff_is_resume();
1989 }
1990
acpi_align_current(uintptr_t current)1991 static inline uintptr_t acpi_align_current(uintptr_t current)
1992 {
1993 return ALIGN_UP(current, 16);
1994 }
1995
1996 /* ACPI table revisions should match the revision of the ACPI spec
1997 * supported. This function keeps the table versions synced. This could
1998 * be made into a weak function if there is ever a need to override the
1999 * coreboot default ACPI spec version supported. */
2000 int get_acpi_table_revision(enum acpi_tables table);
2001 u8 get_acpi_fadt_minor_version(void);
2002
2003 #endif // !defined(__ASSEMBLER__) && !defined(__ACPI__)
2004
2005 #endif /* __ACPI_ACPI_H__ */
2006