xref: /aosp_15_r20/external/coreboot/src/include/gpio.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef __SRC_INCLUDE_GPIO_H__
4 #define __SRC_INCLUDE_GPIO_H__
5 
6 #include <soc/gpio.h> /* IWYU pragma: export */
7 
8 #ifndef __ASSEMBLER__ /* __ASSEMBLER__ also covers __ACPI__ case */
9 
10 #include <types.h>
11 
12 /* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */
13 _Static_assert(sizeof(gpio_t) <= sizeof(u32), "gpio_t doesn't fit in lb_gpio");
14 
15 /* The following functions must be implemented by SoC/board code. */
16 int gpio_get(gpio_t gpio);
17 int gpio_tx_get(gpio_t gpio);
18 void gpio_set(gpio_t gpio, int value);
19 void gpio_input_pulldown(gpio_t gpio);
20 void gpio_input_pullup(gpio_t gpio);
21 void gpio_input(gpio_t gpio);
22 void gpio_output(gpio_t gpio, int value);
23 uint32_t _gpio_base3_value(const gpio_t gpio[], int num_gpio, int binary_first);
24 
25 /*
26  * This function may be implemented by SoC/board code to provide
27  * a mapping from a GPIO pin to controller by returning the ACPI
28  * path for the controller that owns this GPIO.
29  *
30  * If not implemented the default handler will return NULL.
31  */
32 const char *gpio_acpi_path(gpio_t gpio);
33 
34 /*
35  * This function may be implemented by SoC/board code to provide
36  * a mapping from the internal representation of a GPIO to the 16bit
37  * value used in an ACPI GPIO pin table entry.
38  *
39  * If not implemented by the SOC the default handler will return 0
40  * because the underlying type of gpio_t is unknown.
41  */
42 uint16_t gpio_acpi_pin(gpio_t gpio);
43 
44 /*
45  * Read the value presented by the set of GPIOs, when each pin is interpreted
46  * as a base-2 digit (LOW = 0, HIGH = 1).
47  *
48  * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
49  * num_gpio: number of pins to read.
50  *
51  * There are also pulldown and pullup variants which default each gpio to
52  * be configured with an internal pulldown and pullup, respectively.
53  */
54 uint32_t gpio_base2_value(const gpio_t gpio[], int num_gpio);
55 uint32_t gpio_pulldown_base2_value(const gpio_t gpio[], int num_gpio);
56 uint32_t gpio_pullup_base2_value(const gpio_t gpio[], int num_gpio);
57 
58 /*
59  * Read the value presented by the set of GPIOs, when each pin is interpreted
60  * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2).
61  * Example: X1 = Z, X2 = 1 -> gpio_base3_value({GPIO(X1), GPIO(X2)}) = 5
62  * BASE3() from <base3.h> can generate numbers to compare the result to.
63  *
64  * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
65  * num_gpio: number of pins to read.
66  */
gpio_base3_value(const gpio_t gpio[],int num_gpio)67 static inline uint32_t gpio_base3_value(const gpio_t gpio[], int num_gpio)
68 {
69 	return _gpio_base3_value(gpio, num_gpio, 0);
70 }
71 
72 /*
73  * Read the value presented by the set of GPIOs, when each pin is interpreted
74  * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2) in a non-standard
75  * ternary number system where the first 2^n natural numbers are represented
76  * as they would be in a binary system (without any Z digits), and the following
77  * 3^n-2^n numbers use the remaining ternary representations in the normal
78  * ternary system order (skipping the values that were already used up).
79  * This is useful for boards which initially used a binary board ID and later
80  * decided to switch to tri-state after some revisions have already been built.
81  * Example: For num_gpio = 2 we get the following representation:
82  *
83  *   Number      X1     X0
84  *     0          0      0
85  *     1          0      1
86  *     2          1      0
87  *     3          1      1	// Start counting ternaries back at 0 after this
88  *     4          0      2	// Skipping 00 and 01 which are already used up
89  *     5          1      2	// Skipping 10 and 11 which are already used up
90  *     6          2      0
91  *     7          2      1
92  *     8          2      2
93  *
94  * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1].
95  * num_gpio: number of pins to read.
96  */
gpio_binary_first_base3_value(const gpio_t gpio[],int num_gpio)97 static inline uint32_t gpio_binary_first_base3_value(const gpio_t gpio[],
98 						     int num_gpio)
99 {
100 	return _gpio_base3_value(gpio, num_gpio, 1);
101 }
102 
103 #endif /* !__ASSEMBLER__ */
104 
105 #endif /* __SRC_INCLUDE_GPIO_H__ */
106