xref: /aosp_15_r20/external/coreboot/tests/lib/edid-test.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <stdlib.h>
4 #include <tests/test.h>
5 #include <edid.h>
6 #include <assert.h>
7 #include <string.h>
8 #include <tests/lib/edid.h>
9 
10 struct test_state {
11 	int data_size;
12 	void *data;
13 };
14 
get_raw_edid_checksum(const unsigned char * x)15 static uint8_t get_raw_edid_checksum(const unsigned char *x)
16 {
17 	unsigned char sum = 0;
18 	int i;
19 	for (i = 0; i < 127; ++i)
20 		sum += x[i];
21 
22 	return 256 - sum;
23 }
24 
edid_raw_calc_checksum(struct edid_raw * raw)25 static void edid_raw_calc_checksum(struct edid_raw *raw)
26 {
27 	raw->checksum = get_raw_edid_checksum((const unsigned char *)raw);
28 }
29 
test_decode_edid_no_edid(void ** state)30 static void test_decode_edid_no_edid(void **state)
31 {
32 	assert_int_equal(EDID_ABSENT, decode_edid(NULL, 0, NULL));
33 }
34 
test_decode_edid_invalid_header(void ** state)35 static void test_decode_edid_invalid_header(void **state)
36 {
37 	struct edid_raw raw = {.header = EDID_HEADER_INVALID_RAW};
38 	raw.checksum = get_raw_edid_checksum((const unsigned char *)&raw);
39 
40 	assert_int_equal(EDID_ABSENT, decode_edid((unsigned char *)&raw, sizeof(raw), NULL));
41 }
42 
43 /* Frame is modified example of an LCD Desktop IT display
44    from VESA E-EDID Standard Release A2. */
setup_decode_edid_basic_frame(void ** state)45 static int setup_decode_edid_basic_frame(void **state)
46 {
47 	struct edid_raw raw = {
48 		EDID_RAW_DEFAULT_PARAMS,
49 		.video_input_type =
50 			EDID_ANALOG_VSI
51 			| EDID_SIGNAL_LEVEL_0
52 			| EDID_VIDEO_SETUP_BLANK_EQ_BLACK
53 			| EDID_SEPARATE_SYNC_H_AND_V(1)
54 			| EDID_COMPOSITE_SYNC_H(1)
55 			| EDID_COMPOSITE_SYNC_ON_GREEN(1)
56 			| EDID_SERRATION_VSYNC(1),
57 		.horizontal_size = 43, /* [cm] */
58 		.vertical_size = 32,   /* [cm] */
59 		.display_gamma = 120,  /* 220% */
60 		.supported_features =
61 			EDID_STANDBY_MODE(0)
62 			| EDID_SUSPEND_MODE(0)
63 			| EDID_ACTIVE_OFF(1)
64 			| EDID_COLOR_FORMAT_RGB444
65 			| EDID_SRGB_SUPPORTED(0)
66 			| EDID_PREFERRED_TIMING_EXTENDED_INFO
67 			| EDID_DISPLAY_FREQUENCY_CONTINUOUS,
68 		.established_supported_timings = {
69 			[0] = EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz
70 			      | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz
71 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz
72 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz
73 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz
74 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz
75 			      | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz
76 			      | EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz,
77 			[1] = EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz
78 			      | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz
79 			      | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz
80 			      | EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI
81 			      | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz
82 			      | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz
83 			      | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz
84 			      | EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz,
85 		},
86 		.manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz,
87 		.standard_timings_supported = {
88 			[0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600),
89 			[1] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85),
90 
91 			[2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600),
92 			[3] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(75),
93 
94 			[4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600),
95 			[5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(70),
96 
97 			[6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600),
98 			[7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(65),
99 
100 			[8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280),
101 			[9] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85),
102 
103 			[10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280),
104 			[11] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60),
105 
106 			[12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024),
107 			[13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85),
108 
109 			[14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800),
110 			[15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85),
111 		},
112 		.descriptor_block_1 = {
113 			[0] = EDID_PIXEL_CLOCK(162000000u) & 0xFF,
114 			[1] = (EDID_PIXEL_CLOCK(162000000u) >> 8) & 0xFF,
115 
116 			/* Horizontal Addressable Video is 1600px,
117 			   Horizontal Blanking is 560px. */
118 			[2] = 0x40,
119 			[3] = 0x30,
120 			[4] = 0x62,
121 
122 			/* Vertical Addressable Video is 1200 lines,
123 			   Vertical Blanking is 50 lines. */
124 			[5] = 0xB0,
125 			[6] = 0x32,
126 			[7] = 0x40,
127 
128 			[8] = 64u,   /* Horizontal Front Porch in pixels. */
129 			[9] = 192u,  /* Horizontal Pulse Sync Width in pixels. */
130 			[10] = 0x13, /* Vertical Front Porch is 1 line. */
131 			[11] = 0x00, /* Vertical Sync Pulse Width is 3 lines. */
132 
133 			/* Horizontal Addressable Image Size is 427mm,
134 			   Vertical Addressable Image Size is 320mm. */
135 			[12] = 0xAB,
136 			[13] = 0x40,
137 			[14] = 0x11,
138 
139 			[15] = 0x00, /* Horizontal Border Size is 0px. */
140 			[16] = 0x00, /* Vertical Border Size is 0px. */
141 
142 			/* Timing is Non-Interlaced Video,
143 			   Stereo Video is not supported,
144 			   Digital separate syncs are requires. */
145 			[17] = 0x1E,
146 		},
147 		.descriptor_block_2 = {
148 			/* Display Range Limits Block Tag */
149 			[0] = 0,
150 			[1] = 0,
151 			[2] = 0,
152 			[3] = 0xFD,
153 
154 			[4] = 0,   /* Horizontal and Vertical Rate Offsets are zero. */
155 			[5] = 50u, /* Minimum Vertical Freq is 50Hz. */
156 			[6] = 90u, /* Maximum Vertical Freq is 90Hz. */
157 
158 			[7] = 30u,   /* Minimum Horizontal Freq is 30kHz. */
159 			[8] = 110u,  /* Maximum Horizontal Freq is 110kHz. */
160 			[9] = 23u,   /* Maximum Pixel Clock Freq is 230MHz. */
161 			[10] = 0x4,  /* Begin CVT Support Info */
162 			[11] = 0x11, /* Compatible with CVT Version 1.1 */
163 			[12] = 0,    /* Maximum Pixel Clock Freq remains at 230MHz. */
164 			[13] = 200,  /* Maximum Active Pixels per Line is 1600. */
165 			[14] = 0x90, /* Supported aspect ratios: 4:3, 5:4. */
166 
167 			/* Preferred Aspect Ratio is 4:3, Standard CVT Blanking is supported. */
168 			[15] = 0,
169 			[16] = 0x50, /* H. & V. Stretch are supported and Shrinks are not. */
170 			[17] = 60u,  /* Preferred Refresh Rate is 60Hz. */
171 		},
172 		.descriptor_block_3 = {
173 			/* Established Timings III Block Tag */
174 			[0] = 0,
175 			[1] = 0,
176 			[2] = 0,
177 			[3] = 0xF7,
178 			[4] = 0,
179 
180 			[5] = 10u, /* VESA DMT Standard Version #10 */
181 			/*
182 			 * 640x350@85Hz,
183 			 * 640x400@85Hz,
184 			 * 720x400@85Hz,
185 			 * 640x480@85Hz,
186 			 * 800x600@85Hz,
187 			 * 1024x768@85Hz,
188 			 * 1152x864@75Hz are supported.
189 			 */
190 			[6] = 0x7F,
191 
192 			/*
193 			 * 1280x960@60Hz,
194 			 * 1280x960@85Hz,
195 			 * 1280x1024@60Hz,
196 			 * 1280x1024@85Hz are supported.
197 			 */
198 			[7] = 0x0F,
199 
200 			/*
201 			 * 1400x1050@60Hz (Normal Blanking),
202 			 * 1400x1050@75Hz are supported.
203 			 */
204 			[8] = 0x03,
205 
206 			/*
207 			 * 1400x1050@85Hz,
208 			 * 1600x1200@60Hz,
209 			 * 1600x1200@65Hz,
210 			 * 1600x1200@70Hz are supported.
211 			 */
212 			[9] = 0x87,
213 
214 			/*
215 			 * 1600x1200@75Hz,
216 			 * 1600x1200@85Hz are supported.
217 			 */
218 			[10] = 0xC0,
219 
220 			/* 1920 timings not supported. */
221 			[11] = 0x0,
222 
223 			[12 ... 17] = 0,
224 		},
225 		.descriptor_block_4 = {
226 			/* Display Product Name Block Tag */
227 			[0] = 0,
228 			[1] = 0,
229 			[2] = 0,
230 			[3] = 0xFC,
231 			[4] = 0,
232 
233 			/* Product name */
234 			[5] = 'A',
235 			[6] = 'B',
236 			[7] = 'C',
237 			[8] = ' ',
238 			[9] = 'L',
239 			[10] = 'C',
240 			[11] = 'D',
241 			[12] = '2',
242 			[13] = '1',
243 			[14] = '\n',
244 			[15] = ' ',
245 			[16] = ' ',
246 			[17] = ' ',
247 		},
248 		.extension_flag = 0x0, /* No extensions */
249 	};
250 
251 	edid_raw_calc_checksum(&raw);
252 
253 	*state = malloc(sizeof(struct test_state));
254 
255 	struct test_state ts = {.data_size = sizeof(struct edid_raw),
256 				.data = malloc(sizeof(struct edid_raw))};
257 
258 	memcpy(ts.data, &raw, sizeof(raw));
259 	memcpy(*state, &ts, sizeof(ts));
260 
261 	return 0;
262 }
263 
264 /* Test decoding of EDID frame without extensions. */
test_decode_edid_basic_frame(void ** state)265 static void test_decode_edid_basic_frame(void **state)
266 {
267 	struct edid out;
268 	struct test_state *ts = *state;
269 
270 	/* In real-life situations frames often are not 100% conformant,
271 	   but are at least correct when it comes to key data fields. */
272 	assert_int_equal(EDID_CONFORMANT,
273 			 decode_edid((unsigned char *)ts->data, ts->data_size, &out));
274 
275 	assert_int_equal(32, out.framebuffer_bits_per_pixel);
276 	assert_int_equal(0, out.panel_bits_per_color);
277 	assert_int_equal(0, out.panel_bits_per_pixel);
278 	assert_int_equal(0, out.link_clock);
279 	assert_int_equal(1600, out.x_resolution);
280 	assert_int_equal(1200, out.y_resolution);
281 	assert_int_equal(6400, out.bytes_per_line);
282 	assert_int_equal(0, out.hdmi_monitor_detected);
283 	assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string)));
284 	assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME);
285 
286 	/* Mode */
287 	assert_null(out.mode.name);
288 	assert_int_equal(162000, out.mode.pixel_clock);
289 	assert_int_equal(1, out.mode.lvds_dual_channel);
290 	assert_int_equal(0, out.mode.refresh);
291 	assert_int_equal(1600, out.mode.ha);
292 	assert_int_equal(560, out.mode.hbl);
293 	assert_int_equal(64, out.mode.hso);
294 	assert_int_equal(192, out.mode.hspw);
295 	assert_int_equal(0, out.mode.hborder);
296 	assert_int_equal(1200, out.mode.va);
297 	assert_int_equal(50, out.mode.vbl);
298 	assert_int_equal(1, out.mode.vso);
299 	assert_int_equal(0, out.mode.vborder);
300 	assert_int_equal(43, out.mode.phsync);
301 	assert_int_equal(43, out.mode.pvsync);
302 	assert_int_equal(0, out.mode.x_mm);
303 	assert_int_equal(0, out.mode.y_mm);
304 
305 	assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]);
306 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]);
307 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]);
308 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]);
309 }
310 
311 /* Frame is modified example of base EDID frame with CEA861 extension
312    for DTV Display from VESA E-EDID Standard Release A2. */
setup_decode_edid_dtv_frame_with_extension(void ** state)313 static int setup_decode_edid_dtv_frame_with_extension(void **state)
314 {
315 	struct edid_raw raw = {
316 		EDID_RAW_DEFAULT_PARAMS,
317 		.video_input_type =
318 			EDID_DIGITAL_VSI
319 			| EDID_INTERFACE_HDMI_A
320 			| EDID_COLOR_BIT_DEPTH_8B,
321 		.horizontal_size = 16, /* Aspect ratio 16:9 in landscape. */
322 		.vertical_size = 0,    /* Landscape flag */
323 		.display_gamma = 120,  /* 220% */
324 		.supported_features =
325 			EDID_STANDBY_MODE(0)
326 			| EDID_SUSPEND_MODE(0)
327 			| EDID_ACTIVE_OFF(0)
328 			| EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422
329 			| EDID_SRGB_SUPPORTED(1)
330 			| EDID_PREFERRED_TIMING_EXTENDED_INFO
331 			| EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS,
332 
333 		.established_supported_timings = {
334 			[0] = EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz,
335 			[1] = 0,
336 		},
337 		.manufacturers_reserved_timing = 0,
338 		.standard_timings_supported = {
339 			[0 ... 15] = 0,
340 		},
341 		.descriptor_block_1 = {
342 			[0] = EDID_PIXEL_CLOCK(148500000u) & 0xFF,
343 			[1] = (EDID_PIXEL_CLOCK(148500000u) >> 8) & 0xFF,
344 
345 			/* Horizontal Addressable Video is 1920px,
346 			   Horizontal Blanking is 280px. */
347 			[2] = 0x80,
348 			[3] = 0x18,
349 			[4] = 0x71,
350 
351 			/* Vertical Addressable Video is 1080 lines,
352 			   Vertical Blanking is 45 lines. */
353 			[5] = 0x38,
354 			[6] = 0x2D,
355 			[7] = 0x40,
356 
357 			[8] = 88u, /* Horizontal Front Porch in pixels. */
358 			[9] = 44u, /* Horizontal Pulse Sync Width in pixels. */
359 			[10] = 4u, /* Vertical Front Porch is 4 lines. */
360 			[11] = 5u, /* Vertical Sync Pulse Width is 5 lines. */
361 
362 			/* Horizontal Addressable Image Size is 1039mm,
363 			   Vertical Addressable Image Size is 584mm. */
364 			[12] = 0x0F,
365 			[13] = 0x48,
366 			[14] = 0x42,
367 
368 			[15] = 0x00, /* Horizontal Border Size is 0px. */
369 			[16] = 0x00, /* Vertical Border Size is 0px. */
370 
371 			/* Timing is Non-Interlaced Video,
372 			   Stereo Video is not supported,
373 			   Digital separate and syncs are requires. */
374 			[17] = 0x1E,
375 		},
376 		.descriptor_block_2 = {
377 			[0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF,
378 			[1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF,
379 
380 			/* Horizontal Addressable Video is 1920px,
381 			   Horizontal Blanking is 280px. */
382 			[2] = 0x80,
383 			[3] = 0x18,
384 			[4] = 0x71,
385 
386 			/* Vertical Addressable Video is 540 lines,
387 			   Vertical Blanking is 22 lines. */
388 			[5] = 0x1C,
389 			[6] = 0x16,
390 			[7] = 0x20,
391 
392 			[8] = 88u,   /* Horizontal Front Porch in pixels. */
393 			[9] = 44u,   /* Horizontal Pulse Sync Width in pixels. */
394 			[10] = 0x25, /* Vertical Front Porch is 2 lines. */
395 			[11] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */
396 
397 			/* Horizontal Addressable Image Size is 1039mm,
398 			   Vertical Addressable Image Size is 584mm. */
399 			[12] = 0x0F,
400 			[13] = 0x48,
401 			[14] = 0x42,
402 
403 			[15] = 0x00, /* Horizontal Border Size is 0px. */
404 			[16] = 0x00, /* Vertical Border Size is 0px. */
405 
406 			/* Timing is Interlaced Video,
407 			   Stereo Video is not supported,
408 			   Digital separate and syncs are requires. */
409 			[17] = 0x9E,
410 		},
411 		.descriptor_block_3 = {
412 			[0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF,
413 			[1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF,
414 
415 			/* Horizontal Addressable Video is 1280px,
416 			   Horizontal Blanking is 370px. */
417 			[2] = 0x00,
418 			[3] = 0x72,
419 			[4] = 0x51,
420 
421 			/* Vertical Addressable Video is 720 lines,
422 			   Vertical Blanking is 30 lines. */
423 			[5] = 0xD0,
424 			[6] = 0x1E,
425 			[7] = 0x20,
426 
427 			[8] = 110u,   /* Horizontal Front Porch in pixels. */
428 			[9] = 40u,    /* Horizontal Pulse Sync Width in pixels. */
429 			[10] = 0x55u, /* Vertical Front Porch is 5 lines. */
430 			[11] = 0x00,  /* Vertical Sync Pulse Width is 5 lines. */
431 
432 			/* Horizontal Addressable Image Size is 1039mm,
433 			   Vertical Addressable Image Size is 584mm. */
434 			[12] = 0x0F,
435 			[13] = 0x48,
436 			[14] = 0x42,
437 
438 			[15] = 0x00, /* Horizontal Border Size is 0px. */
439 			[16] = 0x00, /* Vertical Border Size is 0px. */
440 
441 			/* Timing is Non-Interlaced Video,
442 			   Stereo Video is not supported,
443 			   Digital separate syncs are requires. */
444 			[17] = 0x1E,
445 		},
446 		.descriptor_block_4 = {
447 			/* Display Product Name Block Tag */
448 			[0] = 0,
449 			[1] = 0,
450 			[2] = 0,
451 			[3] = 0xFC,
452 			[4] = 0,
453 
454 			/* Product name */
455 			[5] = 'A',
456 			[6] = 'B',
457 			[7] = 'C',
458 			[8] = ' ',
459 			[9] = 'L',
460 			[10] = 'C',
461 			[11] = 'D',
462 			[12] = '4',
463 			[13] = '7',
464 			[14] = 'w',
465 			[15] = '\n',
466 			[16] = ' ',
467 			[17] = ' ',
468 		},
469 		.extension_flag = 0x0, /* No extensions */
470 	};
471 
472 	edid_raw_calc_checksum(&raw);
473 
474 	unsigned char ext[128] = {
475 		[0] = 0x02, /* CEA 861 Extension Block Tag Code */
476 		[1] = 0x03, /* CEA 861 Block Version */
477 
478 		[2] = 0x18, /* Detail Timing Descriptors start 0x18 bytes from here. */
479 
480 		/* Underscan is not supported,
481 		   Basic Audio is supported,
482 		   YCbCr 4:4:4 & YCbCr 4:2:2 are supported,
483 		   Number of native formats: 2. */
484 		[3] = 0x72,
485 
486 		/* Video Data Block Tag Code is 2,
487 		   Number of Short Video Descriptor Bytes is 7. */
488 		[4] = 0x47,
489 
490 		/* 1920x1080p 59.94/60 Hz 16 : 9 AR (CEA Format #16)
491 		   is a supported Native Format. */
492 		[5] = 0x90,
493 
494 		/* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5)
495 		   is a supported Native Format. */
496 		[6] = 0x85,
497 
498 		/* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */
499 		[7] = 0x04,
500 
501 		/* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */
502 		[8] = 0x03,
503 
504 		/* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */
505 		[9] = 0x02,
506 
507 		/* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */
508 		[10] = 0x07,
509 
510 		/* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */
511 		[11] = 0x06,
512 
513 		/* Audio Data Block Tag Code is 1,
514 		   Number of Short Audio Descriptor Bytes is 3. */
515 		[12] = 0x23,
516 
517 		/* Audio Format Tag Code is 1 --- LPCM is supported,
518 		   Maximum number of audio channels is 2. */
519 		[13] = 0x09,
520 
521 		/* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */
522 		[14] = 0x07,
523 
524 		/* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */
525 		[15] = 0x07,
526 
527 		/* Speaker Allocation Block Tag Code is 4,
528 		   Number of Speaker Allocation Descriptor Bytes is 3. */
529 		[16] = 0x83,
530 
531 		/* Speaker Allocation is Front-Left & Front-Right. */
532 		[17] = 0x01,
533 
534 		/* Reserved */
535 		[18 ... 19] = 0,
536 
537 		/* Vendor Specific Data Block Tag Code is 3,
538 		   Number of Vendor Specific Data Bytes is 5. */
539 		[20] = 0x65,
540 
541 		/* 24bit IEEE registration Identifier is 0x000C03. */
542 		[21] = 0x03,
543 		[22] = 0x0C,
544 		[23] = 0x00,
545 
546 		/* Vendor Specific Data is 0x10000. */
547 		[24] = 0x01,
548 		[25] = 0x00,
549 
550 		/* Descriptor Block 5 [18 Bytes] */
551 
552 		[26] = EDID_PIXEL_CLOCK(27027000u) & 0xFF,
553 		[27] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF,
554 
555 		/* Horizontal Addressable Video is 720px,
556 		   Horizontal Blanking is 138 px. */
557 		[28] = 0xD0,
558 		[29] = 0x8A,
559 		[30] = 0x20,
560 
561 		/* Vertical Addressable Video is 480 lines,
562 		   Vertical Blanking is 45 lines. */
563 		[31] = 0xE0,
564 		[32] = 0x2D,
565 		[33] = 0x10,
566 
567 		[34] = 16u,  /* Horizontal Front Porch in pixels. */
568 		[35] = 62u,  /* Horizontal Sync Pulse Width in pixels. */
569 		[36] = 0x96, /* Vertical Front Porch is 9 lines. */
570 		[37] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */
571 
572 		/* Displayed Image Aspect Ratio is 16:9 */
573 		[38] = 16u,
574 		[39] = 9u,
575 		[40] = 0u,
576 
577 		/* Horizontal and Vertical Border Size is 0 px */
578 		[41] = 0u,
579 		[42] = 0u,
580 
581 		/* Timing is Interlaced Video,
582 		   Stereo Video is not supported,
583 		   Digital Separate Syncs are required. */
584 		[43] = 0x18,
585 
586 		/* Descriptor Block 6 [18 Bytes] */
587 
588 		[44] = EDID_PIXEL_CLOCK(27027000u) & 0xFF,
589 		[45] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF,
590 
591 		/* Horizontal Addressable Video is 720px,
592 		   Horizontal Blanking is 138 px. */
593 		[46] = 0xD0,
594 		[47] = 0x8A,
595 		[48] = 0x20,
596 
597 		/* Vertical Addressable Video is 480 lines,
598 		   Vertical Blanking is 45 lines. */
599 		[49] = 0xE0,
600 		[50] = 0x2D,
601 		[51] = 0x10,
602 
603 		[52] = 16u,  /* Horizontal Front Porch in pixels. */
604 		[53] = 62u,  /* Horizontal Sync Pulse Width in pixels. */
605 		[54] = 0x96, /* Vertical Front Porch is 9 lines. */
606 		[55] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */
607 
608 		/* Displayed Image Aspect Ratio is 4:3. */
609 		[56] = 4u,
610 		[57] = 3u,
611 		[58] = 0u,
612 
613 		/* Horizontal and Vertical Border Size is 0px. */
614 		[59] = 0u,
615 		[60] = 0u,
616 
617 		/* Timing is Interlaced Video,
618 		   Stereo Video is not supported,
619 		   Digital Separate Syncs are required. */
620 		[61] = 0x18,
621 
622 		/* Descriptor Block 7 [18 Bytes] */
623 
624 		[62] = EDID_PIXEL_CLOCK(27027000u) & 0xFF,
625 		[63] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF,
626 
627 		/* Horizontal Addressable Video is 1440px,
628 		   Horizontal Blanking is 276 px. */
629 		[64] = 0xA0,
630 		[65] = 0x14,
631 		[66] = 0x51,
632 
633 		/* Vertical Addressable Video is 240 lines,
634 		   Vertical Blanking is 23 lines. */
635 		[67] = 0xF0,
636 		[68] = 0x16,
637 		[69] = 0x00,
638 
639 		[70] = 38u,  /* Horizontal Front Porch in pixels. */
640 		[71] = 124u, /* Horizontal Sync Pulse Width in pixels. */
641 		[72] = 0x43, /* Vertical Front Porch is 9 lines. */
642 		[73] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */
643 
644 		/* Displayed Image Aspect Ratio is 16:9 */
645 		[74] = 16u,
646 		[75] = 9u,
647 		[76] = 0u,
648 
649 		/* Horizontal and Vertical Border Size is 0px. */
650 		[77] = 0u,
651 		[78] = 0u,
652 
653 		/* Timing is Interlaced Video,
654 		   Stereo Video is not supported,
655 		   Digital Separate Syncs are required. */
656 		[79] = 0x98,
657 
658 		/* Descriptor Block 8 [18 Bytes] */
659 
660 		[80] = EDID_PIXEL_CLOCK(27027000u) & 0xFF,
661 		[81] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF,
662 
663 		/* Horizontal Addressable Video is 1440px,
664 		   Horizontal Blanking is 276 px. */
665 		[82] = 0xA0,
666 		[83] = 0x14,
667 		[84] = 0x51,
668 
669 		/* Vertical Addressable Video is 240 lines,
670 		   Vertical Blanking is 23 lines. */
671 		[85] = 0xF0,
672 		[86] = 0x16,
673 		[87] = 0x00,
674 
675 		[88] = 38u,  /* Horizontal Front Porch in pixels. */
676 		[89] = 124u, /* Horizontal Sync Pulse Width in pixels. */
677 		[90] = 0x43, /* Vertical Front Porch is 9 lines. */
678 		[91] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */
679 
680 		/* Displayed Image Aspect Ratio is 4:3. */
681 		[92] = 4u,
682 		[93] = 3u,
683 		[94] = 0u,
684 
685 		/* Horizontal and Vertical Border Size is 0px. */
686 		[95] = 0u,
687 		[96] = 0u,
688 
689 		/* Timing is Interlaced Video,
690 		   Stereo Video is not supported,
691 		   Digital Separate Syncs are required. */
692 		[97] = 0x98,
693 
694 		[99 ... 126] = 0};
695 
696 	ext[127] = get_raw_edid_checksum(ext);
697 
698 	*state = malloc(sizeof(struct test_state));
699 
700 	struct test_state ts = {.data_size = sizeof(raw) + sizeof(ext),
701 				.data = malloc(sizeof(raw) + sizeof(ext))};
702 
703 	memcpy(ts.data, &raw, sizeof(raw));
704 	memcpy(ts.data + sizeof(raw), &ext[0], sizeof(ext));
705 
706 	memcpy(*state, &ts, sizeof(ts));
707 
708 	return 0;
709 }
710 
711 /* Test decoding of EDID frame with one extension. */
test_decode_edid_dtv_frame_with_extension(void ** state)712 static void test_decode_edid_dtv_frame_with_extension(void **state)
713 {
714 	struct edid out;
715 	struct test_state *ts = *state;
716 
717 	/* In real-life situations frames often are not 100% conformant,
718 	   but are at least correct when it comes to key data fields. */
719 	assert_int_equal(EDID_CONFORMANT,
720 			 decode_edid((unsigned char *)ts->data, ts->data_size, &out));
721 
722 	assert_int_equal(32, out.framebuffer_bits_per_pixel);
723 	assert_int_equal(8, out.panel_bits_per_color);
724 	assert_int_equal(24, out.panel_bits_per_pixel);
725 	assert_int_equal(0, out.link_clock);
726 	assert_int_equal(1920, out.x_resolution);
727 	assert_int_equal(1080, out.y_resolution);
728 	assert_int_equal(7680, out.bytes_per_line);
729 	assert_int_equal(1, out.hdmi_monitor_detected);
730 	assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string)));
731 	assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME);
732 
733 	/* Mode */
734 	assert_null(out.mode.name);
735 	assert_int_equal(148500, out.mode.pixel_clock);
736 	assert_int_equal(1, out.mode.lvds_dual_channel);
737 	assert_int_equal(0, out.mode.refresh);
738 	assert_int_equal(1920, out.mode.ha);
739 	assert_int_equal(280, out.mode.hbl);
740 	assert_int_equal(88, out.mode.hso);
741 	assert_int_equal(44, out.mode.hspw);
742 	assert_int_equal(0, out.mode.hborder);
743 	assert_int_equal(1080, out.mode.va);
744 	assert_int_equal(45, out.mode.vbl);
745 	assert_int_equal(16, out.mode.vso);
746 	assert_int_equal(0, out.mode.vborder);
747 	assert_int_equal(43, out.mode.phsync);
748 	assert_int_equal(43, out.mode.pvsync);
749 	assert_int_equal(0, out.mode.x_mm);
750 	assert_int_equal(0, out.mode.y_mm);
751 
752 	assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]);
753 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]);
754 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]);
755 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]);
756 }
757 
758 
759 /* Test decoding of EDID frame with one extension. Tested frame is modified
760    example of base EDID frame with CEA861 extension for IT/DTV Display from
761    VESA E-EDID Standard Release A2. */
setup_decode_edid_it_dtv_frame_with_extension(void ** state)762 static int setup_decode_edid_it_dtv_frame_with_extension(void **state)
763 {
764 	struct edid_raw raw = {
765 		EDID_RAW_DEFAULT_PARAMS,
766 		.video_input_type =
767 			EDID_DIGITAL_VSI
768 			| EDID_INTERFACE_HDMI_A
769 			| EDID_COLOR_BIT_DEPTH_8B,
770 		.horizontal_size = 121, /* Aspect ratio 16:9 in landscape */
771 		.vertical_size = 68,	/* Landscape flag */
772 		.display_gamma = 120,	/* 220% */
773 		.supported_features =
774 			EDID_STANDBY_MODE(0)
775 			| EDID_SUSPEND_MODE(0)
776 			| EDID_ACTIVE_OFF(0)
777 			| EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422
778 			| EDID_SRGB_SUPPORTED(1)
779 			| EDID_PREFERRED_TIMING_EXTENDED_INFO
780 			| EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS,
781 		.established_supported_timings = {
782 			[0] = EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz
783 			      | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz
784 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz
785 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz
786 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz
787 			      | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz
788 			      | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz
789 			      | EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz,
790 			[1] = EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz
791 			      | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz
792 			      | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz
793 			      | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz
794 			      | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz
795 			      | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz
796 			      | EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz,
797 		},
798 		.manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz,
799 		.standard_timings_supported = {
800 			[0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280),
801 			[1] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85),
802 
803 			[2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280),
804 			[3] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60),
805 
806 			[4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280),
807 			[5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85),
808 
809 			[6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280),
810 			[7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60),
811 
812 			[8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024),
813 			[9] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85),
814 
815 			[10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(848),
816 			[11] = EDID_ASPECT_RATIO_16_9 | EDID_FIELD_REFRESH_RATE(60),
817 
818 			[12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800),
819 			[13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60),
820 
821 			[14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(640),
822 			[15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60),
823 		},
824 		.descriptor_block_1 = {
825 			[0] = EDID_PIXEL_CLOCK(85500000u) & 0xFF,
826 			[1] = (EDID_PIXEL_CLOCK(85500000u) >> 8) & 0xFF,
827 
828 			/* Horizontal Addressable Video is 1360px,
829 			   Horizontal Blanking is 432px. */
830 			[2] = 0x50,
831 			[3] = 0xB0,
832 			[4] = 0x51,
833 
834 			/* Vertical Addressable Video is 768 lines,
835 			   Vertical Blanking is 27 lines. */
836 			[5] = 0x00,
837 			[6] = 0x1B,
838 			[7] = 0x30,
839 
840 			[8] = 64u,   /* Horizontal Front Porch in pixels. */
841 			[9] = 112u,  /* Horizontal Pulse Sync Width in pixels. */
842 			[10] = 0x36, /* Vertical Front Porch is 3 lines. */
843 			[11] = 0u,   /* Vertical Sync Pulse Width is 6 lines. */
844 
845 			/* Horizontal Addressable Image Size is 1214mm,
846 			   Vertical Addressable Image Size is 683mm. */
847 			[12] = 0xBE,
848 			[13] = 0xAB,
849 			[14] = 0x42,
850 
851 			[15] = 0x00, /* Horizontal border size is 0px. */
852 			[16] = 0x00, /* Vertical Border Size is 0px. */
853 
854 			/* Timing is Non-Interlaced Video,
855 			   Stereo Video is not supported,
856 			   Digital separate and syncs are requires. */
857 			[17] = 0x1E,
858 		},
859 		.descriptor_block_2 = {
860 			[0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF,
861 			[1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF,
862 
863 			/* Horizontal Addressable Video is 1280px,
864 			   Horizontal Blanking is 370px. */
865 			[2] = 0x00,
866 			[3] = 0x72,
867 			[4] = 0x51,
868 
869 			/* Vertical Addressable Video is 720 lines,
870 			   Vertical Blanking is 30 lines. */
871 			[5] = 0xD0,
872 			[6] = 0x1E,
873 			[7] = 0x20,
874 
875 			[8] = 110u,  /* Horizontal Front Porch in pixels. */
876 			[9] = 40u,   /* Horizontal Pulse Sync Width in pixels. */
877 			[10] = 0x55, /* Vertical Front Porch is 5 lines. */
878 			[11] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */
879 
880 			/* Horizontal Addressable Image Size is 1214mm,
881 			   Vertical Addressable Image Size is 683mm. */
882 			[12] = 0xBE,
883 			[13] = 0xAB,
884 			[14] = 0x42,
885 
886 			[15] = 0x00, /* Horizontal border size is 0px. */
887 			[16] = 0x00, /* Vertical Border Size is 0px. */
888 
889 			/* Timing is Non-Interlaced Video,
890 			   Stereo Video is not supported,
891 			   Digital separate and syncs are required. */
892 			[17] = 0x1E,
893 		},
894 		.descriptor_block_3 = {
895 			/* Established timings III Block Tag */
896 			[0 ... 2] = 0u,
897 			[3] = 0xF7,
898 			[4] = 0u,
899 
900 			/* VESA DMT Standard Version #10 */
901 			[5] = 10u,
902 
903 			/*
904 			 * 640x350@85Hz,
905 			 * 640x400@85Hz,
906 			 * 720x400@85Hz,
907 			 * 640x480@85Hz,
908 			 * 800x600@85Hz,
909 			 * 1024x768@85Hz,
910 			 * 1152x864@75Hz are supported.
911 			 */
912 			[6] = 0x7F,
913 
914 			/*
915 			 * 1280x960@60Hz,
916 			 * 1280x960@85Hz,
917 			 * 1280x1024@60Hz,
918 			 * 1280x1024@85Hz
919 			 */
920 			[7] = 0x0F,
921 
922 			/*
923 			 * 1400x1050@60Hz (Normal Blanking),
924 			 * 1400x1050@75Hz are supported.
925 			 */
926 			[8] = 0x03,
927 
928 			/*
929 			 * 1400x1050@85Hz,
930 			 * 1600x1200@60Hz,
931 			 * 1600x1200@65Hz,
932 			 * 1600x1200@70Hz are supported.
933 			 */
934 			[9] = 0x87,
935 
936 			/*
937 			 * 1600x1200@75Hz,
938 			 * 1600x1200@85Hz are supported.
939 			 */
940 			[10] = 0xC0,
941 
942 			/* 1920 PC Timings are not supported. */
943 			[11] = 0u,
944 
945 			/* Reserved */
946 			[12 ... 17] = 0,
947 		},
948 		.descriptor_block_4 = {
949 			/* Display Product Name Block Tag */
950 			[0] = 0,
951 			[1] = 0,
952 			[2] = 0,
953 			[3] = 0xFC,
954 			[4] = 0,
955 
956 			/* Product name */
957 			[5] = 'A',
958 			[6] = 'B',
959 			[7] = 'C',
960 			[8] = ' ',
961 			[9] = 'P',
962 			[10] = 'L',
963 			[11] = 'A',
964 			[12] = '5',
965 			[13] = '5',
966 			[14] = '\n',
967 			[15] = ' ',
968 			[16] = ' ',
969 			[17] = ' ',
970 		},
971 		.extension_flag = 0x0, /* No extensions */
972 	};
973 
974 	edid_raw_calc_checksum(&raw);
975 
976 	unsigned char ext[128] = {
977 		[0] = 0x02, /* CEA 861 Extension Block Tag Code */
978 		[1] = 0x03, /* CEA 861 Block Version */
979 		[2] = 0x17, /* Detail Timing Descriptors start 0x17 bytesfrom here */
980 
981 		/* Underscan is supported,
982 		   Basic Audio is supported,
983 		   YCbCr 4:4:4 & YCbCr 4:2:2 are supported,
984 		   Number of native formats: 0. */
985 		[3] = 0xF0,
986 
987 		/* Video Data Block Tag Code is 2.
988 		   Number of Short Video Descriptor Bytes is 6. */
989 		[4] = 0x46,
990 
991 		/* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) is a supported format. */
992 		[5] = 0x05,
993 
994 		/* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */
995 		[6] = 0x04,
996 
997 		/* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */
998 		[7] = 0x03,
999 
1000 		/* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */
1001 		[8] = 0x02,
1002 
1003 		/* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */
1004 		[9] = 0x07,
1005 
1006 		/* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */
1007 		[10] = 0x06,
1008 
1009 		/* Audio Data Block Tag Code is 1,
1010 		   Number of Short Audio Descriptor Bytes is 3. */
1011 		[11] = 0x23,
1012 
1013 		/* Audio Format Tag Code is 1 --- LPCM is supported,
1014 		   Maximum number of audio channels is 2. */
1015 		[12] = 0x09,
1016 
1017 		/* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */
1018 		[13] = 0x07,
1019 
1020 		/* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */
1021 		[14] = 0x07,
1022 
1023 		/* Speaker Allocation Block Tag Code is 4,
1024 		   Number of Speaker Allocation Descriptor Bytes is 3. */
1025 		[15] = 0x83,
1026 
1027 		/* Speaker Allocation is Front-Left & Front-Right */
1028 		[16] = 0x01,
1029 
1030 		/* Reserved */
1031 		[17 ... 18] = 0,
1032 
1033 		/* Vendor Specific Data Block Tag Code is 3,
1034 		   Number of Vendor Specific Data Bytes is 5. */
1035 		[19] = 0x65,
1036 
1037 		/* 24bit IEEE registration Identifier is 0x000C03. */
1038 		[20] = 0x03,
1039 		[21] = 0x0C,
1040 		[22] = 0x00,
1041 
1042 		/* Vendor Specific Data is 0x10000. */
1043 		[23] = 0x01,
1044 		[24] = 0x00,
1045 
1046 		/* Descriptor Block 5 [18 Bytes] */
1047 
1048 		[25] = EDID_PIXEL_CLOCK(74250000u) & 0xFF,
1049 		[26] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF,
1050 
1051 		/* Horizontal Addressable Video is 1920px,
1052 		   Horizontal Blanking is 280px. */
1053 		[27] = 0x80,
1054 		[28] = 0x18,
1055 		[29] = 0x71,
1056 
1057 		/* Vertical Addressable Video is 540 lines,
1058 		   Vertical Blanking is 22 lines. */
1059 		[30] = 0x1C,
1060 		[31] = 0x16,
1061 		[32] = 0x20,
1062 
1063 		[33] = 88u,  /* Horizontal Front Porch in pixels. */
1064 		[34] = 44u,  /* Horizontal Sync Pulse Width in pixels. */
1065 		[35] = 0x25, /* Vertical Front Porch is 2 lines. */
1066 		[36] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */
1067 
1068 		/* Image size: 1039mm x 584mm */
1069 		[37] = 0x0F,
1070 		[38] = 0x48,
1071 		[39] = 0x42,
1072 
1073 		/* Horizontal and Vertical Border Size is 0px. */
1074 		[40] = 0u,
1075 		[41] = 0u,
1076 
1077 		/* Timing is Interlaced Video,
1078 		   Stereo Video is not supported,
1079 		   Digital Separate Syncs are required. */
1080 		[42] = 0x9E,
1081 
1082 		/* Descriptor Block 6 [18 Bytes] */
1083 
1084 		[43] = EDID_PIXEL_CLOCK(74250000u) & 0xFF,
1085 		[44] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF,
1086 
1087 		/* Horizontal Addressable Video is 1280px,
1088 		   Horizontal Blanking is 370 px. */
1089 		[45] = 0x00,
1090 		[46] = 0x72,
1091 		[47] = 0x51,
1092 
1093 		/* Vertical Addressable Video is 720 lines,
1094 		   Vertical Blanking is 30 lines. */
1095 		[48] = 0xD0,
1096 		[49] = 0x1E,
1097 		[50] = 0x20,
1098 
1099 		[51] = 110u, /* Horizontal Front Porch in pixels. */
1100 		[52] = 40u,  /* Horizontal Sync Pulse Width in pixels. */
1101 		[53] = 0x55, /* Vertical Front Porch is 5 lines. */
1102 		[54] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */
1103 
1104 		/* Image size: 1039mm x 584mm */
1105 		[55] = 0x0F,
1106 		[56] = 0x48,
1107 		[57] = 0x42,
1108 
1109 		/* Horizontal and Vertical Border Size is 0px. */
1110 		[58] = 0u,
1111 		[59] = 0u,
1112 
1113 		/* Timing is Non-Interlaced Video,
1114 		   Stereo Video is not supported,
1115 		   Digital Separate Syncs are required. */
1116 		[60] = 0x1E,
1117 
1118 		/* Descriptor Block 7 [18 Bytes] */
1119 
1120 		[61] = EDID_PIXEL_CLOCK(27000000u) & 0xFF,
1121 		[62] = (EDID_PIXEL_CLOCK(27000000u) >> 8) & 0xFF,
1122 
1123 		/* Horizontal Addressable Video is 1440px,
1124 		   Horizontal Blanking is 276 px. */
1125 		[63] = 0xA0,
1126 		[64] = 0x14,
1127 		[65] = 0x51,
1128 
1129 		/* Vertical Addressable Video is 240 lines,
1130 		   Vertical Blanking is 23 lines. */
1131 		[66] = 0xF0,
1132 		[67] = 0x16,
1133 		[68] = 0x00,
1134 
1135 		[69] = 38u,  /* Horizontal Front Porch in pixels. */
1136 		[70] = 124u, /* Horizontal Sync Pulse Width in pixels. */
1137 		[71] = 0x43, /* Vertical Front Porch is 4 lines. */
1138 		[72] = 0x00, /* Vertical Sync Pulse Width is 3 lines. */
1139 
1140 		/* Image size: 1039mm x 584mm */
1141 		[73] = 0x0F,
1142 		[74] = 0x48,
1143 		[75] = 0x42,
1144 
1145 		/* Horizontal and Vertical Border Size is 0px. */
1146 		[76] = 0u,
1147 		[77] = 0u,
1148 
1149 		/* Timing is Interlaced Video,
1150 		   Stereo Video is not supported,
1151 		   Digital Separate Syncs are required. */
1152 		[78] = 0x18,
1153 
1154 		/* Descriptor Block 8 [18 Bytes] */
1155 
1156 		[79] = EDID_PIXEL_CLOCK(27027000u) & 0xFF,
1157 		[80] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF,
1158 
1159 		/* Horizontal Addressable Video is 1440px,
1160 		   Horizontal Blanking is 276 px. */
1161 		[81] = 0xA0,
1162 		[82] = 0x14,
1163 		[83] = 0x51,
1164 
1165 		/* Vertical Addressable Video is 240 lines,
1166 		   Vertical Blanking is 23 lines. */
1167 		[84] = 0xF0,
1168 		[85] = 0x16,
1169 		[86] = 0x00,
1170 
1171 		[87] = 38u,  /* Horizontal Front Porch in pixels. */
1172 		[88] = 124u, /* Horizontal Sync Pulse Width in pixels. */
1173 		[89] = 0x43, /* Vertical Front Porch is 4 lines. */
1174 		[90] = 0x00, /* Vertical Sync Pulse Width is 3 lines. */
1175 
1176 		/* Image size: 1039mm x 584mm */
1177 		[91] = 0x0F,
1178 		[92] = 0x48,
1179 		[93] = 0x42,
1180 
1181 		/* Horizontal and Vertical Border Size is 0px. */
1182 		[94] = 0u,
1183 		[95] = 0u,
1184 
1185 		/* Timing is Interlaced Video,
1186 		   Stereo Video is not supported,
1187 		   Digital Separate Syncs are required. */
1188 		[96] = 0x98,
1189 
1190 		[97 ... 126] = 0,
1191 	};
1192 
1193 	ext[127] = get_raw_edid_checksum(ext);
1194 
1195 	*state = malloc(sizeof(struct test_state));
1196 
1197 	struct test_state ts = {.data_size = sizeof(raw) + sizeof(ext),
1198 				.data = malloc(sizeof(raw) + sizeof(ext))};
1199 
1200 	memcpy(ts.data, &raw, sizeof(raw));
1201 	memcpy(ts.data + sizeof(raw), &ext[0], sizeof(ext));
1202 
1203 	memcpy(*state, &ts, sizeof(ts));
1204 
1205 	return 0;
1206 }
1207 
test_decode_edid_it_dtv_frame_with_extension(void ** state)1208 static void test_decode_edid_it_dtv_frame_with_extension(void **state)
1209 {
1210 	struct edid out;
1211 	struct test_state *ts = *state;
1212 
1213 	/* In real-life situations frames often are not 100% conformant,
1214 	   but are at least correct when it comes to key data fields. */
1215 	assert_int_equal(EDID_CONFORMANT,
1216 			 decode_edid((unsigned char *)ts->data, ts->data_size, &out));
1217 
1218 	assert_int_equal(32, out.framebuffer_bits_per_pixel);
1219 	assert_int_equal(8, out.panel_bits_per_color);
1220 	assert_int_equal(24, out.panel_bits_per_pixel);
1221 	assert_int_equal(0, out.link_clock);
1222 	assert_int_equal(1360, out.x_resolution);
1223 	assert_int_equal(768, out.y_resolution);
1224 	assert_int_equal(5440, out.bytes_per_line);
1225 	assert_int_equal(1, out.hdmi_monitor_detected);
1226 	assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string)));
1227 	assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME);
1228 
1229 	/* Mode */
1230 	assert_null(out.mode.name);
1231 	assert_int_equal(85500, out.mode.pixel_clock);
1232 	assert_int_equal(0, out.mode.lvds_dual_channel);
1233 	assert_int_equal(0, out.mode.refresh);
1234 	assert_int_equal(1360, out.mode.ha);
1235 	assert_int_equal(432, out.mode.hbl);
1236 	assert_int_equal(64, out.mode.hso);
1237 	assert_int_equal(112, out.mode.hspw);
1238 	assert_int_equal(0, out.mode.hborder);
1239 	assert_int_equal(768, out.mode.va);
1240 	assert_int_equal(27, out.mode.vbl);
1241 	assert_int_equal(3, out.mode.vso);
1242 	assert_int_equal(0, out.mode.vborder);
1243 	assert_int_equal(43, out.mode.phsync);
1244 	assert_int_equal(43, out.mode.pvsync);
1245 	assert_int_equal(0, out.mode.x_mm);
1246 	assert_int_equal(0, out.mode.y_mm);
1247 
1248 	assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]);
1249 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]);
1250 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]);
1251 	assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]);
1252 }
1253 
teardown_edid_test(void ** state)1254 static int teardown_edid_test(void **state)
1255 {
1256 	struct test_state *ts;
1257 
1258 	if (*state == NULL)
1259 		return 0;
1260 
1261 	ts = (struct test_state *)*state;
1262 
1263 	free(ts->data);
1264 	free(ts);
1265 
1266 	return 0;
1267 }
1268 
test_edid_set_framebuffer_bits_per_pixel(void ** state)1269 static void test_edid_set_framebuffer_bits_per_pixel(void **state)
1270 {
1271 	struct edid out;
1272 	struct test_state *ts = *state;
1273 
1274 	decode_edid((unsigned char *)ts->data, ts->data_size, &out);
1275 
1276 	edid_set_framebuffer_bits_per_pixel(&out, 16, 2);
1277 
1278 	assert_int_equal(16, out.framebuffer_bits_per_pixel);
1279 	assert_int_equal(out.mode.ha * 2, out.bytes_per_line);
1280 	assert_int_equal(out.bytes_per_line / (16 / 8), out.x_resolution);
1281 	assert_int_equal(out.mode.va, out.y_resolution);
1282 
1283 	edid_set_framebuffer_bits_per_pixel(&out, 24, 4);
1284 
1285 	assert_int_equal(24, out.framebuffer_bits_per_pixel);
1286 	assert_int_equal(out.mode.ha * 3, out.bytes_per_line);
1287 	assert_int_equal(out.bytes_per_line / (24 / 8), out.x_resolution);
1288 	assert_int_equal(out.mode.va, out.y_resolution);
1289 
1290 	edid_set_framebuffer_bits_per_pixel(&out, 32, 4);
1291 
1292 	assert_int_equal(32, out.framebuffer_bits_per_pixel);
1293 	assert_int_equal(out.mode.ha * 4, out.bytes_per_line);
1294 	assert_int_equal(out.bytes_per_line / (32 / 8), out.x_resolution);
1295 	assert_int_equal(out.mode.va, out.y_resolution);
1296 }
1297 
main(void)1298 int main(void)
1299 {
1300 	const struct CMUnitTest tests[] = {
1301 		cmocka_unit_test(test_decode_edid_no_edid),
1302 		cmocka_unit_test(test_decode_edid_invalid_header),
1303 		cmocka_unit_test_setup_teardown(test_decode_edid_basic_frame,
1304 						setup_decode_edid_basic_frame,
1305 						teardown_edid_test),
1306 		cmocka_unit_test_setup_teardown(test_decode_edid_dtv_frame_with_extension,
1307 						setup_decode_edid_dtv_frame_with_extension,
1308 						teardown_edid_test),
1309 		cmocka_unit_test_setup_teardown(test_decode_edid_it_dtv_frame_with_extension,
1310 						setup_decode_edid_it_dtv_frame_with_extension,
1311 						teardown_edid_test),
1312 		cmocka_unit_test_setup_teardown(test_edid_set_framebuffer_bits_per_pixel,
1313 						setup_decode_edid_basic_frame,
1314 						teardown_edid_test),
1315 	};
1316 
1317 	return cb_run_group_tests(tests, NULL, NULL);
1318 }
1319 
1320