1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6 #include <stdint.h>
7 #include <stdbool.h>
8 #include <inttypes.h>
9 #include <assert.h>
10 #include "pcr.h"
11
12 const uint8_t *sbbar = NULL;
13
read_pcr32(const uint8_t port,const uint16_t offset)14 uint32_t read_pcr32(const uint8_t port, const uint16_t offset)
15 {
16 assert(sbbar);
17 return *(const uint32_t *)(sbbar + (port << 16) + offset);
18 }
19
print_pcr_port(const uint8_t port)20 static void print_pcr_port(const uint8_t port)
21 {
22 size_t i = 0;
23 uint32_t last_reg = 0;
24 bool last_printed = true;
25
26 printf("PCR port offset: 0x%06zx\n\n", (size_t)port << 16);
27
28 for (i = 0; i < PCR_PORT_SIZE; i += 4) {
29 const uint32_t reg = read_pcr32(port, i);
30 const bool rep = i && last_reg == reg;
31 if (!rep) {
32 if (!last_printed)
33 printf("*\n");
34 printf("0x%04zx: 0x%08"PRIx32"\n", i, reg);
35 }
36
37 last_reg = reg;
38 last_printed = !rep;
39 }
40 if (!last_printed)
41 printf("*\n");
42 }
43
print_pcr_ports(struct pci_dev * const sb,const uint8_t * const ports,const size_t count)44 void print_pcr_ports(struct pci_dev *const sb,
45 const uint8_t *const ports, const size_t count)
46 {
47 size_t i;
48
49 pcr_init(sb);
50
51 for (i = 0; i < count; ++i) {
52 printf("\n========== PCR 0x%02x ==========\n\n", ports[i]);
53 print_pcr_port(ports[i]);
54 }
55 }
56
pcr_init(struct pci_dev * const sb)57 void pcr_init(struct pci_dev *const sb)
58 {
59 bool error_exit = false;
60 bool p2sb_revealed = false;
61 struct pci_dev *p2sb;
62 bool use_p2sb = true;
63 pciaddr_t sbbar_phys;
64
65 if (sbbar)
66 return;
67
68 switch (sb->device_id) {
69 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE:
70 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
71 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
72 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
73 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
74 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
75 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
76 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
77 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
78 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
79 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
80 case PCI_DEVICE_ID_INTEL_H110:
81 case PCI_DEVICE_ID_INTEL_H170:
82 case PCI_DEVICE_ID_INTEL_Z170:
83 case PCI_DEVICE_ID_INTEL_Q170:
84 case PCI_DEVICE_ID_INTEL_Q150:
85 case PCI_DEVICE_ID_INTEL_B150:
86 case PCI_DEVICE_ID_INTEL_C236:
87 case PCI_DEVICE_ID_INTEL_C232:
88 case PCI_DEVICE_ID_INTEL_QM170:
89 case PCI_DEVICE_ID_INTEL_HM170:
90 case PCI_DEVICE_ID_INTEL_CM236:
91 case PCI_DEVICE_ID_INTEL_HM175:
92 case PCI_DEVICE_ID_INTEL_QM175:
93 case PCI_DEVICE_ID_INTEL_CM238:
94 case PCI_DEVICE_ID_INTEL_H270:
95 case PCI_DEVICE_ID_INTEL_Z270:
96 case PCI_DEVICE_ID_INTEL_Q270:
97 case PCI_DEVICE_ID_INTEL_Q250:
98 case PCI_DEVICE_ID_INTEL_B250:
99 case PCI_DEVICE_ID_INTEL_Z370:
100 case PCI_DEVICE_ID_INTEL_H310C:
101 case PCI_DEVICE_ID_INTEL_X299:
102 case PCI_DEVICE_ID_INTEL_C621:
103 case PCI_DEVICE_ID_INTEL_C621A:
104 case PCI_DEVICE_ID_INTEL_C622:
105 case PCI_DEVICE_ID_INTEL_C624:
106 case PCI_DEVICE_ID_INTEL_C625:
107 case PCI_DEVICE_ID_INTEL_C626:
108 case PCI_DEVICE_ID_INTEL_C627:
109 case PCI_DEVICE_ID_INTEL_C628:
110 case PCI_DEVICE_ID_INTEL_C629:
111 case PCI_DEVICE_ID_INTEL_C624_SUPER:
112 case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
113 case PCI_DEVICE_ID_INTEL_C621_SUPER:
114 case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
115 case PCI_DEVICE_ID_INTEL_C628_SUPER:
116 case PCI_DEVICE_ID_INTEL_DNV_LPC:
117 p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);
118 break;
119 case PCI_DEVICE_ID_INTEL_APL_LPC:
120 case PCI_DEVICE_ID_INTEL_GLK_LPC:
121 p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
122 break;
123 case PCI_DEVICE_ID_INTEL_H310:
124 case PCI_DEVICE_ID_INTEL_H370:
125 case PCI_DEVICE_ID_INTEL_Z390:
126 case PCI_DEVICE_ID_INTEL_Q370:
127 case PCI_DEVICE_ID_INTEL_B360:
128 case PCI_DEVICE_ID_INTEL_C246:
129 case PCI_DEVICE_ID_INTEL_C242:
130 case PCI_DEVICE_ID_INTEL_QM370:
131 case PCI_DEVICE_ID_INTEL_HM370:
132 case PCI_DEVICE_ID_INTEL_CM246:
133 case PCI_DEVICE_ID_INTEL_Q570:
134 case PCI_DEVICE_ID_INTEL_Z590:
135 case PCI_DEVICE_ID_INTEL_H570:
136 case PCI_DEVICE_ID_INTEL_B560:
137 case PCI_DEVICE_ID_INTEL_H510:
138 case PCI_DEVICE_ID_INTEL_WM590:
139 case PCI_DEVICE_ID_INTEL_QM580:
140 case PCI_DEVICE_ID_INTEL_HM570:
141 case PCI_DEVICE_ID_INTEL_C252:
142 case PCI_DEVICE_ID_INTEL_C256:
143 case PCI_DEVICE_ID_INTEL_W580:
144 case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
145 case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
146 case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
147 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
148 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
149 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
150 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
151 case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
152 case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
153 case PCI_DEVICE_ID_INTEL_ADL_P:
154 case PCI_DEVICE_ID_INTEL_ADL_M:
155 case PCI_DEVICE_ID_INTEL_RPL_P:
156 case PCI_DEVICE_ID_INTEL_EHL:
157 case PCI_DEVICE_ID_INTEL_JSL:
158 case PCI_DEVICE_ID_INTEL_EBG:
159 case PCI_DEVICE_ID_INTEL_ADL_N:
160 sbbar_phys = 0xfd000000;
161 use_p2sb = false;
162 break;
163 case PCI_DEVICE_ID_INTEL_H610E:
164 case PCI_DEVICE_ID_INTEL_Q670E:
165 case PCI_DEVICE_ID_INTEL_R680E:
166 case PCI_DEVICE_ID_INTEL_H610:
167 case PCI_DEVICE_ID_INTEL_B660:
168 case PCI_DEVICE_ID_INTEL_H670:
169 case PCI_DEVICE_ID_INTEL_Q670:
170 case PCI_DEVICE_ID_INTEL_Z690:
171 case PCI_DEVICE_ID_INTEL_W680:
172 case PCI_DEVICE_ID_INTEL_WM690:
173 case PCI_DEVICE_ID_INTEL_HM670:
174 case PCI_DEVICE_ID_INTEL_W790:
175 case PCI_DEVICE_ID_INTEL_Z790:
176 case PCI_DEVICE_ID_INTEL_H770:
177 case PCI_DEVICE_ID_INTEL_B760:
178 case PCI_DEVICE_ID_INTEL_HM770:
179 case PCI_DEVICE_ID_INTEL_WM790:
180 case PCI_DEVICE_ID_INTEL_C262:
181 case PCI_DEVICE_ID_INTEL_C266:
182 case PCI_DEVICE_ID_INTEL_MTL_0:
183 case PCI_DEVICE_ID_INTEL_MTL_1:
184 case PCI_DEVICE_ID_INTEL_MTL_2:
185 case PCI_DEVICE_ID_INTEL_MTL_3:
186 case PCI_DEVICE_ID_INTEL_MTL_4:
187 case PCI_DEVICE_ID_INTEL_MTL_5:
188 case PCI_DEVICE_ID_INTEL_MTL_6:
189 case PCI_DEVICE_ID_INTEL_MTL_7:
190 sbbar_phys = 0xe0000000;
191 use_p2sb = false;
192 break;
193 default:
194 perror("Unknown LPC device.");
195 exit(1);
196 }
197
198 if (use_p2sb) {
199 if (!p2sb) {
200 perror("Can't allocate device node for P2SB.");
201 exit(1);
202 }
203
204 /* do not fill bases here, libpci refuses to refill later */
205 pci_fill_info(p2sb, PCI_FILL_IDENT);
206 if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
207 printf("Trying to reveal Primary to Sideband Bridge "
208 "(P2SB),\nlet's hope the OS doesn't mind... ");
209 /* Do not use pci_write_long(). Bytes
210 surrounding 0xe0 must be maintained. */
211 pci_write_byte(p2sb, 0xe0 + 1, 0);
212
213 pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);
214 if (p2sb->vendor_id != 0xffff ||
215 p2sb->device_id != 0xffff) {
216 printf("done.\n");
217 p2sb_revealed = true;
218 } else {
219 printf("failed.\n");
220 exit(1);
221 }
222 }
223 pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
224
225 sbbar_phys = p2sb->base_addr[0] & ~0xfULL;
226 }
227
228 printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys);
229 sbbar = map_physical(sbbar_phys, SBBAR_SIZE);
230 if (sbbar == NULL) {
231 perror("Error mapping SBREG_BAR");
232 error_exit = true;
233 }
234
235 if (use_p2sb) {
236 if (p2sb_revealed) {
237 printf("Hiding Primary to Sideband Bridge (P2SB).\n");
238 pci_write_byte(p2sb, 0xe0 + 1, 1);
239 }
240 pci_free_dev(p2sb);
241 }
242
243 if (error_exit)
244 exit(1);
245 }
246
pcr_cleanup(void)247 void pcr_cleanup(void)
248 {
249 if (sbbar)
250 unmap_physical((void *)sbbar, SBBAR_SIZE);
251 }
252