1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6 #include <inttypes.h>
7 #include <commonlib/helpers.h>
8 #include "inteltool.h"
9
10 static const io_register_t sunrise_pm_registers[] = {
11 { 0x00, 2, "PM1_STS" }, /* PM1 Status; ACPI pointer: PM1a_EVT_BLK */
12 { 0x02, 2, "PM1_EN" }, /* PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 */
13 { 0x04, 4, "PM1_CNT" }, /* PM1 Control; ACPI pointer: PM1a_CNT_BLK */
14 { 0x08, 4, "PM1_TMR" }, /* PM1 Timer; ACPI pointer: PMTMR_BLK */
15 { 0x30, 4, "SMI_EN" },
16 { 0x34, 4, "SMI_STS" },
17 { 0x40, 4, "GPE_CNTL" },
18 { 0x44, 2, "DEVACT_STS" }, /* Device Activity Status */
19 { 0x50, 4, "PM2_CNT" }, /* PM2 Control; ACPI pointer: PM2a_CNT_BLK */
20 { 0x54, 4, "OC_WDT_CTL" }, /* Overclocking WDT Control */
21 { 0x80, 4, "GPE0_STS_31_0" },
22 { 0x84, 4, "GPE0_STS_63_31" },
23 { 0x88, 4, "GPE0_STS_95_64" },
24 { 0x8c, 4, "GPE0_STS_127_96" },
25 { 0x90, 4, "GPE0_EN_31_0" },
26 { 0x94, 4, "GPE0_EN_63_31" },
27 { 0x98, 4, "GPE0_EN_95_64" },
28 { 0x9c, 4, "GPE0_EN_127_96" },
29 };
30
31 static const io_register_t lynxpoint_lp_pm_registers[] = {
32 { 0x00, 2, "PM1_STS" }, /* PM1 Status; ACPI pointer: PM1a_EVT_BLK */
33 { 0x02, 2, "PM1_EN" }, /* PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 */
34 { 0x04, 4, "PM1_CNT" }, /* PM1 Control; ACPI pointer: PM1a_CNT_BLK */
35 { 0x08, 4, "PM1_TMR" }, /* PM1 Timer; ACPI pointer: PMTMR_BLK */
36 { 0x30, 4, "SMI_EN" },
37 { 0x34, 4, "SMI_STS" },
38 { 0x42, 1, "GPE_CNTL" },
39 { 0x44, 2, "DEVACT_STS" }, /* Device Activity Status */
40 { 0x50, 1, "PM2_CNT" }, /* PM2 Control; ACPI pointer: PM2a_CNT_BLK */
41 /* The TCO registers start here. */
42 { 0x60, 2, "TCO_RLD" },
43 { 0x62, 1, "TCO_DAT_IN" },
44 { 0x63, 1, "TCO_DAT_OUT" },
45 { 0x64, 2, "TCO1_STS" },
46 { 0x66, 2, "TCO2_STS" },
47 { 0x68, 2, "TCO1_CNT" },
48 { 0x6a, 2, "TCO2_CNT" },
49 { 0x6c, 2, "TCO_MESSAGE" },
50 { 0x6e, 1, "TCO_WDCNT" },
51 { 0x6f, 1, "RESERVED" },
52 { 0x70, 1, "SW_IRQ_GEN" },
53 { 0x71, 1, "RESERVED" },
54 { 0x72, 2, "TCO_TMR" },
55 { 0x74, 4, "RESERVED" },
56 { 0x78, 4, "RESERVED" },
57 { 0x7c, 4, "RESERVED" },
58 /* The TCO registers end here. */
59 { 0x80, 4, "GPE0_STS_31_0" },
60 { 0x84, 4, "GPE0_STS_63_32" },
61 { 0x88, 4, "GPE0_STS_94_64" },
62 { 0x8c, 4, "GPE0_STS_127_96" },
63 { 0x90, 4, "GPE0_EN_31_0" },
64 { 0x94, 4, "GPE0_EN_63_32" },
65 { 0x98, 4, "GPE0_EN_94_64" },
66 { 0x9c, 4, "GPE0_EN_127_96" },
67 };
68
69 static const io_register_t pch_pm_registers[] = {
70 { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
71 { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
72 { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
73 { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
74 { 0x0c, 4, "RESERVED" },
75 { 0x10, 4, "RESERVED" },
76 { 0x14, 4, "RESERVED" },
77 { 0x18, 4, "RESERVED" },
78 { 0x1c, 4, "RESERVED" },
79 { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
80 { 0x28, 8, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
81 { 0x30, 4, "SMI_EN" },
82 { 0x34, 4, "SMI_STS" },
83 { 0x38, 2, "ALT_GP_SMI_EN" },
84 { 0x3a, 2, "ALT_GP_SMI_STS" },
85 { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control
86 { 0x3d, 1, "RESERVED" },
87 { 0x3e, 2, "RESERVED" },
88 { 0x40, 2, "RESERVED" },
89 { 0x42, 1, "GPE_CNTL" },
90 { 0x43, 1, "RESERVED" },
91 { 0x44, 2, "DEVACT_STS" }, // Device Activity Status
92 { 0x46, 2, "RESERVED" },
93 { 0x48, 4, "RESERVED" },
94 { 0x4c, 4, "RESERVED" },
95 { 0x50, 1, "PM2_CNT" },
96 { 0x51, 1, "RESERVED" },
97 { 0x52, 2, "RESERVED" },
98 { 0x54, 4, "RESERVED" },
99 { 0x58, 4, "RESERVED" },
100 { 0x5c, 4, "RESERVED" },
101 /* The TCO registers start here. */
102 { 0x60, 2, "TCO_RLD" },
103 { 0x62, 1, "TCO_DAT_IN" },
104 { 0x63, 1, "TCO_DAT_OUT" },
105 { 0x64, 2, "TCO1_STS" },
106 { 0x66, 2, "TCO2_STS" },
107 { 0x68, 2, "TCO1_CNT" },
108 { 0x6a, 2, "TCO2_CNT" },
109 { 0x6c, 2, "TCO_MESSAGE" },
110 { 0x6e, 1, "TCO_WDCNT" },
111 { 0x6f, 1, "RESERVED" },
112 { 0x70, 1, "SW_IRQ_GEN" },
113 { 0x71, 1, "RESERVED" },
114 { 0x72, 2, "TCO_TMR" },
115 { 0x74, 4, "RESERVED" },
116 { 0x78, 4, "RESERVED" },
117 { 0x7c, 4, "RESERVED" },
118 };
119
120 static const io_register_t ich10_pm_registers[] = {
121 { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
122 { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
123 { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
124 { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
125 { 0x0c, 4, "RESERVED" },
126 { 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK
127 #if DANGEROUS_REGISTERS
128 /* These registers return 0 on read, but reading them may cause
129 * the system to enter Cx states, which might hang the system.
130 */
131 { 0x14, 1, "LV2 (Mobile)" },
132 { 0x15, 1, "LV3 (Mobile)" },
133 { 0x16, 1, "LV4 (Mobile)" },
134 #endif
135 { 0x17, 2, "RESERVED" },
136 { 0x19, 1, "RESERVED" },
137 { 0x1a, 2, "RESERVED" },
138 { 0x1c, 4, "RESERVED" },
139 { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
140 { 0x28, 8, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
141 { 0x30, 4, "SMI_EN" },
142 { 0x34, 4, "SMI_STS" },
143 { 0x38, 2, "ALT_GP_SMI_EN" },
144 { 0x3a, 2, "ALT_GP_SMI_STS" },
145 { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control;
146 { 0x3d, 2, "RESERVED" },
147 { 0x3f, 1, "RESERVED" },
148 { 0x40, 2, "RESERVED" },
149 { 0x42, 1, "GPE_CNTL" },
150 { 0x43, 1, "RESERVED" },
151 { 0x44, 2, "DEVACT_STS" }, // Device Activity Status
152 { 0x46, 2, "RESERVED" },
153 { 0x48, 4, "RESERVED" },
154 { 0x4c, 4, "RESERVED" },
155 { 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK
156 { 0x51, 1, "RESERVED" },
157 { 0x52, 2, "RESERVED" },
158 { 0x54, 4, "C3_RES (Mobile)" },
159 { 0x58, 4, "RESERVED" },
160 { 0x5c, 4, "RESERVED" },
161 /* Here start the TCO registers */
162 { 0x60, 2, "TCO_RLD" },
163 { 0x62, 1, "TCO_DAT_IN" },
164 { 0x63, 1, "TCO_DAT_OUT" },
165 { 0x64, 2, "TCO1_STS" },
166 { 0x66, 2, "TCO2_STS" },
167 { 0x68, 2, "TCO1_CNT" },
168 { 0x6a, 2, "TCO2_CNT" },
169 { 0x6c, 2, "TCO_MESSAGE" },
170 { 0x6e, 1, "TCO_WDCNT" },
171 { 0x6f, 1, "RESERVED" },
172 { 0x70, 1, "SW_IRQ_GEN" },
173 { 0x71, 1, "RESERVED" },
174 { 0x72, 2, "TCO_TMR" },
175 { 0x74, 4, "RESERVED" },
176 { 0x78, 4, "RESERVED" },
177 { 0x7c, 4, "RESERVED" },
178 };
179
180 static const io_register_t ich9_pm_registers[] = {
181 { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
182 { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
183 { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
184 { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
185 { 0x0c, 4, "RESERVED" },
186 { 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK
187 #if DANGEROUS_REGISTERS
188 /* These registers return 0 on read, but reading them may cause
189 * the system to enter Cx states, which might hang the system.
190 */
191 { 0x14, 1, "LV2 (Mobile)" },
192 { 0x15, 1, "LV3 (Mobile)" },
193 { 0x16, 1, "LV4 (Mobile)" },
194 { 0x17, 1, "LV5 (Mobile)" },
195 { 0x18, 1, "LV6 (Mobile)" },
196 #endif
197 { 0x19, 1, "RESERVED" },
198 { 0x1a, 2, "RESERVED" },
199 { 0x1c, 4, "RESERVED" },
200 { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
201 { 0x28, 8, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
202 { 0x30, 4, "SMI_EN" },
203 { 0x34, 4, "SMI_STS" },
204 { 0x38, 2, "ALT_GP_SMI_EN" },
205 { 0x3a, 2, "ALT_GP_SMI_STS" },
206 { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control;
207 { 0x3d, 2, "RESERVED" },
208 { 0x3f, 1, "RESERVED" },
209 { 0x40, 2, "RESERVED" },
210 { 0x42, 1, "GPE_CNTL" },
211 { 0x43, 1, "RESERVED" },
212 { 0x44, 2, "DEVACT_STS" }, // Device Activity Status
213 { 0x46, 2, "RESERVED" },
214 { 0x48, 4, "RESERVED" },
215 { 0x4c, 4, "RESERVED" },
216 { 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK
217 { 0x51, 1, "RESERVED" },
218 { 0x52, 2, "RESERVED" },
219 { 0x54, 4, "C3_RES (Mobile)" },
220 { 0x58, 4, "C5_RES (Mobile)" },
221 { 0x5c, 4, "RESERVED" },
222 /* Here start the TCO registers */
223 { 0x60, 2, "TCO_RLD" },
224 { 0x62, 1, "TCO_DAT_IN" },
225 { 0x63, 1, "TCO_DAT_OUT" },
226 { 0x64, 2, "TCO1_STS" },
227 { 0x66, 2, "TCO2_STS" },
228 { 0x68, 2, "TCO1_CNT" },
229 { 0x6a, 2, "TCO2_CNT" },
230 { 0x6c, 2, "TCO_MESSAGE" },
231 { 0x6e, 1, "TCO_WDCNT" },
232 { 0x6f, 1, "RESERVED" },
233 { 0x70, 1, "SW_IRQ_GEN" },
234 { 0x71, 1, "RESERVED" },
235 { 0x72, 2, "TCO_TMR" },
236 { 0x74, 4, "RESERVED" },
237 { 0x78, 4, "RESERVED" },
238 { 0x7c, 4, "RESERVED" },
239 };
240
241 static const io_register_t ich8_pm_registers[] = {
242 { 0x00, 2, "PM1_STS" },
243 { 0x02, 2, "PM1_EN" },
244 { 0x04, 4, "PM1_CNT" },
245 { 0x08, 4, "PM1_TMR" },
246 { 0x0c, 4, "RESERVED" },
247 { 0x10, 4, "PROC_CNT" },
248 #if DANGEROUS_REGISTERS
249 /* These registers return 0 on read, but reading them may cause
250 * the system to enter Cx states, which might hang the system.
251 */
252 { 0x14, 1, "LV2 (Mobile)" },
253 { 0x15, 1, "LV3 (Mobile)" },
254 { 0x16, 1, "LV4 (Mobile)" },
255 { 0x17, 1, "LV5 (Mobile)" },
256 { 0x18, 1, "LV6 (Mobile)" },
257 #endif
258 { 0x19, 1, "RESERVED" },
259 { 0x1a, 2, "RESERVED" },
260 { 0x1c, 4, "RESERVED" },
261 { 0x20, 1, "PM2_CNT (Mobile)" },
262 { 0x21, 1, "RESERVED" },
263 { 0x22, 2, "RESERVED" },
264 { 0x24, 4, "RESERVED" },
265 { 0x28, 4, "GPE0_STS" },
266 { 0x2C, 4, "GPE0_EN" },
267 { 0x30, 4, "SMI_EN" },
268 { 0x34, 4, "SMI_STS" },
269 { 0x38, 2, "ALT_GP_SMI_EN" },
270 { 0x3a, 2, "ALT_GP_SMI_STS" },
271 { 0x3c, 4, "RESERVED" },
272 { 0x40, 2, "RESERVED" },
273 { 0x42, 1, "GPE_CNTL" },
274 { 0x43, 1, "RESERVED" },
275 { 0x44, 2, "DEVACT_STS" },
276 { 0x46, 2, "RESERVED" },
277 { 0x48, 4, "RESERVED" },
278 { 0x4c, 4, "RESERVED" },
279 { 0x50, 1, "SS_CNT (Mobile)" },
280 { 0x51, 1, "RESERVED" },
281 { 0x52, 2, "RESERVED" },
282 { 0x54, 4, "C3_RES (Mobile)" },
283 { 0x58, 4, "C5_RES (Mobile)" },
284 { 0x5c, 4, "RESERVED" },
285 /* Here start the TCO registers */
286 { 0x60, 2, "TCO_RLD" },
287 { 0x62, 1, "TCO_DAT_IN" },
288 { 0x63, 1, "TCO_DAT_OUT" },
289 { 0x64, 2, "TCO1_STS" },
290 { 0x66, 2, "TCO2_STS" },
291 { 0x68, 2, "TCO1_CNT" },
292 { 0x6a, 2, "TCO2_CNT" },
293 { 0x6c, 2, "TCO_MESSAGE" },
294 { 0x6e, 1, "TCO_WDCNT" },
295 { 0x6f, 1, "RESERVED" },
296 { 0x70, 1, "SW_IRQ_GEN" },
297 { 0x71, 1, "RESERVED" },
298 { 0x72, 2, "TCO_TMR" },
299 { 0x74, 4, "RESERVED" },
300 { 0x78, 4, "RESERVED" },
301 { 0x7c, 4, "RESERVED" },
302 };
303
304 static const io_register_t ich7_pm_registers[] = {
305 { 0x00, 2, "PM1_STS" },
306 { 0x02, 2, "PM1_EN" },
307 { 0x04, 4, "PM1_CNT" },
308 { 0x08, 4, "PM1_TMR" },
309 { 0x0c, 4, "RESERVED" },
310 { 0x10, 4, "PROC_CNT" },
311 #if DANGEROUS_REGISTERS
312 /* These registers return 0 on read, but reading them may cause
313 * the system to enter C2/C3/C4 state, which might hang the system.
314 */
315 { 0x14, 1, "LV2 (Mobile/Ultra Mobile)" },
316 { 0x15, 1, "LV3 (Mobile/Ultra Mobile)" },
317 { 0x16, 1, "LV4 (Mobile/Ultra Mobile)" },
318 #endif
319 { 0x17, 1, "RESERVED" },
320 { 0x18, 4, "RESERVED" },
321 { 0x1c, 4, "RESERVED" },
322 { 0x20, 1, "PM2_CNT (Mobile/Ultra Mobile)" },
323 { 0x21, 1, "RESERVED" },
324 { 0x22, 2, "RESERVED" },
325 { 0x24, 4, "RESERVED" },
326 { 0x28, 4, "GPE0_STS" },
327 { 0x2C, 4, "GPE0_EN" },
328 { 0x30, 4, "SMI_EN" },
329 { 0x34, 4, "SMI_STS" },
330 { 0x38, 2, "ALT_GP_SMI_EN" },
331 { 0x3a, 2, "ALT_GP_SMI_STS" },
332 { 0x3c, 4, "RESERVED" },
333 { 0x40, 2, "RESERVED" },
334 { 0x42, 1, "GPE_CNTL" },
335 { 0x43, 1, "RESERVED" },
336 { 0x44, 2, "DEVACT_STS" },
337 { 0x46, 2, "RESERVED" },
338 { 0x48, 4, "RESERVED" },
339 { 0x4c, 4, "RESERVED" },
340 { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
341 { 0x51, 1, "RESERVED" },
342 { 0x52, 2, "RESERVED" },
343 { 0x54, 4, "C3_RES (Mobile/Ultra Mobile)" },
344 { 0x58, 4, "RESERVED" },
345 { 0x5c, 4, "RESERVED" },
346 /* Here start the TCO registers */
347 { 0x60, 2, "TCO_RLD" },
348 { 0x62, 1, "TCO_DAT_IN" },
349 { 0x63, 1, "TCO_DAT_OUT" },
350 { 0x64, 2, "TCO1_STS" },
351 { 0x66, 2, "TCO2_STS" },
352 { 0x68, 2, "TCO1_CNT" },
353 { 0x6a, 2, "TCO2_CNT" },
354 { 0x6c, 2, "TCO_MESSAGE" },
355 { 0x6e, 1, "TCO_WDCNT" },
356 { 0x6f, 1, "RESERVED" },
357 { 0x70, 1, "SW_IRQ_GEN" },
358 { 0x71, 1, "RESERVED" },
359 { 0x72, 2, "TCO_TMR" },
360 { 0x74, 4, "RESERVED" },
361 { 0x78, 4, "RESERVED" },
362 { 0x7c, 4, "RESERVED" },
363 };
364
365 /*
366 * INTEL I/O Controller Hub 6 Family
367 * http://www.intel.com/assets/pdf/datasheet/301473.pdf
368 */
369 static const io_register_t ich6_pm_registers[] = {
370 /* 10.8.3 */
371 { 0x00, 2, "PM1_STS" },
372 { 0x02, 2, "PM1_EN" },
373 { 0x04, 4, "PM1_CNT" },
374 { 0x08, 4, "PM1_TMR" },
375 { 0x10, 4, "PROC_CNT" },
376 #if DANGEROUS_REGISTERS
377 /* These registers return 0 on read, but reading them may cause
378 * the system to enter C2/C3/C4 state, which might hang the system.
379 */
380 { 0x14, 1, "LV2" },
381 { 0x15, 1, "LV3 (Mobile Only)" },
382 { 0x16, 1, "LV4 (Mobile Only)" },
383 #endif
384 { 0x20, 1, "PM2_CNT (Mobile Only)" },
385 { 0x28, 4, "GPE0_STS" },
386 { 0x2c, 4, "GPE0_EN" },
387 { 0x30, 4, "SMI_EN" },
388 { 0x34, 4, "SMI_STS" },
389 { 0x38, 2, "ALT_GP_SMI_EN" },
390 { 0x3a, 2, "ALT_GP_SMI_STS" },
391 { 0x44, 2, "DEVACT_STS" },
392 { 0x50, 1, "SS_CNT (Mobile Only)" },
393 { 0x54, 4, "C3_RES (Mobile Only)" },
394 };
395
396 static const io_register_t ich5_pm_registers[] = {
397 { 0x00, 2, "PM1_STS" },
398 { 0x02, 2, "PM1_EN" },
399 { 0x04, 4, "PM1_CNT" },
400 { 0x08, 4, "PM1_TMR" },
401 { 0x0c, 4, "RESERVED" },
402 { 0x10, 4, "PROC_CNT" },
403 { 0x14, 3, "RESERVED" },
404 { 0x17, 9, "RESERVED" },
405 { 0x20, 1, "RESERVED" },
406 { 0x28, 4, "GPE0_STS" },
407 { 0x2c, 4, "GPE0_EN" },
408 { 0x30, 4, "SMI_EN" },
409 { 0x34, 4, "SMI_STS" },
410 { 0x38, 2, "ALT_GP_SMI_EN" },
411 { 0x3a, 2, "ALT_GP_SMI_STS" },
412 { 0x3c, 4, "RESERVED" },
413 { 0x40, 1, "MON_SMI" },
414 { 0x42, 2, "RESERVED" },
415 { 0x44, 1, "DEVACT_STS" },
416 { 0x48, 1, "DEVTRAP_EN" },
417 { 0x50, 1, "RESERVED" },
418 { 0x51, 15, "RESERVED" },
419 { 0x60, 16, "RESERVED" },
420 };
421
422 static const io_register_t ich4_pm_registers[] = {
423 { 0x00, 2, "PM1_STS" },
424 { 0x02, 2, "PM1_EN" },
425 { 0x04, 4, "PM1_CNT" },
426 { 0x08, 4, "PM1_TMR" },
427 { 0x0c, 4, "RESERVED" },
428 { 0x10, 4, "PROC_CNT" },
429 #if DANGEROUS_REGISTERS
430 /* These registers return 0 on read, but reading them may cause
431 * the system to enter C2/C3/C4 state, which might hang the system.
432 */
433 { 0x14, 1, "LV2 (Mobile)" },
434 { 0x15, 1, "LV3 (Mobile)" },
435 { 0x16, 1, "LV4 (Mobile)" },
436 #endif
437 { 0x17, 1, "RESERVED" },
438 { 0x18, 4, "RESERVED" },
439 { 0x1c, 4, "RESERVED" },
440 { 0x20, 1, "PM2_CNT (Mobile)" },
441 { 0x21, 1, "RESERVED" },
442 { 0x22, 2, "RESERVED" },
443 { 0x24, 4, "RESERVED" },
444 { 0x28, 4, "GPE0_STS" },
445 { 0x2C, 4, "GPE0_EN" },
446 { 0x30, 4, "SMI_EN" },
447 { 0x34, 4, "SMI_STS" },
448 { 0x38, 2, "ALT_GP_SMI_EN" },
449 { 0x3a, 2, "ALT_GP_SMI_STS" },
450 { 0x3c, 4, "RESERVED" },
451 { 0x40, 2, "MON_SMI" },
452 { 0x42, 2, "RESERVED" },
453 { 0x44, 2, "DEVACT_STS" },
454 { 0x46, 2, "RESERVED" },
455 { 0x48, 4, "DEVTRAP_EN" },
456 { 0x4c, 2, "BUS_ADDR_TRACK" },
457 { 0x4e, 2, "BUS_CYC_TRACK" },
458 { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
459 { 0x51, 1, "RESERVED" },
460 { 0x52, 2, "RESERVED" },
461 { 0x54, 4, "RESERVED" },
462 { 0x58, 4, "RESERVED" },
463 { 0x5c, 4, "RESERVED" },
464 /* Here start the TCO registers */
465 { 0x60, 1, "TCO_RLD" },
466 { 0x61, 1, "TCO_TMR" },
467 { 0x62, 1, "TCO_DAT_IN" },
468 { 0x63, 1, "TCO_DAT_OUT" },
469 { 0x64, 2, "TCO1_STS" },
470 { 0x66, 2, "TCO2_STS" },
471 { 0x68, 2, "TCO1_CNT" },
472 { 0x6a, 2, "TCO2_CNT" },
473 { 0x6c, 2, "TCO_MESSAGE" },
474 { 0x6e, 1, "TCO_WDSTATUS" },
475 { 0x6f, 1, "RESERVED" },
476 { 0x70, 1, "SW_IRQ_GEN" },
477 { 0x71, 1, "RESERVED" },
478 { 0x72, 2, "RESERVED" },
479 { 0x74, 4, "RESERVED" },
480 { 0x78, 4, "RESERVED" },
481 { 0x7c, 4, "RESERVED" },
482 };
483
484 static const io_register_t ich2_pm_registers[] = {
485 { 0x00, 2, "PM1_STS" },
486 { 0x02, 2, "PM1_EN" },
487 { 0x04, 4, "PM1_CNT" },
488 { 0x08, 4, "PM1_TMR" },
489 { 0x0c, 4, "RESERVED" },
490 { 0x10, 4, "PROC_CNT" },
491 #if DANGEROUS_REGISTERS
492 /* This register returns 0 on read, but reading it may cause
493 * the system to enter C2 state, which might hang the system.
494 */
495 { 0x14, 1, "LV2" },
496 { 0x15, 1, "RESERVED" },
497 { 0x16, 2, "RESERVED" },
498 #endif
499 { 0x18, 4, "RESERVED" },
500 { 0x1c, 4, "RESERVED" },
501 { 0x20, 4, "RESERVED" },
502 { 0x24, 4, "RESERVED" },
503 { 0x28, 2, "GPE0_STS" },
504 { 0x2a, 2, "GPE0_EN" },
505 { 0x2c, 2, "GPE1_STS" },
506 { 0x2e, 2, "GPE1_EN" },
507 { 0x30, 2, "SMI_EN" },
508 { 0x32, 2, "RESERVED" },
509 { 0x34, 2, "SMI_STS" },
510 { 0x36, 2, "RESERVED" },
511 { 0x38, 4, "RESERVED" },
512 { 0x3c, 4, "RESERVED" },
513 { 0x40, 2, "MON_SMI_STS" },
514 { 0x42, 2, "RESERVED" },
515 { 0x44, 2, "DEV_TRP_STS" },
516 { 0x46, 2, "RESERVED" },
517 { 0x48, 2, "TRP_EN" },
518 { 0x4A, 2, "RESERVED" },
519 { 0x4c, 2, "BUS_ADDR_TRACK" },
520 { 0x4e, 1, "BUS_CYC_TRACK" },
521 { 0x4f, 1, "RESERVED" },
522 { 0x50, 4, "RESERVED" },
523 { 0x54, 4, "RESERVED" },
524 { 0x58, 4, "RESERVED" },
525 { 0x5c, 4, "RESERVED" },
526 /* Here start the TCO registers */
527 { 0x60, 1, "TCO_RLD" },
528 { 0x61, 1, "TCO_TMR" },
529 { 0x62, 1, "TCO_DAT_IN" },
530 { 0x63, 1, "TCO_DAT_OUT" },
531 { 0x64, 2, "TCO1_STS" },
532 { 0x66, 2, "TCO2_STS" },
533 { 0x68, 2, "TCO1_CNT" },
534 { 0x6a, 2, "TCO2_CNT" },
535 { 0x6c, 1, "TCO_MESSAGE1" },
536 { 0x6d, 1, "TCO_MESSAGE2" },
537 { 0x6e, 1, "TCO_WDSTATUS" },
538 { 0x6f, 1, "RESERVED" },
539 { 0x70, 1, "SW_IRQ_GEN" },
540 { 0x71, 1, "RESERVED" },
541 { 0x72, 2, "RESERVED" },
542 { 0x74, 4, "RESERVED" },
543 { 0x78, 4, "RESERVED" },
544 { 0x7c, 4, "RESERVED" },
545 };
546
547 static const io_register_t ich0_pm_registers[] = {
548 { 0x00, 2, "PM1_STS" },
549 { 0x02, 2, "PM1_EN" },
550 { 0x04, 4, "PM1_CNT" },
551 { 0x08, 4, "PM1_TMR" },
552 { 0x0c, 4, "RESERVED" },
553 { 0x10, 4, "PROC_CNT" },
554 #if DANGEROUS_REGISTERS
555 /* This register returns 0 on read, but reading it may cause
556 * the system to enter C2 state, which might hang the system.
557 */
558 { 0x14, 1, "LV2" },
559 { 0x15, 1, "RESERVED" },
560 { 0x16, 2, "RESERVED" },
561 #endif
562 { 0x18, 4, "RESERVED" },
563 { 0x1c, 4, "RESERVED" },
564 { 0x20, 4, "RESERVED" },
565 { 0x24, 4, "RESERVED" },
566 { 0x28, 4, "GPE0_STS" },
567 { 0x2C, 4, "GPE0_EN" },
568 { 0x30, 2, "SMI_EN" },
569 { 0x32, 2, "RESERVED" },
570 { 0x34, 2, "SMI_STS" },
571 { 0x36, 2, "RESERVED" },
572 { 0x38, 4, "RESERVED" },
573 { 0x3c, 4, "RESERVED" },
574 { 0x40, 2, "IOMON_STS_EN" },
575 { 0x42, 2, "RESERVED" },
576 { 0x44, 2, "DEVACT_STS" },
577 { 0x46, 2, "RESERVED" },
578 { 0x48, 4, "RESERVED" },
579 { 0x4c, 2, "BUS_ADDR_TRACK" },
580 { 0x4e, 1, "BUS_CYC_TRACK" },
581 { 0x4f, 1, "RESERVED" },
582 { 0x50, 4, "RESERVED" },
583 { 0x54, 4, "RESERVED" },
584 { 0x58, 4, "RESERVED" },
585 { 0x5c, 4, "RESERVED" },
586 /* Here start the TCO registers */
587 { 0x60, 1, "TCO_RLD" },
588 { 0x61, 1, "TCO_TMR" },
589 { 0x62, 1, "TCO_DAT_IN" },
590 { 0x63, 1, "TCO_DAT_OUT" },
591 { 0x64, 2, "TCO1_STS" },
592 { 0x66, 2, "TCO2_STS" },
593 { 0x68, 2, "TCO1_CNT" },
594 { 0x6a, 2, "TCO2_CNT" },
595 { 0x6c, 1, "TCO_MESSAGE1" },
596 { 0x6d, 1, "TCO_MESSAGE2" },
597 { 0x6e, 1, "TCO_WDSTATUS" },
598 { 0x6f, 1, "RESERVED" },
599 { 0x70, 4, "RESERVED" },
600 { 0x74, 4, "RESERVED" },
601 { 0x78, 4, "RESERVED" },
602 { 0x7c, 4, "RESERVED" },
603 };
604
605 static const io_register_t i82371xx_pm_registers[] = {
606 { 0x00, 2, "PMSTS" },
607 { 0x02, 2, "PMEN" },
608 { 0x04, 2, "PMCNTRL" },
609 { 0x06, 2, "RESERVED" },
610 { 0x08, 1, "PMTMR" },
611 { 0x09, 1, "RESERVED" },
612 { 0x0A, 1, "RESERVED" },
613 { 0x0B, 1, "RESERVED" },
614 { 0x0C, 2, "GPSTS" },
615 { 0x0E, 2, "GPEN" },
616 { 0x10, 4, "PCNTRL" },
617 #if DANGEROUS_REGISTERS
618 /*
619 * This register returns 0 on read, but reading it may cause
620 * the system to enter C2 state, which might hang the system.
621 */
622 { 0x14, 1, "PLVL2" },
623 { 0x15, 1, "PLVL3" },
624 { 0x16, 2, "RESERVED" },
625 #endif
626 { 0x18, 2, "GLBSTS" },
627 { 0x1A, 2, "RESERVED" },
628 { 0x1c, 4, "DEVSTS" },
629 { 0x20, 2, "GLBEN" },
630 { 0x22, 1, "RESERVED" },
631 { 0x23, 1, "RESERVED" },
632 { 0x24, 1, "RESERVED" },
633 { 0x25, 1, "RESERVED" },
634 { 0x26, 1, "RESERVED" },
635 { 0x27, 1, "RESERVED" },
636 { 0x28, 4, "GLBCTL" },
637 { 0x2C, 4, "DEVCTL" },
638 /* The registers 0x30-0x33 and 0x34-0x37 allow byte-wise reads only. */
639 { 0x30, 1, "GPIREG 0" },
640 { 0x31, 1, "GPIREG 1" },
641 { 0x32, 1, "GPIREG 2" },
642 { 0x33, 1, "GPIREG 3" },
643 { 0x34, 1, "GPOREG 0" },
644 { 0x35, 1, "GPOREG 1" },
645 { 0x36, 1, "GPOREG 2" },
646 { 0x37, 1, "GPOREG 3" },
647 };
648
649 static const io_register_t i63xx_pm_registers[] = {
650 { 0x00, 2, "PM1_STS" },
651 { 0x02, 2, "PM1_EN" },
652 { 0x04, 4, "PM1_CNT" },
653 { 0x08, 4, "PM1_TMR" },
654 { 0x0c, 4, "RESERVED" },
655 { 0x10, 4, "PROC_CNT" },
656 #if DANGEROUS_REGISTERS
657 /* This register returns 0 on read, but reading it may cause
658 * the system to enter C2 state, which might hang the system.
659 */
660 { 0x14, 1, "LV2" },
661 { 0x15, 1, "RESERVED" },
662 { 0x16, 2, "RESERVED" },
663 #endif
664 { 0x18, 4, "RESERVED" },
665 { 0x1c, 4, "RESERVED" },
666 { 0x20, 4, "RESERVED" },
667 { 0x24, 4, "RESERVED" },
668 { 0x28, 4, "GPE0_STS" },
669 { 0x2C, 4, "GPE0_EN" },
670 { 0x30, 4, "SMI_EN" },
671 { 0x34, 4, "SMI_STS" },
672 { 0x38, 2, "ALT_GP_SMI_EN" },
673 { 0x3a, 2, "ALT_GP_SMI_STS" },
674 { 0x3c, 4, "RESERVED" },
675 { 0x40, 4, "RESERVED" },
676 { 0x44, 2, "DEVACT_STS" },
677 { 0x46, 2, "RESERVED" },
678 { 0x48, 4, "RESERVED" },
679 { 0x4c, 4, "RESERVED" },
680 { 0x50, 4, "RESERVED" },
681 { 0x54, 4, "C3_RES" },
682 { 0x58, 4, "RESERVED" },
683 { 0x5c, 4, "RESERVED" },
684 { 0x60, 1, "RESERVED" },
685 { 0x64, 4, "RESERVED" },
686 { 0x68, 4, "RESERVED" },
687 { 0x6c, 4, "RESERVED" },
688 { 0x70, 4, "RESERVED" },
689 { 0x74, 4, "RESERVED" },
690 { 0x78, 4, "RESERVED" },
691 { 0x7c, 4, "RESERVED" },
692 };
693
print_pmbase(struct pci_dev * sb,struct pci_access * pacc)694 int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
695 {
696 size_t i, pm_registers_size = 0;
697 size_t pm_cfg_registers_size = 0;
698 uint16_t pmbase;
699 const io_register_t *pm_registers;
700 const io_register_t *pm_cfg_registers;
701 uint64_t pwrmbase_phys = 0;
702 struct pci_dev *acpi = NULL;
703
704 printf("\n========== ACPI/PMC =========\n\n");
705
706 switch (sb->device_id) {
707 case PCI_DEVICE_ID_INTEL_3400:
708 case PCI_DEVICE_ID_INTEL_3420:
709 case PCI_DEVICE_ID_INTEL_3450:
710 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
711 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
712 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
713 case PCI_DEVICE_ID_INTEL_B55_A:
714 case PCI_DEVICE_ID_INTEL_B55_B:
715 case PCI_DEVICE_ID_INTEL_H55:
716 case PCI_DEVICE_ID_INTEL_H57:
717 case PCI_DEVICE_ID_INTEL_HM55:
718 case PCI_DEVICE_ID_INTEL_HM57:
719 case PCI_DEVICE_ID_INTEL_P55:
720 case PCI_DEVICE_ID_INTEL_PM55:
721 case PCI_DEVICE_ID_INTEL_Q57:
722 case PCI_DEVICE_ID_INTEL_QM57:
723 case PCI_DEVICE_ID_INTEL_QS57:
724 case PCI_DEVICE_ID_INTEL_Z68:
725 case PCI_DEVICE_ID_INTEL_P67:
726 case PCI_DEVICE_ID_INTEL_UM67:
727 case PCI_DEVICE_ID_INTEL_HM65:
728 case PCI_DEVICE_ID_INTEL_H67:
729 case PCI_DEVICE_ID_INTEL_HM67:
730 case PCI_DEVICE_ID_INTEL_Q65:
731 case PCI_DEVICE_ID_INTEL_QS67:
732 case PCI_DEVICE_ID_INTEL_Q67:
733 case PCI_DEVICE_ID_INTEL_QM67:
734 case PCI_DEVICE_ID_INTEL_B65:
735 case PCI_DEVICE_ID_INTEL_C202:
736 case PCI_DEVICE_ID_INTEL_C204:
737 case PCI_DEVICE_ID_INTEL_C206:
738 case PCI_DEVICE_ID_INTEL_H61:
739 case PCI_DEVICE_ID_INTEL_Z77:
740 case PCI_DEVICE_ID_INTEL_Z75:
741 case PCI_DEVICE_ID_INTEL_Q77:
742 case PCI_DEVICE_ID_INTEL_Q75:
743 case PCI_DEVICE_ID_INTEL_B75:
744 case PCI_DEVICE_ID_INTEL_H77:
745 case PCI_DEVICE_ID_INTEL_C216:
746 case PCI_DEVICE_ID_INTEL_QM77:
747 case PCI_DEVICE_ID_INTEL_QS77:
748 case PCI_DEVICE_ID_INTEL_HM77:
749 case PCI_DEVICE_ID_INTEL_UM77:
750 case PCI_DEVICE_ID_INTEL_HM76:
751 case PCI_DEVICE_ID_INTEL_HM75:
752 case PCI_DEVICE_ID_INTEL_HM70:
753 case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
754 case PCI_DEVICE_ID_INTEL_C8_MOBILE:
755 case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
756 case PCI_DEVICE_ID_INTEL_Z87:
757 case PCI_DEVICE_ID_INTEL_Z85:
758 case PCI_DEVICE_ID_INTEL_HM86:
759 case PCI_DEVICE_ID_INTEL_H87:
760 case PCI_DEVICE_ID_INTEL_HM87:
761 case PCI_DEVICE_ID_INTEL_Q85:
762 case PCI_DEVICE_ID_INTEL_Q87:
763 case PCI_DEVICE_ID_INTEL_QM87:
764 case PCI_DEVICE_ID_INTEL_B85:
765 case PCI_DEVICE_ID_INTEL_C222:
766 case PCI_DEVICE_ID_INTEL_C224:
767 case PCI_DEVICE_ID_INTEL_C226:
768 case PCI_DEVICE_ID_INTEL_H81:
769 case PCI_DEVICE_ID_INTEL_C9_MOBILE:
770 case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
771 case PCI_DEVICE_ID_INTEL_HM97:
772 case PCI_DEVICE_ID_INTEL_Z97:
773 case PCI_DEVICE_ID_INTEL_H97:
774 pmbase = pci_read_word(sb, 0x40) & 0xff80;
775 pm_registers = pch_pm_registers;
776 pm_registers_size = ARRAY_SIZE(pch_pm_registers);
777 break;
778 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
779 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
780 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
781 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
782 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
783 pmbase = pci_read_word(sb, 0x40) & 0xff80;
784 pm_registers = lynxpoint_lp_pm_registers;
785 pm_registers_size = ARRAY_SIZE(lynxpoint_lp_pm_registers);
786 break;
787 case PCI_DEVICE_ID_INTEL_ICH10:
788 case PCI_DEVICE_ID_INTEL_ICH10D:
789 case PCI_DEVICE_ID_INTEL_ICH10DO:
790 case PCI_DEVICE_ID_INTEL_ICH10R:
791 pmbase = pci_read_word(sb, 0x40) & 0xff80;
792 pm_registers = ich10_pm_registers;
793 pm_registers_size = ARRAY_SIZE(ich10_pm_registers);
794 break;
795 case PCI_DEVICE_ID_INTEL_ICH7:
796 case PCI_DEVICE_ID_INTEL_ICH7M:
797 case PCI_DEVICE_ID_INTEL_ICH7DH:
798 case PCI_DEVICE_ID_INTEL_ICH7MDH:
799 case PCI_DEVICE_ID_INTEL_NM10:
800 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
801 pm_registers = ich7_pm_registers;
802 pm_registers_size = ARRAY_SIZE(ich7_pm_registers);
803 break;
804 case PCI_DEVICE_ID_INTEL_ICH9DH:
805 case PCI_DEVICE_ID_INTEL_ICH9DO:
806 case PCI_DEVICE_ID_INTEL_ICH9R:
807 case PCI_DEVICE_ID_INTEL_ICH9:
808 case PCI_DEVICE_ID_INTEL_ICH9M:
809 case PCI_DEVICE_ID_INTEL_ICH9ME:
810 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
811 pm_registers = ich9_pm_registers;
812 pm_registers_size = ARRAY_SIZE(ich9_pm_registers);
813 break;
814 case PCI_DEVICE_ID_INTEL_ICH8:
815 case PCI_DEVICE_ID_INTEL_ICH8M:
816 case PCI_DEVICE_ID_INTEL_ICH8ME:
817 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
818 pm_registers = ich8_pm_registers;
819 pm_registers_size = ARRAY_SIZE(ich8_pm_registers);
820 break;
821 case PCI_DEVICE_ID_INTEL_ICH6:
822 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
823 pm_registers = ich6_pm_registers;
824 pm_registers_size = ARRAY_SIZE(ich6_pm_registers);
825 break;
826 case PCI_DEVICE_ID_INTEL_ICH5:
827 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
828 pm_registers = ich5_pm_registers;
829 pm_registers_size = ARRAY_SIZE(ich5_pm_registers);
830 break;
831 case PCI_DEVICE_ID_INTEL_ICH4:
832 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
833 pm_registers = ich4_pm_registers;
834 pm_registers_size = ARRAY_SIZE(ich4_pm_registers);
835 break;
836 case PCI_DEVICE_ID_INTEL_ICH2:
837 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
838 pm_registers = ich2_pm_registers;
839 pm_registers_size = ARRAY_SIZE(ich2_pm_registers);
840 break;
841 case PCI_DEVICE_ID_INTEL_ICH0:
842 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
843 pm_registers = ich0_pm_registers;
844 pm_registers_size = ARRAY_SIZE(ich0_pm_registers);
845 break;
846 case PCI_DEVICE_ID_INTEL_82371XX:
847 acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 3);
848 if (!acpi) {
849 printf("Southbridge function 3 not found.\n");
850 return 1;
851 }
852 pmbase = pci_read_word(acpi, 0x40) & 0xfffc;
853
854 pm_registers = i82371xx_pm_registers;
855 pm_registers_size = ARRAY_SIZE(i82371xx_pm_registers);
856 break;
857 case PCI_DEVICE_ID_INTEL_I63XX:
858 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
859 pm_registers = i63xx_pm_registers;
860 pm_registers_size = ARRAY_SIZE(i63xx_pm_registers);
861 break;
862 case PCI_DEVICE_ID_INTEL_H110:
863 case PCI_DEVICE_ID_INTEL_H170:
864 case PCI_DEVICE_ID_INTEL_Z170:
865 case PCI_DEVICE_ID_INTEL_Q170:
866 case PCI_DEVICE_ID_INTEL_Q150:
867 case PCI_DEVICE_ID_INTEL_B150:
868 case PCI_DEVICE_ID_INTEL_C236:
869 case PCI_DEVICE_ID_INTEL_C232:
870 case PCI_DEVICE_ID_INTEL_QM170:
871 case PCI_DEVICE_ID_INTEL_HM170:
872 case PCI_DEVICE_ID_INTEL_CM236:
873 case PCI_DEVICE_ID_INTEL_HM175:
874 case PCI_DEVICE_ID_INTEL_QM175:
875 case PCI_DEVICE_ID_INTEL_CM238:
876 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
877 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
878 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
879 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
880 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
881 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
882 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
883 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
884 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
885 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
886 case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
887 acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 2);
888 if (!acpi) {
889 printf("PMC device not found.\n");
890 return 1;
891 }
892 pmbase = pci_read_word(acpi, 0x40) & ~0xff;
893 pwrmbase_phys = pci_read_long(acpi, 0x48) & ~0xfff;
894
895 pm_registers = sunrise_pm_registers;
896 pm_registers_size = ARRAY_SIZE(sunrise_pm_registers);
897 break;
898 default:
899 printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n");
900 return 1;
901 }
902
903 for (i = 0; i < pm_cfg_registers_size; i++) {
904 switch (pm_cfg_registers[i].size) {
905 case 8:
906 printf("0x%04x: 0x%08x (%s)\n"
907 " 0x%08x\n",
908 pm_cfg_registers[i].addr,
909 pci_read_long(acpi, pm_cfg_registers[i].addr),
910 pm_cfg_registers[i].name,
911 pci_read_long(acpi, pm_cfg_registers[i].addr+4));
912 break;
913 case 4:
914 printf("0x%04x: 0x%08x (%s)\n",
915 pm_cfg_registers[i].addr,
916 pci_read_long(acpi, pm_cfg_registers[i].addr),
917 pm_cfg_registers[i].name);
918 break;
919 case 2:
920 printf("0x%04x: 0x%04x (%s)\n",
921 pm_cfg_registers[i].addr,
922 pci_read_word(acpi, pm_cfg_registers[i].addr),
923 pm_cfg_registers[i].name);
924 break;
925 case 1:
926 printf("0x%04x: 0x%02x (%s)\n",
927 pm_cfg_registers[i].addr,
928 pci_read_byte(acpi, pm_cfg_registers[i].addr),
929 pm_cfg_registers[i].name);
930 break;
931 }
932 }
933
934 if (acpi)
935 pci_free_dev(acpi);
936
937 printf("\n========== ABASE/PMBASE =========\n\n");
938 printf("PMBASE = 0x%04x (IO)\n\n", pmbase);
939
940 for (i = 0; i < pm_registers_size; i++) {
941 switch (pm_registers[i].size) {
942 case 8:
943 printf("pmbase+0x%04x: 0x%08x (%s)\n"
944 " 0x%08x\n",
945 pm_registers[i].addr,
946 inl(pmbase+pm_registers[i].addr),
947 pm_registers[i].name,
948 inl(pmbase+pm_registers[i].addr+4));
949 break;
950 case 4:
951 printf("pmbase+0x%04x: 0x%08x (%s)\n",
952 pm_registers[i].addr,
953 inl(pmbase+pm_registers[i].addr),
954 pm_registers[i].name);
955 break;
956 case 2:
957 printf("pmbase+0x%04x: 0x%04x (%s)\n",
958 pm_registers[i].addr,
959 inw(pmbase+pm_registers[i].addr),
960 pm_registers[i].name);
961 break;
962 case 1:
963 printf("pmbase+0x%04x: 0x%02x (%s)\n",
964 pm_registers[i].addr,
965 inb(pmbase+pm_registers[i].addr),
966 pm_registers[i].name);
967 break;
968 }
969 }
970
971 if (pwrmbase_phys) {
972 const size_t pwrmbase_size = 4 * KiB;
973 volatile const u8 *const pwrmbase =
974 map_physical(pwrmbase_phys, pwrmbase_size);
975 if (!pwrmbase) {
976 perror("Error mapping PWRMBASE");
977 exit(1);
978 }
979
980 printf("\n=========== PWRMBASE ===========\n\n");
981 printf("PWRMBASE = 0x%08" PRIx64 " (MEM)\n\n", pwrmbase_phys);
982
983 for (i = 0; i < pwrmbase_size; i += 4) {
984 if (read32(pwrmbase + i))
985 printf("0x%04zx: 0x%08"PRIx32"\n",
986 i, read32(pwrmbase + i));
987 }
988
989 unmap_physical((void *)pwrmbase, pwrmbase_size);
990 }
991
992 return 0;
993 }
994