1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include "msrtool.h"
4
intel_pentium3_probe(const struct targetdef * target,const struct cpuid_t * id)5 int intel_pentium3_probe(const struct targetdef *target, const struct cpuid_t *id) {
6 return ((VENDOR_INTEL == id->vendor) &&
7 (0x6 == id->family) && (
8 (0xa == id->model) ||
9 (0xb == id->model)
10 ));
11 }
12
13 const struct msrdef intel_pentium3_msrs[] = {
14 {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
15 { BITS_EOT }
16 }},
17 {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
18 { BITS_EOT }
19 }},
20 {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {
21 { BITS_EOT }
22 }},
23 {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", {
24 { BITS_EOT }
25 }},
26 {0x33, MSRTYPE_RDWR, MSR2(0, 0), "TEST_CTL", "", {
27 { BITS_EOT }
28 }},
29 {0x3f, MSRTYPE_RDWR, MSR2(0, 0), "THERM_DIODE_OFFSET", "", {
30 { BITS_EOT }
31 }},
32 {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {
33 { BITS_EOT }
34 }},
35 {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR0", "", {
36 { BITS_EOT }
37 }},
38 {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR1", "", {
39 { BITS_EOT }
40 }},
41 {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", {
42 { BITS_EOT }
43 }},
44 {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
45 { BITS_EOT }
46 }},
47 {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
48 { BITS_EOT }
49 }},
50 {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
51 { BITS_EOT }
52 }},
53 {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", {
54 { BITS_EOT }
55 }},
56 {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", {
57 { BITS_EOT }
58 }},
59 {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {
60 { BITS_EOT }
61 }},
62 {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
63 { BITS_EOT }
64 }},
65 {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
66 { BITS_EOT }
67 }},
68 {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
69 { BITS_EOT }
70 }},
71 {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
72 { BITS_EOT }
73 }},
74 {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
75 { BITS_EOT }
76 }},
77 {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
78 { BITS_EOT }
79 }},
80 {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
81 { BITS_EOT }
82 }},
83 {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
84 { BITS_EOT }
85 }},
86 {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
87 { BITS_EOT }
88 }},
89 {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
90 { BITS_EOT }
91 }},
92 {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
93 { BITS_EOT }
94 }},
95 {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
96 { BITS_EOT }
97 }},
98 {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
99 { BITS_EOT }
100 }},
101 {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
102 { BITS_EOT }
103 }},
104 {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
105 { BITS_EOT }
106 }},
107 {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
108 { BITS_EOT }
109 }},
110 {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
111 { BITS_EOT }
112 }},
113 {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
114 { BITS_EOT }
115 }},
116 {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
117 { BITS_EOT }
118 }},
119 {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
120 { BITS_EOT }
121 }},
122 {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
123 { BITS_EOT }
124 }},
125 {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
126 { BITS_EOT }
127 }},
128 {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
129 { BITS_EOT }
130 }},
131 {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
132 { BITS_EOT }
133 }},
134 {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
135 { BITS_EOT }
136 }},
137 {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
138 { BITS_EOT }
139 }},
140 {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
141 { BITS_EOT }
142 }},
143 {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
144 { BITS_EOT }
145 }},
146 {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
147 { BITS_EOT }
148 }},
149 {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
150 { BITS_EOT }
151 }},
152 {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
153 { BITS_EOT }
154 }},
155 {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
156 { BITS_EOT }
157 }},
158 {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
159 { BITS_EOT }
160 }},
161 {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
162 { BITS_EOT }
163 }},
164 {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
165 { BITS_EOT }
166 }},
167 { MSR_EOT }
168 };
169