xref: /aosp_15_r20/external/cpu_features/include/internal/hwcaps.h (revision eca53ba6d2e951e174b64682eaf56a36b8204c89)
1*eca53ba6SRoland Levillain // Copyright 2017 Google LLC
2*eca53ba6SRoland Levillain //
3*eca53ba6SRoland Levillain // Licensed under the Apache License, Version 2.0 (the "License");
4*eca53ba6SRoland Levillain // you may not use this file except in compliance with the License.
5*eca53ba6SRoland Levillain // You may obtain a copy of the License at
6*eca53ba6SRoland Levillain //
7*eca53ba6SRoland Levillain //    http://www.apache.org/licenses/LICENSE-2.0
8*eca53ba6SRoland Levillain //
9*eca53ba6SRoland Levillain // Unless required by applicable law or agreed to in writing, software
10*eca53ba6SRoland Levillain // distributed under the License is distributed on an "AS IS" BASIS,
11*eca53ba6SRoland Levillain // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12*eca53ba6SRoland Levillain // See the License for the specific language governing permissions and
13*eca53ba6SRoland Levillain // limitations under the License.
14*eca53ba6SRoland Levillain 
15*eca53ba6SRoland Levillain // Interface to retrieve hardware capabilities. It relies on Linux's getauxval
16*eca53ba6SRoland Levillain // or `/proc/self/auxval` under the hood.
17*eca53ba6SRoland Levillain #ifndef CPU_FEATURES_INCLUDE_INTERNAL_HWCAPS_H_
18*eca53ba6SRoland Levillain #define CPU_FEATURES_INCLUDE_INTERNAL_HWCAPS_H_
19*eca53ba6SRoland Levillain 
20*eca53ba6SRoland Levillain #include <stdbool.h>
21*eca53ba6SRoland Levillain #include <stdint.h>
22*eca53ba6SRoland Levillain 
23*eca53ba6SRoland Levillain #include "cpu_features_macros.h"
24*eca53ba6SRoland Levillain 
25*eca53ba6SRoland Levillain CPU_FEATURES_START_CPP_NAMESPACE
26*eca53ba6SRoland Levillain 
27*eca53ba6SRoland Levillain // To avoid depending on the linux kernel we reproduce the architecture specific
28*eca53ba6SRoland Levillain // constants here.
29*eca53ba6SRoland Levillain 
30*eca53ba6SRoland Levillain // http://elixir.free-electrons.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
31*eca53ba6SRoland Levillain #define AARCH64_HWCAP_FP (1UL << 0)
32*eca53ba6SRoland Levillain #define AARCH64_HWCAP_ASIMD (1UL << 1)
33*eca53ba6SRoland Levillain #define AARCH64_HWCAP_EVTSTRM (1UL << 2)
34*eca53ba6SRoland Levillain #define AARCH64_HWCAP_AES (1UL << 3)
35*eca53ba6SRoland Levillain #define AARCH64_HWCAP_PMULL (1UL << 4)
36*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SHA1 (1UL << 5)
37*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SHA2 (1UL << 6)
38*eca53ba6SRoland Levillain #define AARCH64_HWCAP_CRC32 (1UL << 7)
39*eca53ba6SRoland Levillain #define AARCH64_HWCAP_ATOMICS (1UL << 8)
40*eca53ba6SRoland Levillain #define AARCH64_HWCAP_FPHP (1UL << 9)
41*eca53ba6SRoland Levillain #define AARCH64_HWCAP_ASIMDHP (1UL << 10)
42*eca53ba6SRoland Levillain #define AARCH64_HWCAP_CPUID (1UL << 11)
43*eca53ba6SRoland Levillain #define AARCH64_HWCAP_ASIMDRDM (1UL << 12)
44*eca53ba6SRoland Levillain #define AARCH64_HWCAP_JSCVT (1UL << 13)
45*eca53ba6SRoland Levillain #define AARCH64_HWCAP_FCMA (1UL << 14)
46*eca53ba6SRoland Levillain #define AARCH64_HWCAP_LRCPC (1UL << 15)
47*eca53ba6SRoland Levillain #define AARCH64_HWCAP_DCPOP (1UL << 16)
48*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SHA3 (1UL << 17)
49*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SM3 (1UL << 18)
50*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SM4 (1UL << 19)
51*eca53ba6SRoland Levillain #define AARCH64_HWCAP_ASIMDDP (1UL << 20)
52*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SHA512 (1UL << 21)
53*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SVE (1UL << 22)
54*eca53ba6SRoland Levillain #define AARCH64_HWCAP_ASIMDFHM (1UL << 23)
55*eca53ba6SRoland Levillain #define AARCH64_HWCAP_DIT (1UL << 24)
56*eca53ba6SRoland Levillain #define AARCH64_HWCAP_USCAT (1UL << 25)
57*eca53ba6SRoland Levillain #define AARCH64_HWCAP_ILRCPC (1UL << 26)
58*eca53ba6SRoland Levillain #define AARCH64_HWCAP_FLAGM (1UL << 27)
59*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SSBS (1UL << 28)
60*eca53ba6SRoland Levillain #define AARCH64_HWCAP_SB (1UL << 29)
61*eca53ba6SRoland Levillain #define AARCH64_HWCAP_PACA (1UL << 30)
62*eca53ba6SRoland Levillain #define AARCH64_HWCAP_PACG (1UL << 31)
63*eca53ba6SRoland Levillain 
64*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_DCPODP (1UL << 0)
65*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVE2 (1UL << 1)
66*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVEAES (1UL << 2)
67*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVEPMULL (1UL << 3)
68*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVEBITPERM (1UL << 4)
69*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVESHA3 (1UL << 5)
70*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVESM4 (1UL << 6)
71*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_FLAGM2 (1UL << 7)
72*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_FRINT (1UL << 8)
73*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVEI8MM (1UL << 9)
74*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVEF32MM (1UL << 10)
75*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVEF64MM (1UL << 11)
76*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVEBF16 (1UL << 12)
77*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_I8MM (1UL << 13)
78*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_BF16 (1UL << 14)
79*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_DGH (1UL << 15)
80*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_RNG (1UL << 16)
81*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_BTI (1UL << 17)
82*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_MTE (1UL << 18)
83*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_ECV (1UL << 19)
84*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_AFP (1UL << 20)
85*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_RPRES (1UL << 21)
86*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_MTE3 (1UL << 22)
87*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME (1UL << 23)
88*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_I16I64 (1UL << 24)
89*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_F64F64 (1UL << 25)
90*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_I8I32 (1UL << 26)
91*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_F16F32 (1UL << 27)
92*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_B16F32 (1UL << 28)
93*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_F32F32 (1UL << 29)
94*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_FA64 (1UL << 30)
95*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_WFXT (1UL << 31)
96*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_EBF16 (1UL << 32)
97*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVE_EBF16 (1UL << 33)
98*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_CSSC (1UL << 34)
99*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_RPRFM (1UL << 35)
100*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SVE2P1 (1UL << 36)
101*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME2 (1UL << 37)
102*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME2P1 (1UL << 38)
103*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_I16I32 (1UL << 39)
104*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_BI32I32 (1UL << 40)
105*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_B16B16 (1UL << 41)
106*eca53ba6SRoland Levillain #define AARCH64_HWCAP2_SME_F16F16 (1UL << 42)
107*eca53ba6SRoland Levillain 
108*eca53ba6SRoland Levillain // http://elixir.free-electrons.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
109*eca53ba6SRoland Levillain #define ARM_HWCAP_SWP (1UL << 0)
110*eca53ba6SRoland Levillain #define ARM_HWCAP_HALF (1UL << 1)
111*eca53ba6SRoland Levillain #define ARM_HWCAP_THUMB (1UL << 2)
112*eca53ba6SRoland Levillain #define ARM_HWCAP_26BIT (1UL << 3)
113*eca53ba6SRoland Levillain #define ARM_HWCAP_FAST_MULT (1UL << 4)
114*eca53ba6SRoland Levillain #define ARM_HWCAP_FPA (1UL << 5)
115*eca53ba6SRoland Levillain #define ARM_HWCAP_VFP (1UL << 6)
116*eca53ba6SRoland Levillain #define ARM_HWCAP_EDSP (1UL << 7)
117*eca53ba6SRoland Levillain #define ARM_HWCAP_JAVA (1UL << 8)
118*eca53ba6SRoland Levillain #define ARM_HWCAP_IWMMXT (1UL << 9)
119*eca53ba6SRoland Levillain #define ARM_HWCAP_CRUNCH (1UL << 10)
120*eca53ba6SRoland Levillain #define ARM_HWCAP_THUMBEE (1UL << 11)
121*eca53ba6SRoland Levillain #define ARM_HWCAP_NEON (1UL << 12)
122*eca53ba6SRoland Levillain #define ARM_HWCAP_VFPV3 (1UL << 13)
123*eca53ba6SRoland Levillain #define ARM_HWCAP_VFPV3D16 (1UL << 14)
124*eca53ba6SRoland Levillain #define ARM_HWCAP_TLS (1UL << 15)
125*eca53ba6SRoland Levillain #define ARM_HWCAP_VFPV4 (1UL << 16)
126*eca53ba6SRoland Levillain #define ARM_HWCAP_IDIVA (1UL << 17)
127*eca53ba6SRoland Levillain #define ARM_HWCAP_IDIVT (1UL << 18)
128*eca53ba6SRoland Levillain #define ARM_HWCAP_VFPD32 (1UL << 19)
129*eca53ba6SRoland Levillain #define ARM_HWCAP_LPAE (1UL << 20)
130*eca53ba6SRoland Levillain #define ARM_HWCAP_EVTSTRM (1UL << 21)
131*eca53ba6SRoland Levillain #define ARM_HWCAP2_AES (1UL << 0)
132*eca53ba6SRoland Levillain #define ARM_HWCAP2_PMULL (1UL << 1)
133*eca53ba6SRoland Levillain #define ARM_HWCAP2_SHA1 (1UL << 2)
134*eca53ba6SRoland Levillain #define ARM_HWCAP2_SHA2 (1UL << 3)
135*eca53ba6SRoland Levillain #define ARM_HWCAP2_CRC32 (1UL << 4)
136*eca53ba6SRoland Levillain 
137*eca53ba6SRoland Levillain // http://elixir.free-electrons.com/linux/latest/source/arch/mips/include/uapi/asm/hwcap.h
138*eca53ba6SRoland Levillain #define MIPS_HWCAP_R6 (1UL << 0)
139*eca53ba6SRoland Levillain #define MIPS_HWCAP_MSA (1UL << 1)
140*eca53ba6SRoland Levillain #define MIPS_HWCAP_CRC32 (1UL << 2)
141*eca53ba6SRoland Levillain #define MIPS_HWCAP_MIPS16 (1UL << 3)
142*eca53ba6SRoland Levillain #define MIPS_HWCAP_MDMX (1UL << 4)
143*eca53ba6SRoland Levillain #define MIPS_HWCAP_MIPS3D (1UL << 5)
144*eca53ba6SRoland Levillain #define MIPS_HWCAP_SMARTMIPS (1UL << 6)
145*eca53ba6SRoland Levillain #define MIPS_HWCAP_DSP (1UL << 7)
146*eca53ba6SRoland Levillain #define MIPS_HWCAP_DSP2 (1UL << 8)
147*eca53ba6SRoland Levillain #define MIPS_HWCAP_DSP3 (1UL << 9)
148*eca53ba6SRoland Levillain 
149*eca53ba6SRoland Levillain // http://elixir.free-electrons.com/linux/latest/source/arch/powerpc/include/uapi/asm/cputable.h
150*eca53ba6SRoland Levillain #ifndef _UAPI__ASM_POWERPC_CPUTABLE_H
151*eca53ba6SRoland Levillain /* in AT_HWCAP */
152*eca53ba6SRoland Levillain #define PPC_FEATURE_32 0x80000000
153*eca53ba6SRoland Levillain #define PPC_FEATURE_64 0x40000000
154*eca53ba6SRoland Levillain #define PPC_FEATURE_601_INSTR 0x20000000
155*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
156*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_FPU 0x08000000
157*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_MMU 0x04000000
158*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_4xxMAC 0x02000000
159*eca53ba6SRoland Levillain #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
160*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_SPE 0x00800000
161*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
162*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
163*eca53ba6SRoland Levillain #define PPC_FEATURE_NO_TB 0x00100000
164*eca53ba6SRoland Levillain #define PPC_FEATURE_POWER4 0x00080000
165*eca53ba6SRoland Levillain #define PPC_FEATURE_POWER5 0x00040000
166*eca53ba6SRoland Levillain #define PPC_FEATURE_POWER5_PLUS 0x00020000
167*eca53ba6SRoland Levillain #define PPC_FEATURE_CELL 0x00010000
168*eca53ba6SRoland Levillain #define PPC_FEATURE_BOOKE 0x00008000
169*eca53ba6SRoland Levillain #define PPC_FEATURE_SMT 0x00004000
170*eca53ba6SRoland Levillain #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
171*eca53ba6SRoland Levillain #define PPC_FEATURE_ARCH_2_05 0x00001000
172*eca53ba6SRoland Levillain #define PPC_FEATURE_PA6T 0x00000800
173*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_DFP 0x00000400
174*eca53ba6SRoland Levillain #define PPC_FEATURE_POWER6_EXT 0x00000200
175*eca53ba6SRoland Levillain #define PPC_FEATURE_ARCH_2_06 0x00000100
176*eca53ba6SRoland Levillain #define PPC_FEATURE_HAS_VSX 0x00000080
177*eca53ba6SRoland Levillain 
178*eca53ba6SRoland Levillain #define PPC_FEATURE_PSERIES_PERFMON_COMPAT 0x00000040
179*eca53ba6SRoland Levillain 
180*eca53ba6SRoland Levillain /* Reserved - do not use                0x00000004 */
181*eca53ba6SRoland Levillain #define PPC_FEATURE_TRUE_LE 0x00000002
182*eca53ba6SRoland Levillain #define PPC_FEATURE_PPC_LE 0x00000001
183*eca53ba6SRoland Levillain 
184*eca53ba6SRoland Levillain /* in AT_HWCAP2 */
185*eca53ba6SRoland Levillain #define PPC_FEATURE2_ARCH_2_07 0x80000000
186*eca53ba6SRoland Levillain #define PPC_FEATURE2_HTM 0x40000000
187*eca53ba6SRoland Levillain #define PPC_FEATURE2_DSCR 0x20000000
188*eca53ba6SRoland Levillain #define PPC_FEATURE2_EBB 0x10000000
189*eca53ba6SRoland Levillain #define PPC_FEATURE2_ISEL 0x08000000
190*eca53ba6SRoland Levillain #define PPC_FEATURE2_TAR 0x04000000
191*eca53ba6SRoland Levillain #define PPC_FEATURE2_VEC_CRYPTO 0x02000000
192*eca53ba6SRoland Levillain #define PPC_FEATURE2_HTM_NOSC 0x01000000
193*eca53ba6SRoland Levillain #define PPC_FEATURE2_ARCH_3_00 0x00800000
194*eca53ba6SRoland Levillain #define PPC_FEATURE2_HAS_IEEE128 0x00400000
195*eca53ba6SRoland Levillain #define PPC_FEATURE2_DARN 0x00200000
196*eca53ba6SRoland Levillain #define PPC_FEATURE2_SCV 0x00100000
197*eca53ba6SRoland Levillain #define PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000
198*eca53ba6SRoland Levillain #endif
199*eca53ba6SRoland Levillain 
200*eca53ba6SRoland Levillain // https://elixir.bootlin.com/linux/v6.0-rc6/source/arch/s390/include/asm/elf.h
201*eca53ba6SRoland Levillain #define HWCAP_S390_ESAN3        1
202*eca53ba6SRoland Levillain #define HWCAP_S390_ZARCH        2
203*eca53ba6SRoland Levillain #define HWCAP_S390_STFLE        4
204*eca53ba6SRoland Levillain #define HWCAP_S390_MSA          8
205*eca53ba6SRoland Levillain #define HWCAP_S390_LDISP        16
206*eca53ba6SRoland Levillain #define HWCAP_S390_EIMM         32
207*eca53ba6SRoland Levillain #define HWCAP_S390_DFP          64
208*eca53ba6SRoland Levillain #define HWCAP_S390_HPAGE        128
209*eca53ba6SRoland Levillain #define HWCAP_S390_ETF3EH       256
210*eca53ba6SRoland Levillain #define HWCAP_S390_HIGH_GPRS    512
211*eca53ba6SRoland Levillain #define HWCAP_S390_TE           1024
212*eca53ba6SRoland Levillain #define HWCAP_S390_VX           2048
213*eca53ba6SRoland Levillain #define HWCAP_S390_VXRS         HWCAP_S390_VX
214*eca53ba6SRoland Levillain #define HWCAP_S390_VXD          4096
215*eca53ba6SRoland Levillain #define HWCAP_S390_VXRS_BCD     HWCAP_S390_VXD
216*eca53ba6SRoland Levillain #define HWCAP_S390_VXE          8192
217*eca53ba6SRoland Levillain #define HWCAP_S390_VXRS_EXT     HWCAP_S390_VXE
218*eca53ba6SRoland Levillain #define HWCAP_S390_GS           16384
219*eca53ba6SRoland Levillain #define HWCAP_S390_VXRS_EXT2    32768
220*eca53ba6SRoland Levillain #define HWCAP_S390_VXRS_PDE     65536
221*eca53ba6SRoland Levillain #define HWCAP_S390_SORT         131072
222*eca53ba6SRoland Levillain #define HWCAP_S390_DFLT         262144
223*eca53ba6SRoland Levillain #define HWCAP_S390_VXRS_PDE2    524288
224*eca53ba6SRoland Levillain #define HWCAP_S390_NNPA         1048576
225*eca53ba6SRoland Levillain #define HWCAP_S390_PCI_MIO      2097152
226*eca53ba6SRoland Levillain #define HWCAP_S390_SIE          4194304
227*eca53ba6SRoland Levillain 
228*eca53ba6SRoland Levillain // https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/uapi/asm/hwcap.h
229*eca53ba6SRoland Levillain #define RISCV_HWCAP_32 0x32
230*eca53ba6SRoland Levillain #define RISCV_HWCAP_64 0x64
231*eca53ba6SRoland Levillain #define RISCV_HWCAP_128 0x128
232*eca53ba6SRoland Levillain #define RISCV_HWCAP_M (1UL << ('M' - 'A'))
233*eca53ba6SRoland Levillain #define RISCV_HWCAP_A (1UL << ('A' - 'A'))
234*eca53ba6SRoland Levillain #define RISCV_HWCAP_F (1UL << ('F' - 'A'))
235*eca53ba6SRoland Levillain #define RISCV_HWCAP_D (1UL << ('D' - 'A'))
236*eca53ba6SRoland Levillain #define RISCV_HWCAP_Q (1UL << ('Q' - 'A'))
237*eca53ba6SRoland Levillain #define RISCV_HWCAP_C (1UL << ('C' - 'A'))
238*eca53ba6SRoland Levillain #define RISCV_HWCAP_V (1UL << ('V' - 'A'))
239*eca53ba6SRoland Levillain 
240*eca53ba6SRoland Levillain // https://github.com/torvalds/linux/blob/master/arch/loongarch/include/uapi/asm/hwcap.h
241*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_CPUCFG   (1 << 0)
242*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_LAM      (1 << 1)
243*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_UAL      (1 << 2)
244*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_FPU      (1 << 3)
245*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_LSX      (1 << 4)
246*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_LASX     (1 << 5)
247*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_CRC32    (1 << 6)
248*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_COMPLEX  (1 << 7)
249*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_CRYPTO   (1 << 8)
250*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_LVZ      (1 << 9)
251*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_LBT_X86  (1 << 10)
252*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_LBT_ARM  (1 << 11)
253*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_LBT_MIPS (1 << 12)
254*eca53ba6SRoland Levillain #define HWCAP_LOONGARCH_PTW      (1 << 13)
255*eca53ba6SRoland Levillain 
256*eca53ba6SRoland Levillain typedef struct {
257*eca53ba6SRoland Levillain   unsigned long hwcaps;
258*eca53ba6SRoland Levillain   unsigned long hwcaps2;
259*eca53ba6SRoland Levillain } HardwareCapabilities;
260*eca53ba6SRoland Levillain 
261*eca53ba6SRoland Levillain // Retrieves values from auxiliary vector for types AT_HWCAP and AT_HWCAP2.
262*eca53ba6SRoland Levillain // First tries to call getauxval(), if not available falls back to reading
263*eca53ba6SRoland Levillain // "/proc/self/auxv".
264*eca53ba6SRoland Levillain HardwareCapabilities CpuFeatures_GetHardwareCapabilities(void);
265*eca53ba6SRoland Levillain 
266*eca53ba6SRoland Levillain // Checks whether value for AT_HWCAP (or AT_HWCAP2) match hwcaps_mask.
267*eca53ba6SRoland Levillain bool CpuFeatures_IsHwCapsSet(const HardwareCapabilities hwcaps_mask,
268*eca53ba6SRoland Levillain                              const HardwareCapabilities hwcaps);
269*eca53ba6SRoland Levillain 
270*eca53ba6SRoland Levillain // Get pointer for the AT_PLATFORM type.
271*eca53ba6SRoland Levillain const char* CpuFeatures_GetPlatformPointer(void);
272*eca53ba6SRoland Levillain // Get pointer for the AT_BASE_PLATFORM type.
273*eca53ba6SRoland Levillain const char* CpuFeatures_GetBasePlatformPointer(void);
274*eca53ba6SRoland Levillain 
275*eca53ba6SRoland Levillain CPU_FEATURES_END_CPP_NAMESPACE
276*eca53ba6SRoland Levillain 
277*eca53ba6SRoland Levillain #endif  // CPU_FEATURES_INCLUDE_INTERNAL_HWCAPS_H_
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