1// Copyright 2021 Google LLC 2// 3// Licensed under the Apache License, Version 2.0 (the "License"); 4// you may not use this file except in compliance with the License. 5// You may obtain a copy of the License at 6// 7// http://www.apache.org/licenses/LICENSE-2.0 8// 9// Unless required by applicable law or agreed to in writing, software 10// distributed under the License is distributed on an "AS IS" BASIS, 11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12// See the License for the specific language governing permissions and 13// limitations under the License. 14 15#include <stdbool.h> 16 17#include "cpu_features_macros.h" 18#include "cpuinfo_aarch64.h" 19#include "internal/bit_utils.h" 20#include "internal/filesystem.h" 21#include "internal/stack_line_reader.h" 22#include "internal/string_view.h" 23 24#if !defined(CPU_FEATURES_ARCH_AARCH64) 25#error "Cannot compile aarch64_base on a non aarch64 platform." 26#endif 27 28//////////////////////////////////////////////////////////////////////////////// 29// Definitions for introspection. 30//////////////////////////////////////////////////////////////////////////////// 31#define INTROSPECTION_TABLE \ 32 LINE(AARCH64_FP, fp, "fp", AARCH64_HWCAP_FP, 0) \ 33 LINE(AARCH64_ASIMD, asimd, "asimd", AARCH64_HWCAP_ASIMD, 0) \ 34 LINE(AARCH64_EVTSTRM, evtstrm, "evtstrm", AARCH64_HWCAP_EVTSTRM, 0) \ 35 LINE(AARCH64_AES, aes, "aes", AARCH64_HWCAP_AES, 0) \ 36 LINE(AARCH64_PMULL, pmull, "pmull", AARCH64_HWCAP_PMULL, 0) \ 37 LINE(AARCH64_SHA1, sha1, "sha1", AARCH64_HWCAP_SHA1, 0) \ 38 LINE(AARCH64_SHA2, sha2, "sha2", AARCH64_HWCAP_SHA2, 0) \ 39 LINE(AARCH64_CRC32, crc32, "crc32", AARCH64_HWCAP_CRC32, 0) \ 40 LINE(AARCH64_ATOMICS, atomics, "atomics", AARCH64_HWCAP_ATOMICS, 0) \ 41 LINE(AARCH64_FPHP, fphp, "fphp", AARCH64_HWCAP_FPHP, 0) \ 42 LINE(AARCH64_ASIMDHP, asimdhp, "asimdhp", AARCH64_HWCAP_ASIMDHP, 0) \ 43 LINE(AARCH64_CPUID, cpuid, "cpuid", AARCH64_HWCAP_CPUID, 0) \ 44 LINE(AARCH64_ASIMDRDM, asimdrdm, "asimdrdm", AARCH64_HWCAP_ASIMDRDM, 0) \ 45 LINE(AARCH64_JSCVT, jscvt, "jscvt", AARCH64_HWCAP_JSCVT, 0) \ 46 LINE(AARCH64_FCMA, fcma, "fcma", AARCH64_HWCAP_FCMA, 0) \ 47 LINE(AARCH64_LRCPC, lrcpc, "lrcpc", AARCH64_HWCAP_LRCPC, 0) \ 48 LINE(AARCH64_DCPOP, dcpop, "dcpop", AARCH64_HWCAP_DCPOP, 0) \ 49 LINE(AARCH64_SHA3, sha3, "sha3", AARCH64_HWCAP_SHA3, 0) \ 50 LINE(AARCH64_SM3, sm3, "sm3", AARCH64_HWCAP_SM3, 0) \ 51 LINE(AARCH64_SM4, sm4, "sm4", AARCH64_HWCAP_SM4, 0) \ 52 LINE(AARCH64_ASIMDDP, asimddp, "asimddp", AARCH64_HWCAP_ASIMDDP, 0) \ 53 LINE(AARCH64_SHA512, sha512, "sha512", AARCH64_HWCAP_SHA512, 0) \ 54 LINE(AARCH64_SVE, sve, "sve", AARCH64_HWCAP_SVE, 0) \ 55 LINE(AARCH64_ASIMDFHM, asimdfhm, "asimdfhm", AARCH64_HWCAP_ASIMDFHM, 0) \ 56 LINE(AARCH64_DIT, dit, "dit", AARCH64_HWCAP_DIT, 0) \ 57 LINE(AARCH64_USCAT, uscat, "uscat", AARCH64_HWCAP_USCAT, 0) \ 58 LINE(AARCH64_ILRCPC, ilrcpc, "ilrcpc", AARCH64_HWCAP_ILRCPC, 0) \ 59 LINE(AARCH64_FLAGM, flagm, "flagm", AARCH64_HWCAP_FLAGM, 0) \ 60 LINE(AARCH64_SSBS, ssbs, "ssbs", AARCH64_HWCAP_SSBS, 0) \ 61 LINE(AARCH64_SB, sb, "sb", AARCH64_HWCAP_SB, 0) \ 62 LINE(AARCH64_PACA, paca, "paca", AARCH64_HWCAP_PACA, 0) \ 63 LINE(AARCH64_PACG, pacg, "pacg", AARCH64_HWCAP_PACG, 0) \ 64 LINE(AARCH64_DCPODP, dcpodp, "dcpodp", 0, AARCH64_HWCAP2_DCPODP) \ 65 LINE(AARCH64_SVE2, sve2, "sve2", 0, AARCH64_HWCAP2_SVE2) \ 66 LINE(AARCH64_SVEAES, sveaes, "sveaes", 0, AARCH64_HWCAP2_SVEAES) \ 67 LINE(AARCH64_SVEPMULL, svepmull, "svepmull", 0, AARCH64_HWCAP2_SVEPMULL) \ 68 LINE(AARCH64_SVEBITPERM, svebitperm, "svebitperm", 0, \ 69 AARCH64_HWCAP2_SVEBITPERM) \ 70 LINE(AARCH64_SVESHA3, svesha3, "svesha3", 0, AARCH64_HWCAP2_SVESHA3) \ 71 LINE(AARCH64_SVESM4, svesm4, "svesm4", 0, AARCH64_HWCAP2_SVESM4) \ 72 LINE(AARCH64_FLAGM2, flagm2, "flagm2", 0, AARCH64_HWCAP2_FLAGM2) \ 73 LINE(AARCH64_FRINT, frint, "frint", 0, AARCH64_HWCAP2_FRINT) \ 74 LINE(AARCH64_SVEI8MM, svei8mm, "svei8mm", 0, AARCH64_HWCAP2_SVEI8MM) \ 75 LINE(AARCH64_SVEF32MM, svef32mm, "svef32mm", 0, AARCH64_HWCAP2_SVEF32MM) \ 76 LINE(AARCH64_SVEF64MM, svef64mm, "svef64mm", 0, AARCH64_HWCAP2_SVEF64MM) \ 77 LINE(AARCH64_SVEBF16, svebf16, "svebf16", 0, AARCH64_HWCAP2_SVEBF16) \ 78 LINE(AARCH64_I8MM, i8mm, "i8mm", 0, AARCH64_HWCAP2_I8MM) \ 79 LINE(AARCH64_BF16, bf16, "bf16", 0, AARCH64_HWCAP2_BF16) \ 80 LINE(AARCH64_DGH, dgh, "dgh", 0, AARCH64_HWCAP2_DGH) \ 81 LINE(AARCH64_RNG, rng, "rng", 0, AARCH64_HWCAP2_RNG) \ 82 LINE(AARCH64_BTI, bti, "bti", 0, AARCH64_HWCAP2_BTI) \ 83 LINE(AARCH64_MTE, mte, "mte", 0, AARCH64_HWCAP2_MTE) \ 84 LINE(AARCH64_ECV, ecv, "ecv", 0, AARCH64_HWCAP2_ECV) \ 85 LINE(AARCH64_AFP, afp, "afp", 0, AARCH64_HWCAP2_AFP) \ 86 LINE(AARCH64_RPRES, rpres, "rpres", 0, AARCH64_HWCAP2_RPRES) \ 87 LINE(AARCH64_MTE3, mte3, "mte3", 0, AARCH64_HWCAP2_MTE3) \ 88 LINE(AARCH64_SME, sme, "sme", 0, AARCH64_HWCAP2_SME) \ 89 LINE(AARCH64_SME_I16I64, smei16i64, "smei16i64", 0, \ 90 AARCH64_HWCAP2_SME_I16I64) \ 91 LINE(AARCH64_SME_F64F64, smef64f64, "smef64f64", 0, \ 92 AARCH64_HWCAP2_SME_F64F64) \ 93 LINE(AARCH64_SME_I8I32, smei8i32, "smei8i32", 0, AARCH64_HWCAP2_SME_I8I32) \ 94 LINE(AARCH64_SME_F16F32, smef16f32, "smef16f32", 0, \ 95 AARCH64_HWCAP2_SME_F16F32) \ 96 LINE(AARCH64_SME_B16F32, smeb16f32, "smeb16f32", 0, \ 97 AARCH64_HWCAP2_SME_B16F32) \ 98 LINE(AARCH64_SME_F32F32, smef32f32, "smef32f32", 0, \ 99 AARCH64_HWCAP2_SME_F32F32) \ 100 LINE(AARCH64_SME_FA64, smefa64, "smefa64", 0, AARCH64_HWCAP2_SME_FA64) \ 101 LINE(AARCH64_WFXT, wfxt, "wfxt", 0, AARCH64_HWCAP2_WFXT) \ 102 LINE(AARCH64_EBF16, ebf16, "ebf16", 0, AARCH64_HWCAP2_EBF16) \ 103 LINE(AARCH64_SVE_EBF16, sveebf16, "sveebf16", 0, AARCH64_HWCAP2_SVE_EBF16) \ 104 LINE(AARCH64_CSSC, cssc, "cssc", 0, AARCH64_HWCAP2_CSSC) \ 105 LINE(AARCH64_RPRFM, rprfm, "rprfm", 0, AARCH64_HWCAP2_RPRFM) \ 106 LINE(AARCH64_SVE2P1, sve2p1, "sve2p1", 0, AARCH64_HWCAP2_SVE2P1) \ 107 LINE(AARCH64_SME2, sme2, "sme2", 0, AARCH64_HWCAP2_SME2) \ 108 LINE(AARCH64_SME2P1, sme2p1, "sme2p1", 0, AARCH64_HWCAP2_SME2P1) \ 109 LINE(AARCH64_SME_I16I32, smei16i32, "smei16i32", 0, \ 110 AARCH64_HWCAP2_SME_I16I32) \ 111 LINE(AARCH64_SME_BI32I32, smebi32i32, "smebi32i32", 0, \ 112 AARCH64_HWCAP2_SME_BI32I32) \ 113 LINE(AARCH64_SME_B16B16, smeb16b16, "smeb16b16", 0, \ 114 AARCH64_HWCAP2_SME_B16B16) \ 115 LINE(AARCH64_SME_F16F16, smef16f16, "smef16f16", 0, AARCH64_HWCAP2_SME_F16F16) 116#define INTROSPECTION_PREFIX Aarch64 117#define INTROSPECTION_ENUM_PREFIX AARCH64 118#include "define_introspection_and_hwcaps.inl" 119