1 // Copyright 2020 The ChromiumOS Authors
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // These cpuid bit definitions come from HAXM here:
6 // https://github.com/intel/haxm/blob/v7.6.1/core/include/cpuid.h#L97
7
8 use bitflags::bitflags;
9
feature_bit(bit: u32) -> u3210 const fn feature_bit(bit: u32) -> u32 {
11 1 << bit
12 }
13
14 /*
15 * Intel SDM Vol. 2A: Table 3-10.
16 * Feature Information Returned in the ECX Register
17 * Features for CPUID with EAX=01h stored in ECX
18 */
19 bitflags! {
20 #[derive(Copy, Clone, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
21 #[repr(transparent)]
22 pub struct Feature1Ecx: u32 {
23 const SSE3 = feature_bit(0); /* 0x00000001 Streaming SIMD Extensions 3 */
24 const PCLMULQDQ = feature_bit(1); /* 0x00000002 PCLMULQDQ Instruction */
25 const DTES64 = feature_bit(2); /* 0x00000004 64-bit DS Area */
26 const MONITOR = feature_bit(3); /* 0x00000008 MONITOR/MWAIT Instructions */
27 const DS_CPL = feature_bit(4); /* 0x00000010 CPL Qualified Debug Store */
28 const VMX = feature_bit(5); /* 0x00000020 Virtual Machine Extensions */
29 const SMX = feature_bit(6); /* 0x00000040 Safer Mode Extensions */
30 const EIST = feature_bit(7); /* 0x00000080 Enhanced Intel SpeedStep technology */
31 const TM2 = feature_bit(8); /* 0x00000100 Thermal Monitor 2 */
32 const SSSE3 = feature_bit(9); /* 0x00000200 Supplemental Streaming SIMD Extensions 3 */
33 const CNXT_ID = feature_bit(10); /* 0x00000400 L1 Context ID */
34 const SDBG = feature_bit(11); /* 0x00000800 Silicon Debug Interface */
35 const FMA = feature_bit(12); /* 0x00001000 Fused Multiply-Add */
36 const CMPXCHG16B = feature_bit(13); /* 0x00002000 CMPXCHG16B Instruction */
37 const XTPR_UPDATE = feature_bit(14); /* 0x00004000 xTPR Update Control */
38 const PDCM = feature_bit(15); /* 0x00008000 Perfmon and Debug Capability */
39 const PCID = feature_bit(17); /* 0x00020000 Process-context identifiers */
40 const DCA = feature_bit(18); /* 0x00040000 Direct cache access for DMA writes */
41 const SSE41 = feature_bit(19); /* 0x00080000 Streaming SIMD Extensions 4.1 */
42 const SSE42 = feature_bit(20); /* 0x00100000 Streaming SIMD Extensions 4.2 */
43 const X2APIC = feature_bit(21); /* 0x00200000 x2APIC support */
44 const MOVBE = feature_bit(22); /* 0x00400000 MOVBE Instruction */
45 const POPCNT = feature_bit(23); /* 0x00800000 POPCNT Instruction */
46 const TSC_DEADLINE = feature_bit(24); /* 0x01000000 APIC supports one-shot operation using TSC deadline */
47 const AESNI = feature_bit(25); /* 0x02000000 AESNI Extension */
48 const XSAVE = feature_bit(26); /* 0x04000000 XSAVE/XRSTOR/XSETBV/XGETBV Instructions and XCR0 */
49 const OSXSAVE = feature_bit(27); /* 0x08000000 XSAVE enabled by OS */
50 const AVX = feature_bit(28); /* 0x10000000 Advanced Vector Extensions */
51 const F16C = feature_bit(29); /* 0x20000000 16-bit Floating-Point Instructions */
52 const RDRAND = feature_bit(30); /* 0x40000000 RDRAND Instruction */
53 const HYPERVISOR = feature_bit(31); /* 0x80000000 Hypervisor Running */
54 }
55 }
56
57 /*
58 * Intel SDM Vol. 2A: Table 3-11.
59 * More on Feature Information Returned in the EDX Register
60 * Features for CPUID with EAX=01h stored in EDX
61 */
62 bitflags! {
63 #[derive(Copy, Clone, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
64 #[repr(transparent)]
65 pub struct Feature1Edx: u32 {
66 const FPU = feature_bit(0); /* 0x00000001 Floating Point Unit On-Chip */
67 const VME = feature_bit(1); /* 0x00000002 Virtual 8086 Mode Enhancements */
68 const DE = feature_bit(2); /* 0x00000004 Debugging Extensions */
69 const PSE = feature_bit(3); /* 0x00000008 Page Size Extension */
70 const TSC = feature_bit(4); /* 0x00000010 Time Stamp Counter */
71 const MSR = feature_bit(5); /* 0x00000020 RDMSR/WRMSR Instructions */
72 const PAE = feature_bit(6); /* 0x00000040 Physical Address Extension */
73 const MCE = feature_bit(7); /* 0x00000080 Machine Check Exception */
74 const CX8 = feature_bit(8); /* 0x00000100 CMPXCHG8B Instruction */
75 const APIC = feature_bit(9); /* 0x00000200 APIC On-Chip */
76 const SEP = feature_bit(11); /* 0x00000800 SYSENTER/SYSEXIT Instructions */
77 const MTRR = feature_bit(12); /* 0x00001000 Memory Type Range Registers */
78 const PGE = feature_bit(13); /* 0x00002000 Page Global Bit */
79 const MCA = feature_bit(14); /* 0x00004000 Machine Check Architecture */
80 const CMOV = feature_bit(15); /* 0x00008000 Conditional Move Instructions */
81 const PAT = feature_bit(16); /* 0x00010000 Page Attribute Table */
82 const PSE36 = feature_bit(17); /* 0x00020000 36-Bit Page Size Extension */
83 const PSN = feature_bit(18); /* 0x00040000 Processor Serial Number */
84 const CLFSH = feature_bit(19); /* 0x00080000 CLFLUSH Instruction */
85 const DS = feature_bit(21); /* 0x00200000 Debug Store */
86 const ACPI = feature_bit(22); /* 0x00400000 Thermal Monitor and Software Controlled Clock Facilities */
87 const MMX = feature_bit(23); /* 0x00800000 Intel MMX Technology */
88 const FXSR = feature_bit(24); /* 0x01000000 FXSAVE and FXRSTOR Instructions */
89 const SSE = feature_bit(25); /* 0x02000000 Streaming SIMD Extensions */
90 const SSE2 = feature_bit(26); /* 0x04000000 Streaming SIMD Extensions 2 */
91 const SS = feature_bit(27); /* 0x08000000 Self Snoop */
92 const HTT = feature_bit(28); /* 0x10000000 Max APIC IDs reserved field is Valid */
93 const TM = feature_bit(29); /* 0x20000000 Thermal Monitor */
94 const PBE = feature_bit(31); /* 0x80000000 Pending Break Enable */
95 }
96 }
97 /*
98 * Intel SDM Vol. 2A: Table 3-8. Information Returned by CPUID Instruction
99 * Extended Function CPUID Information
100 * Features for CPUID with EAX=80000001h stored in ECX
101 */
102 bitflags! {
103 #[derive(Copy, Clone, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
104 #[repr(transparent)]
105 pub struct Feature80000001Ecx: u32 {
106 const LAHF = feature_bit(0); /* 0x00000001 LAHF/SAHF Instructions */
107 const ABM = feature_bit(5); /* 0x00000020 Advanced bit manipulation (lzcnt and popcnt) */
108 const PREFETCHW = feature_bit(8); /* 0x00000100 PREFETCH/PREFETCHW instructions */
109 }
110 }
111
112 /*
113 * Intel SDM Vol. 2A: Table 3-8. Information Returned by CPUID Instruction
114 * Extended Function CPUID Information
115 * Features for CPUID with EAX=80000001h stored in EDX
116 */
117 bitflags! {
118 #[derive(Copy, Clone, Debug, Eq, Hash, Ord, PartialEq, PartialOrd)]
119 #[repr(transparent)]
120 pub struct Feature80000001Edx: u32 {
121 const SYSCALL = feature_bit(11); /* 0x00000800 SYSCALL/SYSRET Instructions */
122 const NX = feature_bit(20); /* 0x00100000 No-Execute Bit */
123 const PDPE1GB = feature_bit(26); /* 0x04000000 Gibibyte pages */
124 const RDTSCP = feature_bit(27); /* 0x08000000 RDTSCP Instruction */
125 const EM64T = feature_bit(29); /* 0x20000000 Long Mode */
126 }
127 }
128