1 // Copyright 2020 The ChromiumOS Authors 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 // This list of MSRs comes from HAXM here: 6 // https://github.com/intel/haxm/blob/v7.6.1/core/include/ia32_defs.h#L99 7 8 pub const IA32_P5_MC_ADDR: u32 = 0x0; 9 pub const IA32_P5_MC_TYPE: u32 = 0x1; 10 pub const IA32_TSC: u32 = 0x10; 11 pub const IA32_PLATFORM_ID: u32 = 0x17; 12 pub const IA32_APIC_BASE: u32 = 0x1b; 13 pub const IA32_EBC_HARD_POWERON: u32 = 0x2a; 14 pub const IA32_EBC_SOFT_POWERON: u32 = 0x2b; 15 pub const IA32_EBC_FREQUENCY_ID: u32 = 0x2c; 16 pub const IA32_FEATURE_CONTROL: u32 = 0x3a; 17 pub const IA32_THERM_DIODE_OFFSET: u32 = 0x3f; 18 pub const IA32_BIOS_UPDT_TRIG: u32 = 0x79; 19 pub const IA32_BIOS_SIGN_ID: u32 = 0x8b; 20 pub const IA32_SMM_MONITOR_CTL: u32 = 0x9b; 21 pub const IA32_PMC0: u32 = 0xc1; 22 pub const IA32_PMC1: u32 = 0xc2; 23 pub const IA32_PMC2: u32 = 0xc3; 24 pub const IA32_PMC3: u32 = 0xc4; 25 pub const IA32_FSB_FREQ: u32 = 0xcd; 26 pub const IA32_MPERF: u32 = 0xe7; 27 pub const IA32_APERF: u32 = 0xe8; 28 pub const IA32_TEMP_TARGET: u32 = 0xee; 29 pub const IA32_MTRRCAP: u32 = 0xfe; 30 pub const IA32_BBL_CR_CTL3: u32 = 0x11e; 31 pub const IA32_SYSENTER_CS: u32 = 0x174; 32 pub const IA32_SYSENTER_ESP: u32 = 0x175; 33 pub const IA32_SYSENTER_EIP: u32 = 0x176; 34 pub const IA32_MCG_CAP: u32 = 0x179; 35 pub const IA32_MCG_STATUS: u32 = 0x17a; 36 pub const IA32_MCG_CTL: u32 = 0x17b; 37 pub const IA32_PERFEVTSEL0: u32 = 0x186; 38 pub const IA32_PERFEVTSEL1: u32 = 0x187; 39 pub const IA32_PERFEVTSEL2: u32 = 0x188; 40 pub const IA32_PERFEVTSEL3: u32 = 0x189; 41 pub const IA32_PERF_CTL: u32 = 0x199; 42 pub const IA32_MISC_ENABLE: u32 = 0x1a0; 43 pub const IA32_DEBUGCTL: u32 = 0x1d9; 44 pub const IA32_MTRR_PHYSBASE0: u32 = 0x200; 45 pub const IA32_MTRR_PHYSMASK0: u32 = 0x201; 46 pub const IA32_MTRR_PHYSBASE1: u32 = 0x202; 47 pub const IA32_MTRR_PHYSMASK1: u32 = 0x203; 48 pub const IA32_MTRR_PHYSBASE2: u32 = 0x204; 49 pub const IA32_MTRR_PHYSMASK2: u32 = 0x205; 50 pub const IA32_MTRR_PHYSBASE3: u32 = 0x206; 51 pub const IA32_MTRR_PHYSMASK3: u32 = 0x207; 52 pub const IA32_MTRR_PHYSBASE4: u32 = 0x208; 53 pub const IA32_MTRR_PHYSMASK4: u32 = 0x209; 54 pub const IA32_MTRR_PHYSBASE5: u32 = 0x20a; 55 pub const IA32_MTRR_PHYSMASK5: u32 = 0x20b; 56 pub const IA32_MTRR_PHYSBASE6: u32 = 0x20c; 57 pub const IA32_MTRR_PHYSMASK6: u32 = 0x20d; 58 pub const IA32_MTRR_PHYSBASE7: u32 = 0x20e; 59 pub const IA32_MTRR_PHYSMASK7: u32 = 0x20f; 60 pub const IA32_MTRR_PHYSBASE8: u32 = 0x210; 61 pub const IA32_MTRR_PHYSMASK8: u32 = 0x211; 62 pub const IA32_MTRR_PHYSBASE9: u32 = 0x212; 63 pub const IA32_MTRR_PHYSMASK9: u32 = 0x213; 64 pub const MTRRFIX64K_00000: u32 = 0x250; 65 pub const MTRRFIX16K_80000: u32 = 0x258; 66 pub const MTRRFIX16K_A0000: u32 = 0x259; 67 pub const MTRRFIX4K_C0000: u32 = 0x268; 68 pub const MTRRFIX4K_F8000: u32 = 0x26f; 69 pub const IA32_CR_PAT: u32 = 0x277; 70 pub const IA32_MC0_CTL2: u32 = 0x280; 71 pub const IA32_MC1_CTL2: u32 = 0x281; 72 pub const IA32_MC2_CTL2: u32 = 0x282; 73 pub const IA32_MC3_CTL2: u32 = 0x283; 74 pub const IA32_MC4_CTL2: u32 = 0x284; 75 pub const IA32_MC5_CTL2: u32 = 0x285; 76 pub const IA32_MC6_CTL2: u32 = 0x286; 77 pub const IA32_MC7_CTL2: u32 = 0x287; 78 pub const IA32_MC8_CTL2: u32 = 0x288; 79 pub const IA32_MTRR_DEF_TYPE: u32 = 0x2ff; 80 pub const MSR_BPU_COUNTER0: u32 = 0x300; 81 pub const IA32_FIXED_CTR0: u32 = 0x309; 82 pub const IA32_FIXED_CTR1: u32 = 0x30a; 83 pub const IA32_FIXED_CTR2: u32 = 0x30b; 84 pub const IA32_PERF_CAPABILITIES: u32 = 0x345; 85 pub const MSR_PEBS_MATRIX_VERT: u32 = 0x3f2; 86 pub const IA32_FIXED_CTR_CTRL: u32 = 0x38d; 87 pub const IA32_PERF_GLOBAL_STATUS: u32 = 0x38e; 88 pub const IA32_PERF_GLOBAL_CTRL: u32 = 0x38f; 89 pub const IA32_PERF_GLOBAL_OVF_CTRL: u32 = 0x390; 90 pub const IA32_MC0_CTL: u32 = 0x400; 91 pub const IA32_MC0_STATUS: u32 = 0x401; 92 pub const IA32_MC0_ADDR: u32 = 0x402; 93 pub const IA32_MC0_MISC: u32 = 0x403; 94 pub const IA32_CPUID_FEATURE_MASK: u32 = 0x478; 95 pub const IA32_VMX_BASIC: u32 = 0x480; 96 pub const IA32_VMX_PINBASED_CTLS: u32 = 0x481; 97 pub const IA32_VMX_PROCBASED_CTLS: u32 = 0x482; 98 pub const IA32_VMX_EXIT_CTLS: u32 = 0x483; 99 pub const IA32_VMX_ENTRY_CTLS: u32 = 0x484; 100 pub const IA32_VMX_MISC: u32 = 0x485; 101 pub const IA32_VMX_CR0_FIXED0: u32 = 0x486; 102 pub const IA32_VMX_CR0_FIXED1: u32 = 0x487; 103 pub const IA32_VMX_CR4_FIXED0: u32 = 0x488; 104 pub const IA32_VMX_CR4_FIXED1: u32 = 0x489; 105 pub const IA32_VMX_VMCS_ENUM: u32 = 0x48a; 106 pub const IA32_VMX_SECONDARY_CTLS: u32 = 0x48b; 107 pub const IA32_VMX_EPT_VPID_CAP: u32 = 0x48c; 108 pub const IA32_VMX_TRUE_PINBASED_CTLS: u32 = 0x48d; 109 pub const IA32_VMX_TRUE_PROCBASED_CTLS: u32 = 0x48e; 110 pub const IA32_VMX_TRUE_EXIT_CTLS: u32 = 0x48f; 111 pub const IA32_VMX_TRUE_ENTRY_CTLS: u32 = 0x490; 112 pub const IA32_EFER: u32 = 0xc0000080; 113 pub const IA32_STAR: u32 = 0xc0000081; 114 pub const IA32_LSTAR: u32 = 0xc0000082; 115 pub const IA32_CSTAR: u32 = 0xc0000083; 116 pub const IA32_SF_MASK: u32 = 0xc0000084; 117 pub const IA32_FS_BASE: u32 = 0xc0000100; 118 pub const IA32_GS_BASE: u32 = 0xc0000101; 119 pub const IA32_KERNEL_GS_BASE: u32 = 0xc0000102; 120 pub const IA32_TSC_AUX: u32 = 0xc0000103; 121