1 #include <stdio.h>
2 #include <string.h>
3
4 #include "internal.h"
5
6 #define SERDES_OFFSET 32
7
8 /* Macros and dump functions for the 16-bit mv88e6xxx per-port registers */
9
10 #define REG(_reg, _name, _val) \
11 printf("%.02u: %-38.38s 0x%.4x\n", _reg, _name, _val)
12
13 #define FIELD(_name, _fmt, ...) \
14 printf(" %-36.36s " _fmt "\n", _name, ##__VA_ARGS__)
15
16 #define FIELD_BITMAP(_name, _val) \
17 FIELD(_name, "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", \
18 ((_val) & 0x0001) ? "0 " : "", \
19 ((_val) & 0x0002) ? "1 " : "", \
20 ((_val) & 0x0004) ? "2 " : "", \
21 ((_val) & 0x0008) ? "3 " : "", \
22 ((_val) & 0x0010) ? "4 " : "", \
23 ((_val) & 0x0020) ? "5 " : "", \
24 ((_val) & 0x0040) ? "6 " : "", \
25 ((_val) & 0x0080) ? "7 " : "", \
26 ((_val) & 0x0100) ? "8 " : "", \
27 ((_val) & 0x0200) ? "9 " : "", \
28 ((_val) & 0x0400) ? "10 " : "", \
29 ((_val) & 0x0800) ? "11 " : "", \
30 ((_val) & 0x1000) ? "12 " : "", \
31 ((_val) & 0x2000) ? "13 " : "", \
32 ((_val) & 0x4000) ? "14 " : "", \
33 ((_val) & 0x8000) ? "15 " : "")
34
dsa_mv88e6161(int reg,u16 val)35 static void dsa_mv88e6161(int reg, u16 val)
36 {
37 switch (reg) {
38 case 0:
39 REG(reg, "Port Status", val);
40 FIELD("Pause Enabled", "%u", !!(val & 0x8000));
41 FIELD("My Pause", "%u", !!(val & 0x4000));
42 FIELD("Half-duplex Flow Control", "%u", !!(val & 0x2000));
43 FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000));
44 FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down");
45 FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half");
46 FIELD("Speed", "%s",
47 (val & 0x0300) == 0x0000 ? "10 Mbps" :
48 (val & 0x0300) == 0x0100 ? "100 Mbps" :
49 (val & 0x0300) == 0x0200 ? "1000 Mbps" :
50 (val & 0x0300) == 0x0300 ? "Reserved" : "?");
51 FIELD("Auto-Media Detect Disable", "%u", !!(val & 0x0040));
52 FIELD("Transmitter Paused", "%u", !!(val & 0x0020));
53 FIELD("Flow Control", "%u", !!(val & 0x0010));
54 FIELD("Config Duplex", "%s", val & 0x0008 ? "Full" : "Half");
55 FIELD("Config Mode", "0x%x", val & 0x0007);
56 break;
57 case 1:
58 REG(reg, "PCS Control", val);
59 FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080));
60 FIELD("Force Flow Control", "%u", !!(val & 0x0040));
61 FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down");
62 FIELD("Force Link", "%u", !!(val & 0x0010));
63 FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half");
64 FIELD("Force Duplex", "%u", !!(val & 0x0004));
65 FIELD("Force Speed", "%s",
66 (val & 0x0003) == 0x0000 ? "10 Mbps" :
67 (val & 0x0003) == 0x0001 ? "100 Mbps" :
68 (val & 0x0003) == 0x0002 ? "1000 Mbps" :
69 (val & 0x0003) == 0x0003 ? "Not forced" : "?");
70 break;
71 case 2:
72 REG(reg, "Jamming Control", val);
73 break;
74 case 3:
75 REG(reg, "Switch Identifier", val);
76 break;
77 case 4:
78 REG(reg, "Port Control", val);
79 FIELD("Source Address Filtering controls", "%s",
80 (val & 0xc000) == 0x0000 ? "Disabled" :
81 (val & 0xc000) == 0x4000 ? "Drop On Lock" :
82 (val & 0xc000) == 0x8000 ? "Drop On Unlock" :
83 (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?");
84 FIELD("Egress Mode", "%s",
85 (val & 0x3000) == 0x0000 ? "Unmodified" :
86 (val & 0x3000) == 0x1000 ? "Untagged" :
87 (val & 0x3000) == 0x2000 ? "Tagged" :
88 (val & 0x3000) == 0x3000 ? "Reserved" : "?");
89 FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800));
90 FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400));
91 FIELD("Frame Mode", "%s",
92 (val & 0x0300) == 0x0000 ? "Normal" :
93 (val & 0x0300) == 0x0100 ? "DSA" :
94 (val & 0x0300) == 0x0200 ? "Provider" :
95 (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?");
96 FIELD("VLAN Tunnel", "%u", !!(val & 0x0080));
97 FIELD("TagIfBoth", "%u", !!(val & 0x0040));
98 FIELD("Initial Priority assignment", "%s",
99 (val & 0x0030) == 0x0000 ? "Defaults" :
100 (val & 0x0030) == 0x0010 ? "Tag Priority" :
101 (val & 0x0030) == 0x0020 ? "IP Priority" :
102 (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?");
103 FIELD("Egress Flooding mode", "%s",
104 (val & 0x000c) == 0x0000 ? "No unknown DA" :
105 (val & 0x000c) == 0x0004 ? "No unknown multicast DA" :
106 (val & 0x000c) == 0x0008 ? "No unknown unicast DA" :
107 (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?");
108 FIELD("Port State", "%s",
109 (val & 0x0003) == 0x0000 ? "Disabled" :
110 (val & 0x0003) == 0x0001 ? "Blocking/Listening" :
111 (val & 0x0003) == 0x0002 ? "Learning" :
112 (val & 0x0003) == 0x0003 ? "Forwarding" : "?");
113 break;
114 case 5:
115 REG(reg, "Port Control 1", val);
116 FIELD("Message Port", "%u", !!(val & 0x8000));
117 FIELD("Trunk Port", "%u", !!(val & 0x4000));
118 FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8);
119 FIELD("FID[5:4]", "0x%.2x", (val & 0x0003) << 4);
120 break;
121 case 6:
122 REG(reg, "Port Base VLAN Map (Header)", val);
123 FIELD("FID[3:0]", "0x%.2x", (val & 0xf000) >> 12);
124 FIELD_BITMAP("VLANTable", val & 0x003f);
125 break;
126 case 7:
127 REG(reg, "Default VLAN ID & Priority", val);
128 FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13);
129 FIELD("Force to use Default VID", "%u", !!(val & 0x1000));
130 FIELD("Default VLAN Identifier", "%u", val & 0x0fff);
131 break;
132 case 8:
133 REG(reg, "Port Control 2", val);
134 FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000));
135 FIELD("Jumbo Mode", "%s",
136 (val & 0x3000) == 0x0000 ? "1522" :
137 (val & 0x3000) == 0x1000 ? "2048" :
138 (val & 0x3000) == 0x2000 ? "10240" :
139 (val & 0x3000) == 0x3000 ? "Reserved" : "?");
140 FIELD("802.1QMode", "%s",
141 (val & 0x0c00) == 0x0000 ? "Disabled" :
142 (val & 0x0c00) == 0x0400 ? "Fallback" :
143 (val & 0x0c00) == 0x0800 ? "Check" :
144 (val & 0x0c00) == 0x0c00 ? "Secure" : "?");
145 FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200));
146 FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100));
147 FIELD("Map using DA hits", "%u", !!(val & 0x0080));
148 FIELD("ARP Mirror enable", "%u", !!(val & 0x0040));
149 FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020));
150 FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010));
151 break;
152 case 9:
153 REG(reg, "Egress Rate Control", val);
154 break;
155 case 10:
156 REG(reg, "Egress Rate Control 2", val);
157 break;
158 case 11:
159 REG(reg, "Port Association Vector", val);
160 break;
161 case 12:
162 REG(reg, "Port ATU Control", val);
163 break;
164 case 13:
165 REG(reg, "Priority Override", val);
166 break;
167 case 15:
168 REG(reg, "PortEType", val);
169 break;
170 case 16:
171 REG(reg, "InDiscardsLo Frame Counter", val);
172 break;
173 case 17:
174 REG(reg, "InDiscardsHi Frame Counter", val);
175 break;
176 case 18:
177 REG(reg, "InFiltered Frame Counter", val);
178 break;
179 case 19:
180 REG(reg, "OutFiltered Frame Counter", val);
181 break;
182 case 24:
183 REG(reg, "Tag Remap 0-3", val);
184 break;
185 case 25:
186 REG(reg, "Tag Remap 4-7", val);
187 break;
188 case 27:
189 REG(reg, "Queue Counters", val);
190 break;
191 default:
192 REG(reg, "Reserved", val);
193 break;
194 }
195 }
196
dsa_mv88e6185(int reg,u16 val)197 static void dsa_mv88e6185(int reg, u16 val)
198 {
199 switch (reg) {
200 case 0:
201 REG(reg, "Port Status", val);
202 break;
203 case 1:
204 REG(reg, "PCS Control", val);
205 break;
206 case 3:
207 REG(reg, "Switch Identifier", val);
208 break;
209 case 4:
210 REG(reg, "Port Control", val);
211 break;
212 case 5:
213 REG(reg, "Port Control 1", val);
214 break;
215 case 6:
216 REG(reg, "Port Base VLAN Map (Header)", val);
217 break;
218 case 7:
219 REG(reg, "Default VLAN ID & Priority", val);
220 break;
221 case 8:
222 REG(reg, "Port Control 2", val);
223 break;
224 case 9:
225 REG(reg, "Rate Control", val);
226 break;
227 case 10:
228 REG(reg, "Rate Control 2", val);
229 break;
230 case 11:
231 REG(reg, "Port Association Vector", val);
232 break;
233 case 16:
234 REG(reg, "InDiscardsLo Frame Counter", val);
235 break;
236 case 17:
237 REG(reg, "InDiscardsHi Frame Counter", val);
238 break;
239 case 18:
240 REG(reg, "InFiltered Frame Counter", val);
241 break;
242 case 19:
243 REG(reg, "OutFiltered Frame Counter", val);
244 break;
245 case 24:
246 REG(reg, "Tag Remap 0-3", val);
247 break;
248 case 25:
249 REG(reg, "Tag Remap 4-7", val);
250 break;
251 default:
252 REG(reg, "Reserved", val);
253 break;
254 }
255 };
256
dsa_mv88e6352(int reg,u16 val)257 static void dsa_mv88e6352(int reg, u16 val)
258 {
259 switch (reg) {
260 case 0:
261 REG(reg, "Port Status", val);
262 FIELD("Pause Enabled", "%u", !!(val & 0x8000));
263 FIELD("My Pause", "%u", !!(val & 0x4000));
264 FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000));
265 FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down");
266 FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half");
267 FIELD("Speed", "%s",
268 (val & 0x0300) == 0x0000 ? "10 Mbps" :
269 (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" :
270 (val & 0x0300) == 0x0200 ? "1000 Mbps" :
271 (val & 0x0300) == 0x0300 ? "Reserved" : "?");
272 FIELD("EEE Enabled", "%u", !!(val & 0x0040));
273 FIELD("Transmitter Paused", "%u", !!(val & 0x0020));
274 FIELD("Flow Control", "%u", !!(val & 0x0010));
275 FIELD("Config Mode", "0x%x", val & 0x000f);
276 break;
277 case 1:
278 REG(reg, "Physical Control", val);
279 FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default");
280 FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default");
281 FIELD("200 BASE Mode", "%s", val & 0x1000 ? "200" : "100");
282 FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080));
283 FIELD("Force Flow Control", "%u", !!(val & 0x0040));
284 FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down");
285 FIELD("Force Link", "%u", !!(val & 0x0010));
286 FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half");
287 FIELD("Force Duplex", "%u", !!(val & 0x0004));
288 FIELD("Force Speed", "%s",
289 (val & 0x0003) == 0x0000 ? "10 Mbps" :
290 (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" :
291 (val & 0x0003) == 0x0002 ? "1000 Mbps" :
292 (val & 0x0003) == 0x0003 ? "Not forced" : "?");
293 break;
294 case 2:
295 REG(reg, "Jamming Control", val);
296 break;
297 case 3:
298 REG(reg, "Switch Identifier", val);
299 break;
300 case 4:
301 REG(reg, "Port Control", val);
302 FIELD("Source Address Filtering controls", "%s",
303 (val & 0xc000) == 0x0000 ? "Disabled" :
304 (val & 0xc000) == 0x4000 ? "Drop On Lock" :
305 (val & 0xc000) == 0x8000 ? "Drop On Unlock" :
306 (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?");
307 FIELD("Egress Mode", "%s",
308 (val & 0x3000) == 0x0000 ? "Unmodified" :
309 (val & 0x3000) == 0x1000 ? "Untagged" :
310 (val & 0x3000) == 0x2000 ? "Tagged" :
311 (val & 0x3000) == 0x3000 ? "Reserved" : "?");
312 FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800));
313 FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400));
314 FIELD("Frame Mode", "%s",
315 (val & 0x0300) == 0x0000 ? "Normal" :
316 (val & 0x0300) == 0x0100 ? "DSA" :
317 (val & 0x0300) == 0x0200 ? "Provider" :
318 (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?");
319 FIELD("VLAN Tunnel", "%u", !!(val & 0x0080));
320 FIELD("TagIfBoth", "%u", !!(val & 0x0040));
321 FIELD("Initial Priority assignment", "%s",
322 (val & 0x0030) == 0x0000 ? "Defaults" :
323 (val & 0x0030) == 0x0010 ? "Tag Priority" :
324 (val & 0x0030) == 0x0020 ? "IP Priority" :
325 (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?");
326 FIELD("Egress Flooding mode", "%s",
327 (val & 0x000c) == 0x0000 ? "No unknown DA" :
328 (val & 0x000c) == 0x0004 ? "No unknown multicast DA" :
329 (val & 0x000c) == 0x0008 ? "No unknown unicast DA" :
330 (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?");
331 FIELD("Port State", "%s",
332 (val & 0x0003) == 0x0000 ? "Disabled" :
333 (val & 0x0003) == 0x0001 ? "Blocking/Listening" :
334 (val & 0x0003) == 0x0002 ? "Learning" :
335 (val & 0x0003) == 0x0003 ? "Forwarding" : "?");
336 break;
337 case 5:
338 REG(reg, "Port Control 1", val);
339 FIELD("Message Port", "%u", !!(val & 0x8000));
340 FIELD("Trunk Port", "%u", !!(val & 0x4000));
341 FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8);
342 FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4);
343 break;
344 case 6:
345 REG(reg, "Port Base VLAN Map (Header)", val);
346 FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12);
347 FIELD_BITMAP("VLANTable", val & 0x007f);
348 break;
349 case 7:
350 REG(reg, "Default VLAN ID & Priority", val);
351 FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13);
352 FIELD("Force to use Default VID", "%u", !!(val & 0x1000));
353 FIELD("Default VLAN Identifier", "%u", val & 0x0fff);
354 break;
355 case 8:
356 REG(reg, "Port Control 2", val);
357 FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000));
358 FIELD("Jumbo Mode", "%s",
359 (val & 0x3000) == 0x0000 ? "1522" :
360 (val & 0x3000) == 0x1000 ? "2048" :
361 (val & 0x3000) == 0x2000 ? "10240" :
362 (val & 0x3000) == 0x3000 ? "Reserved" : "?");
363 FIELD("802.1QMode", "%s",
364 (val & 0x0c00) == 0x0000 ? "Disabled" :
365 (val & 0x0c00) == 0x0400 ? "Fallback" :
366 (val & 0x0c00) == 0x0800 ? "Check" :
367 (val & 0x0c00) == 0x0c00 ? "Secure" : "?");
368 FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200));
369 FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100));
370 FIELD("Map using DA hits", "%u", !!(val & 0x0080));
371 FIELD("ARP Mirror enable", "%u", !!(val & 0x0040));
372 FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020));
373 FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010));
374 FIELD("Use Default Queue Priority", "%u", !!(val & 0x0008));
375 FIELD("Default Queue Priority", "0x%x", (val & 0x0006) >> 1);
376 break;
377 case 9:
378 REG(reg, "Egress Rate Control", val);
379 break;
380 case 10:
381 REG(reg, "Egress Rate Control 2", val);
382 break;
383 case 11:
384 REG(reg, "Port Association Vector", val);
385 break;
386 case 12:
387 REG(reg, "Port ATU Control", val);
388 break;
389 case 13:
390 REG(reg, "Override", val);
391 break;
392 case 14:
393 REG(reg, "Policy Control", val);
394 break;
395 case 15:
396 REG(reg, "Port Ether Type", val);
397 break;
398 case 16:
399 REG(reg, "InDiscardsLo Frame Counter", val);
400 break;
401 case 17:
402 REG(reg, "InDiscardsHi Frame Counter", val);
403 break;
404 case 18:
405 REG(reg, "InFiltered/TcamCtr Frame Counter", val);
406 break;
407 case 19:
408 REG(reg, "Rx Frame Counter", val);
409 break;
410 case 20 ... 21:
411 REG(reg, "Reserved", val);
412 break;
413 case 22:
414 REG(reg, "LED Control", val);
415 break;
416 case 23:
417 REG(reg, "Reserved", val);
418 break;
419 case 24:
420 REG(reg, "Tag Remap 0-3", val);
421 break;
422 case 25:
423 REG(reg, "Tag Remap 4-7", val);
424 break;
425 case 26:
426 REG(reg, "Reserved", val);
427 break;
428 case 27:
429 REG(reg, "Queue Counters", val);
430 break;
431 case 28 ... 31:
432 REG(reg, "Reserved", val);
433 break;
434 case SERDES_OFFSET + 0:
435 REG(reg - SERDES_OFFSET, "Fiber Control", val);
436 FIELD("Fiber Reset", "%u", !!(val & 0x8000));
437 FIELD("Loopback", "%u", !!(val & 0x4000));
438 FIELD("Speed", "%s",
439 (val & (0x2000 | 0x0040)) == 0x0000 ? "10 Mbps" :
440 (val & (0x2000 | 0x0040)) == 0x2000 ? "100 Mbps" :
441 (val & (0x2000 | 0x0040)) == 0x0040 ? "1000 Mbps" :
442 (val & (0x2000 | 0x0040)) == (0x2000 | 0x0040) ?
443 "Reserved" : "?");
444 FIELD("Autoneg Enable", "%u", !!(val & 0x1000));
445 FIELD("Power down", "%u", !!(val & 0x0800));
446 FIELD("Isolate", "%u", !!(val & 0x0400));
447 FIELD("Restart Autoneg", "%u", !!(val & 0x0200));
448 FIELD("Duplex", "%s", val & 0x0100 ? "Full" : "Half");
449 break;
450 case SERDES_OFFSET + 1:
451 REG(reg - SERDES_OFFSET, "Fiber Status", val);
452 FIELD("100Base-X FD", "%u", !!(val & 0x4000));
453 FIELD("100Base-X HD", "%u", !!(val & 0x2000));
454 FIELD("Autoneg Complete", "%u", !!(val & 0x0020));
455 FIELD("Remote Fault", "%u", !!(val & 0x0010));
456 FIELD("Autoneg Ability", "%u", !!(val & 0x0008));
457 FIELD("Link Status", "%s", val & 0x0004 ? "Up" : "Down");
458 break;
459 case SERDES_OFFSET + 2:
460 REG(reg - SERDES_OFFSET, "PHY ID 1", val);
461 break;
462 case SERDES_OFFSET + 3:
463 REG(reg - SERDES_OFFSET, "PHY ID 2", val);
464 break;
465 case SERDES_OFFSET + 4:
466 REG(reg - SERDES_OFFSET, "Fiber Autoneg Advertisement", val);
467 FIELD("Remote Fault", "%s",
468 (val & 0x3000) == 0x0000 ? "No error, link OK" :
469 (val & 0x3000) == 0x1000 ? "Link failure" :
470 (val & 0x3000) == 0x2000 ? "Offline" :
471 (val & 0x3000) == 0x3000 ? "Autoneg Error" : "?");
472 FIELD("Pause", "%s",
473 (val & 0x0180) == 0x0000 ? "No Pause" :
474 (val & 0x0180) == 0x0080 ? "Symmetric Pause" :
475 (val & 0x0180) == 0x0100 ? "Asymmetric Pause" :
476 (val & 0x0180) == 0x0180 ? "Symmetric & Asymmetric Pause" :
477 "?");
478 FIELD("1000BaseX HD", "%u", !!(val & 0x0040));
479 FIELD("1000BaseX FD", "%u", !!(val & 0x0020));
480 break;
481 case SERDES_OFFSET + 5:
482 REG(reg - SERDES_OFFSET, "Fiber Link Autoneg Ability", val);
483 FIELD("Acknowledge", "%u", !!(val & 0x4000));
484 FIELD("Remote Fault", "%s",
485 (val & 0x3000) == 0x0000 ? "No error, link OK" :
486 (val & 0x3000) == 0x1000 ? "Link failure" :
487 (val & 0x3000) == 0x2000 ? "Offline" :
488 (val & 0x3000) == 0x3000 ? "Autoneg Error" : "?");
489 FIELD("Pause", "%s",
490 (val & 0x0180) == 0x0000 ? "No Pause" :
491 (val & 0x0180) == 0x0080 ? "Symmetric Pause" :
492 (val & 0x0180) == 0x0100 ? "Asymmetric Pause" :
493 (val & 0x0180) == 0x0180 ? "Symmetric & Asymmetric Pause" :
494 "?");
495 FIELD("1000BaseX HD", "%u", !!(val & 0x0040));
496 FIELD("1000BaseX FD", "%u", !!(val & 0x0020));
497 break;
498 case SERDES_OFFSET + 6:
499 REG(reg - SERDES_OFFSET, "Fiber Autoneg Expansion", val);
500 FIELD("Link Partner Next Page Ability", "%u", !!(val & 0x0008));
501 FIELD("Page Received", "%u", !!(val & 0x0002));
502 FIELD("Link Partner Autoneg Ability", "%u", !!(val & 0x0001));
503 break;
504 case SERDES_OFFSET + 7:
505 REG(reg - SERDES_OFFSET, "Fiber Next Page Transmit", val);
506 break;
507 case SERDES_OFFSET + 8:
508 REG(reg - SERDES_OFFSET, "Fiber Link Partner Next Page", val);
509 break;
510 case SERDES_OFFSET + 9 ... SERDES_OFFSET + 14:
511 REG(reg - SERDES_OFFSET, "Reserved", val);
512 break;
513 case SERDES_OFFSET + 15:
514 REG(reg - SERDES_OFFSET, "Extended Status", val);
515 break;
516 case SERDES_OFFSET + 16:
517 REG(reg - SERDES_OFFSET, "Fiber Specific Control", val);
518 FIELD("Fiber Transmit FIFO Depth", "%s",
519 (val & 0xc000) == 0x0000 ? "16 Bits" :
520 (val & 0xc000) == 0x4000 ? "24 Bits" :
521 (val & 0xc000) == 0x8000 ? "32 Bits" :
522 (val & 0xc000) == 0xc000 ? "40 Bits" : "?");
523 FIELD("SERDES Loopback", "%u", !!(val & 0x1000));
524 FIELD("Force Link Good", "%u", !!(val & 0x0400));
525 FIELD("MAC Interface Power Down", "%u", !!(val & 0x0008));
526 FIELD("Mode", "%s",
527 (val & 0x0003) == 0x0000 ? "100BaseFX" :
528 (val & 0x0003) == 0x0001 ? "1000BaseX" :
529 (val & 0x0003) == 0x0002 ? "SGMII System" :
530 (val & 0x0003) == 0x0003 ? "SGMII Media" : "?");
531 break;
532 case SERDES_OFFSET + 17:
533 REG(reg - SERDES_OFFSET, "Fiber Specific Status", val);
534 FIELD("Speed", "%s",
535 (val & 0xc000) == 0x0000 ? "10 Mbps" :
536 (val & 0xc000) == 0x4000 ? "100 Mbps" :
537 (val & 0xc000) == 0x8000 ? "1000 Mbps" :
538 (val & 0xc000) == 0xc000 ? "Reserved" : "?");
539 FIELD("Duplex", "%s", val & 0x2000 ? "Full" : "Half");
540 FIELD("Page Received", "%u", !!(val & 0x1000));
541 FIELD("Speed/Duplex Resolved", "%u", !!(val & 0x0800));
542 FIELD("Link", "%s", val & 0x0400 ? "Up" : "Down");
543 FIELD("Sync", "%u", !!(val & 0x0020));
544 FIELD("Energy Detect", "%s", val & 0x010 ? "False" : "True");
545 FIELD("Transmit Pause", "%u", !!(val & 0x0008));
546 FIELD("Receive Pause", "%u", !!(val & 0x00004));
547 break;
548 case SERDES_OFFSET + 18:
549 REG(reg - SERDES_OFFSET, "Fiber Interrupt Enable", val);
550 FIELD("Speed Changed", "%u", !!(val & 0x4000));
551 FIELD("Duplex Changed", "%u", !!(val & 0x2000));
552 FIELD("Page Received", "%u", !!(val & 0x1000));
553 FIELD("Autoneg Complete", "%u", !!(val & 0x0800));
554 FIELD("Link Status Change", "%u", !!(val & 0x0400));
555 FIELD("Symbol Error", "%u", !!(val & 0x0200));
556 FIELD("False Carrier", "%u", !!(val & 0x0100));
557 FIELD("Energy Detect", "%u", !!(val & 0x0010));
558 break;
559 case SERDES_OFFSET + 19:
560 REG(reg - SERDES_OFFSET, "Fiber Interrupt Status", val);
561 FIELD("Speed Changed", "%u", !!(val & 0x4000));
562 FIELD("Duplex Changed", "%u", !!(val & 0x2000));
563 FIELD("Page Received", "%u", !!(val & 0x1000));
564 FIELD("Autoneg Complete", "%u", !!(val & 0x0800));
565 FIELD("Link Status Change", "%u", !!(val & 0x0400));
566 FIELD("Symbol Error", "%u", !!(val & 0x0200));
567 FIELD("False Carrier", "%u", !!(val & 0x0100));
568 FIELD("Energy Detect", "%u", !!(val & 0x0010));
569 break;
570 case SERDES_OFFSET + 20:
571 REG(reg - SERDES_OFFSET, "Reserved", val);
572 break;
573 case SERDES_OFFSET + 21:
574 REG(reg - SERDES_OFFSET, "Fiber Receive Error Counter", val);
575 break;
576 case SERDES_OFFSET + 22:
577 REG(reg - SERDES_OFFSET, "Reserved", val);
578 break;
579 case SERDES_OFFSET + 23:
580 REG(reg - SERDES_OFFSET, "PRBS Control", val);
581 break;
582 case SERDES_OFFSET + 24:
583 REG(reg - SERDES_OFFSET, "PRBS Error Counter LSB", val);
584 break;
585 case SERDES_OFFSET + 25:
586 REG(reg - SERDES_OFFSET, "PRBS Error Counter MSB", val);
587 break;
588 case SERDES_OFFSET + 26:
589 REG(reg - SERDES_OFFSET, "Fiber Specific Control 2", val);
590 FIELD("1000BaseX Noise Filtering", "%u", !!(val & 0x4000));
591 FIELD("1000BaseFX Noise Filtering", "%u", !!(val & 0x2000));
592 FIELD("SERDES Autoneg Bypass Enable", "%u", !!(val & 0x0040));
593 FIELD("SERDES Autoneg Bypass Status", "%u", !!(val & 0x0020));
594 FIELD("Fiber Transmitter Disable", "%u", !!(val & 0x0008));
595 FIELD("SGMII/Fiber Output Amplitude", "%s",
596 (val & 0x0007) == 0x0000 ? "14mV" :
597 (val & 0x0007) == 0x0001 ? "112mV" :
598 (val & 0x0007) == 0x0002 ? "210mV" :
599 (val & 0x0007) == 0x0003 ? "308mV" :
600 (val & 0x0007) == 0x0004 ? "406mV" :
601 (val & 0x0007) == 0x0005 ? "504mV" :
602 (val & 0x0007) == 0x0006 ? "602mV" :
603 (val & 0x0007) == 0x0007 ? "700mV" : "?");
604 break;
605 default:
606 REG(reg - SERDES_OFFSET, "Reserved", val);
607 break;
608 }
609 };
610
dsa_mv88e6390(int reg,u16 val)611 static void dsa_mv88e6390(int reg, u16 val)
612 {
613 switch (reg) {
614 case 0:
615 REG(reg, "Port Status", val);
616 FIELD("Transmit Pause Enable bit", "%u", !!(val & 0x8000));
617 FIELD("Receive Pause Enable bit", "%u", !!(val & 0x4000));
618 FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000));
619 FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down");
620 FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half");
621 FIELD("Speed", "%s",
622 (val & 0x0300) == 0x0000 ? "10 Mbps" :
623 (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" :
624 (val & 0x0300) == 0x0200 ? "1000 Mbps" :
625 (val & 0x0300) == 0x0300 ? "10 Gb or 2500 Mbps" : "?");
626 FIELD("Duplex Fixed", "%u", !!(val & 0x0080));
627 FIELD("EEE Enabled", "%u", !!(val & 0x0040));
628 FIELD("Transmitter Paused", "%u", !!(val & 0x0020));
629 FIELD("Flow Control", "%u", !!(val & 0x0010));
630 FIELD("Config Mode", "0x%x", val & 0x000f);
631 break;
632 case 1:
633 REG(reg, "Physical Control", val);
634 FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default");
635 FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default");
636 FIELD("Force Speed", "%u", !!(val & 0x2000));
637 FIELD("Alternate Speed Mode", "%s", val & 0x1000 ? "Alternate" : "Normal");
638 FIELD("MII PHY Mode", "%s", val & 0x0800 ? "PHY" : "MAC");
639 FIELD("EEE force value", "%u", !!(val & 0x0200));
640 FIELD("Force EEE", "%u", !!(val & 0x0100));
641 FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down");
642 FIELD("Force Link", "%u", !!(val & 0x0010));
643 FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half");
644 FIELD("Force Duplex", "%u", !!(val & 0x0004));
645 FIELD("Force Speed", "%s",
646 (val & 0x0003) == 0x0000 ? "10 Mbps" :
647 (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" :
648 (val & 0x0003) == 0x0002 ? "1000 Mbps" :
649 (val & 0x0003) == 0x0003 ? "10 Gb or 2500 Mbps" : "?");
650 break;
651 case 2:
652 REG(reg, "Flow Control", val);
653 break;
654 case 3:
655 REG(reg, "Switch Identifier", val);
656 break;
657 case 4:
658 REG(reg, "Port Control", val);
659 FIELD("Source Address Filtering controls", "%s",
660 (val & 0xc000) == 0x0000 ? "Disabled" :
661 (val & 0xc000) == 0x4000 ? "Drop On Lock" :
662 (val & 0xc000) == 0x8000 ? "Drop On Unlock" :
663 (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?");
664 FIELD("Egress Mode", "%s",
665 (val & 0x3000) == 0x0000 ? "Unmodified" :
666 (val & 0x3000) == 0x1000 ? "Untagged" :
667 (val & 0x3000) == 0x2000 ? "Tagged" :
668 (val & 0x3000) == 0x3000 ? "Reserved" : "?");
669 FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800));
670 FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400));
671 FIELD("Frame Mode", "%s",
672 (val & 0x0300) == 0x0000 ? "Normal" :
673 (val & 0x0300) == 0x0100 ? "DSA" :
674 (val & 0x0300) == 0x0200 ? "Provider" :
675 (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?");
676 FIELD("VLAN Tunnel", "%u", !!(val & 0x0080));
677 FIELD("TagIfBoth", "%u", !!(val & 0x0040));
678 FIELD("Initial Priority assignment", "%s",
679 (val & 0x0030) == 0x0000 ? "Defaults" :
680 (val & 0x0030) == 0x0010 ? "Tag Priority" :
681 (val & 0x0030) == 0x0020 ? "IP Priority" :
682 (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?");
683 FIELD("Egress Flooding mode", "%s",
684 (val & 0x000c) == 0x0000 ? "No unknown DA" :
685 (val & 0x000c) == 0x0004 ? "No unknown multicast DA" :
686 (val & 0x000c) == 0x0008 ? "No unknown unicast DA" :
687 (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?");
688 FIELD("Port State", "%s",
689 (val & 0x0003) == 0x0000 ? "Disabled" :
690 (val & 0x0003) == 0x0001 ? "Blocking/Listening" :
691 (val & 0x0003) == 0x0002 ? "Learning" :
692 (val & 0x0003) == 0x0003 ? "Forwarding" : "?");
693 break;
694 case 5:
695 REG(reg, "Port Control 1", val);
696 FIELD("Message Port", "%u", !!(val & 0x8000));
697 FIELD("LAG Port", "%u", !!(val & 0x4000));
698 FIELD("VTU Page", "%u", !!(val & 0x2000));
699 FIELD("LAG ID", "%u", (val & 0x0f00) >> 8);
700 FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4);
701 break;
702 case 6:
703 REG(reg, "Port Base VLAN Map (Header)", val);
704 FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12);
705 FIELD("Force Mapping", "%u", !!(val & 0x0800));
706 FIELD_BITMAP("VLANTable", val & 0x007ff);
707 break;
708 case 7:
709 REG(reg, "Default VLAN ID & Priority", val);
710 FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13);
711 FIELD("Force to use Default VID", "%u", !!(val & 0x1000));
712 FIELD("Default VLAN Identifier", "%u", val & 0x0fff);
713 break;
714 case 8:
715 REG(reg, "Port Control 2", val);
716 FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000));
717 FIELD("Allow bad FCS", "%u", !!(val & 0x4000));
718 FIELD("Jumbo Mode", "%s",
719 (val & 0x3000) == 0x0000 ? "1522" :
720 (val & 0x3000) == 0x1000 ? "2048" :
721 (val & 0x3000) == 0x2000 ? "10240" :
722 (val & 0x3000) == 0x3000 ? "Reserved" : "?");
723 FIELD("802.1QMode", "%s",
724 (val & 0x0c00) == 0x0000 ? "Disabled" :
725 (val & 0x0c00) == 0x0400 ? "Fallback" :
726 (val & 0x0c00) == 0x0800 ? "Check" :
727 (val & 0x0c00) == 0x0c00 ? "Secure" : "?");
728 FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200));
729 FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100));
730 FIELD("Map using DA hits", "%u", !!(val & 0x0080));
731 FIELD("ARP Mirror enable", "%u", !!(val & 0x0040));
732 FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020));
733 FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010));
734 FIELD("Allow VID of Zero", "%u", !!(val & 0x0008));
735 FIELD("Default Queue Priority", "0x%x", val & 0x0007);
736 break;
737 case 9:
738 REG(reg, "Egress Rate Control", val);
739 break;
740 case 10:
741 REG(reg, "Egress Rate Control 2", val);
742 break;
743 case 11:
744 REG(reg, "Port Association Vector", val);
745 break;
746 case 12:
747 REG(reg, "Port ATU Control", val);
748 break;
749 case 13:
750 REG(reg, "Override", val);
751 break;
752 case 14:
753 REG(reg, "Policy Control", val);
754 break;
755 case 15:
756 REG(reg, "Port Ether Type", val);
757 break;
758 case 22:
759 REG(reg, "LED Control", val);
760 break;
761 case 23:
762 REG(reg, "IP Priority Mapping Table", val);
763 break;
764 case 24:
765 REG(reg, "IEEE Priority Mapping Table", val);
766 break;
767 case 25:
768 REG(reg, "Port Control 3", val);
769 break;
770 case 27:
771 REG(reg, "Queue Counters", val);
772 break;
773 case 28:
774 REG(reg, "Queue Control", val);
775 break;
776 case 30:
777 REG(reg, "Cut Through Control", val);
778 break;
779 case 31:
780 REG(reg, "Debug Counters", val);
781 break;
782 default:
783 REG(reg, "Reserved", val);
784 break;
785 }
786 };
787
788 struct dsa_mv88e6xxx_switch {
789 void (*dump)(int reg, u16 val);
790 const char *name;
791 u16 id;
792 };
793
794 static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = {
795 { .id = 0x04a0, .name = "88E6085 ", .dump = NULL },
796 { .id = 0x0950, .name = "88E6095 ", .dump = NULL },
797 { .id = 0x0990, .name = "88E6097 ", .dump = NULL },
798 { .id = 0x0a00, .name = "88E6190X", .dump = dsa_mv88e6390 },
799 { .id = 0x0a10, .name = "88E6390X", .dump = dsa_mv88e6390 },
800 { .id = 0x1060, .name = "88E6131 ", .dump = NULL },
801 { .id = 0x1150, .name = "88E6320 ", .dump = NULL },
802 { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 },
803 { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 },
804 { .id = 0x1650, .name = "88E6165 ", .dump = NULL },
805 { .id = 0x1710, .name = "88E6171 ", .dump = NULL },
806 { .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 },
807 { .id = 0x1750, .name = "88E6175 ", .dump = NULL },
808 { .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 },
809 { .id = 0x1900, .name = "88E6190 ", .dump = dsa_mv88e6390 },
810 { .id = 0x1910, .name = "88E6191 ", .dump = NULL },
811 { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 },
812 { .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 },
813 { .id = 0x2900, .name = "88E6290 ", .dump = dsa_mv88e6390 },
814 { .id = 0x3100, .name = "88E6321 ", .dump = NULL },
815 { .id = 0x3400, .name = "88E6141 ", .dump = NULL },
816 { .id = 0x3410, .name = "88E6341 ", .dump = NULL },
817 { .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 },
818 { .id = 0x3710, .name = "88E6350 ", .dump = NULL },
819 { .id = 0x3750, .name = "88E6351 ", .dump = NULL },
820 { .id = 0x3900, .name = "88E6390 ", .dump = dsa_mv88e6390 },
821 };
822
dsa_mv88e6xxx_dump_regs(struct ethtool_regs * regs)823 static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs)
824 {
825 const struct dsa_mv88e6xxx_switch *sw = NULL;
826 const u16 *data = (u16 *)regs->data;
827 unsigned int i;
828 u16 id;
829
830 /* Marvell chips have 32 per-port 16-bit registers */
831 if (regs->len < 32 * sizeof(u16))
832 return 1;
833
834 id = regs->version & 0xfff0;
835
836 for (i = 0; i < ARRAY_SIZE(dsa_mv88e6xxx_switches); i++) {
837 if (id == dsa_mv88e6xxx_switches[i].id) {
838 sw = &dsa_mv88e6xxx_switches[i];
839 break;
840 }
841 }
842
843 if (!sw)
844 return 1;
845
846 printf("%s Switch Port Registers\n", sw->name);
847 printf("------------------------------\n");
848
849 for (i = 0; i < 32; i++)
850 if (sw->dump)
851 sw->dump(i, data[i]);
852 else
853 REG(i, "", data[i]);
854
855 /* Dump the SERDES registers, if provided */
856 if (regs->len > SERDES_OFFSET * sizeof(u16)) {
857 printf("\n%s Switch Port SERDES Registers\n", sw->name);
858 printf("-------------------------------------\n");
859 for (i = SERDES_OFFSET; i < regs->len / 2; i++)
860 if (sw->dump)
861 sw->dump(i, data[i]);
862 else
863 REG(i - SERDES_OFFSET, "", data[i]);
864 }
865
866 return 0;
867 }
868
869 #undef FIELD_BITMAP
870 #undef FIELD
871 #undef REG
872
dsa_dump_regs(struct ethtool_drvinfo * info __maybe_unused,struct ethtool_regs * regs)873 int dsa_dump_regs(struct ethtool_drvinfo *info __maybe_unused,
874 struct ethtool_regs *regs)
875 {
876 /* DSA per-driver register dump */
877 if (!dsa_mv88e6xxx_dump_regs(regs))
878 return 0;
879
880 /* Fallback to hexdump */
881 return 1;
882 }
883