1 /* Copyright (c) 2023 Huawei Corporation */
2 #include <stdio.h>
3 #include <stdlib.h>
4 #include <errno.h>
5 #include "internal.h"
6
7 /* distinguish drive register data of earlier versions */
8 #define HNS3_REG_MAGIC_NUMBER 0x686e733372656773 /* hns3regs */
9 #define HNS3_REG_RSV_NAME "reserved"
10 #define HNS3_REG_UNKNOW_NAME "unknown"
11 #define HNS3_REG_UNKNOW_VALUE_LEN 4
12
13 struct hns3_reg_tlv {
14 u16 tag;
15 u16 len;
16 };
17
18 struct hns3_reg_header {
19 u64 magic_number;
20 u8 is_vf;
21 u8 rsv[7];
22 };
23
24 struct hns3_reg_info {
25 const char *name;
26 u16 value_len;
27 };
28
29 struct hns3_regs_group {
30 const char *group_name;
31 const struct hns3_reg_info *regs;
32 u16 regs_count;
33 };
34
35 enum hns3_reg_tag {
36 HNS3_TAG_CMDQ = 0,
37 HNS3_TAG_COMMON,
38 HNS3_TAG_RING,
39 HNS3_TAG_TQP_INTR,
40 HNS3_TAG_QUERY_32_BIT,
41 HNS3_TAG_QUERY_64_BIT,
42 HNS3_TAG_DFX_BIOS_COMMON,
43 HNS3_TAG_DFX_SSU_0,
44 HNS3_TAG_DFX_SSU_1,
45 HNS3_TAG_DFX_IGU_EGU,
46 HNS3_TAG_DFX_RPU_0,
47 HNS3_TAG_DFX_RPU_1,
48 HNS3_TAG_DFX_NCSI,
49 HNS3_TAG_DFX_RTC,
50 HNS3_TAG_DFX_PPP,
51 HNS3_TAG_DFX_RCB,
52 HNS3_TAG_DFX_TQP,
53 HNS3_TAG_DFX_SSU_2,
54 HNS3_TAG_DFX_RPU_TNL,
55 HNS3_TAG_MAX,
56 };
57
58 const bool hns3_reg_is_repeat_tag_array[] = {
59 [HNS3_TAG_RING] = true,
60 [HNS3_TAG_TQP_INTR] = true,
61 [HNS3_TAG_DFX_RPU_TNL] = true,
62 };
63
64 const struct hns3_reg_info pf_cmdq_regs[] = {
65 {"comm_nic_csq_baseaddr_l", 4},
66 {"comm_nic_csq_baseaddr_h", 4},
67 {"comm_nic_csq_depth", 4},
68 {"comm_nic_csq_tail", 4},
69 {"comm_nic_csq_head", 4},
70 {"comm_nic_crq_baseaddr_l", 4},
71 {"comm_nic_crq_baseaddr_h", 4},
72 {"comm_nic_crq_depth", 4},
73 {"comm_nic_crq_tail", 4},
74 {"comm_nic_crq_head", 4},
75 {"comm_vector0_cmdq_src", 4},
76 {"comm_cmdq_intr_sts", 4},
77 {"comm_cmdq_intr_en", 4},
78 {"comm_cmdq_intr_gen", 4},
79 };
80
81 const struct hns3_reg_info pf_common_regs[] = {
82 {"misc_vector_base", 4},
83 {"pf_other_int", 4},
84 {"misc_reset_sts", 4},
85 {"misc_vector_int_sts", 4},
86 {"global_reset", 4},
87 {"fun_rst_ing", 4},
88 {"gro_en", 4},
89 };
90
91 const struct hns3_reg_info pf_ring_regs[] = {
92 {"ring_rx_addr_l", 4},
93 {"ring_rx_addr_h", 4},
94 {"ring_rx_bd_num", 4},
95 {"ring_rx_bd_length", 4},
96 {"ring_rx_merge_en", 4},
97 {"ring_rx_tail", 4},
98 {"ring_rx_head", 4},
99 {"ring_rx_fbd_num", 4},
100 {"ring_rx_offset", 4},
101 {"ring_rx_fbd_offset", 4},
102 {"ring_rx_stash", 4},
103 {"ring_rx_bd_err", 4},
104 {"ring_tx_addr_l", 4},
105 {"ring_tx_addr_h", 4},
106 {"ring_tx_bd_num", 4},
107 {"ring_tx_priority", 4},
108 {"ring_tx_tc", 4},
109 {"ring_tx_merge_en", 4},
110 {"ring_tx_tail", 4},
111 {"ring_tx_head", 4},
112 {"ring_tx_fbd_num", 4},
113 {"ring_tx_offset", 4},
114 {"ring_tx_ebd_num", 4},
115 {"ring_tx_ebd_offset", 4},
116 {"ring_tx_bd_err", 4},
117 {"ring_en", 4},
118 };
119
120 const struct hns3_reg_info pf_tqp_intr_regs[] = {
121 {"tqp_intr_ctrl", 4},
122 {"tqp_intr_gl0", 4},
123 {"tqp_intr_gl1", 4},
124 {"tqp_intr_gl2", 4},
125 {"tqp_intr_rl", 4},
126 };
127
128 const struct hns3_reg_info query_32_bit_regs[] = {
129 {"ssu_common_err_int", 4},
130 {"ssu_port_based_err_int", 4},
131 {"ssu_fifo_overflow_int", 4},
132 {"ssu_ets_tcg_int", 4},
133 {"ssu_bp_status_0", 4},
134 {"ssu_bp_status_1", 4},
135 {"ssu_bp_status_2", 4},
136 {"ssu_bp_status_3", 4},
137 {"ssu_bp_status_4", 4},
138 {"ssu_bp_status_5", 4},
139 {"ssu_mac_tx_pfc_ind", 4},
140 {"ssu_mac_rx_pfc_ind", 4},
141 {"ssu_rx_oq_drop_pkt_cnt", 4},
142 {"ssu_tx_oq_drop_pkt_cnt", 4},
143 };
144
145 const struct hns3_reg_info query_64_bit_regs[] = {
146 {"ppp_get_rx_pkt_cnt", 8},
147 {"ppp_get_tx_pkt_cnt", 8},
148 {"ppp_send_uc_prt2host_pkt_cnt", 8},
149 {"ppp_send_uc_prt2prt_pkt_cnt", 8},
150 {"ppp_send_uc_host2host_pkt_cnt", 8},
151 {"ppp_send_uc_host2prt_pkt_cnt", 8},
152 {"ppp_send_mc_from_prt_cnt", 8},
153 };
154
155 const struct hns3_reg_info dfx_bios_common_regs[] = {
156 {HNS3_REG_RSV_NAME, 4},
157 {"bp_cpu_state", 4},
158 {"dfx_msix_info_nic_0", 4},
159 {"dfx_msix_info_nic_1", 4},
160 {"dfx_msix_info_nic_2", 4},
161 {"dfx_msix_info_nic_3", 4},
162 {"dfx_msix_info_roc_0", 4},
163 {"dfx_msix_info_roc_1", 4},
164 {"dfx_msix_info_roc_2", 4},
165 {"dfx_msix_info_roc_3", 4},
166 {HNS3_REG_RSV_NAME, 8},
167 };
168
169 const struct hns3_reg_info dfx_ssu_0_regs[] = {
170 {HNS3_REG_RSV_NAME, 4},
171 {"ssu_ets_port_status", 4},
172 {"ssu_ets_tcg_status", 4},
173 {HNS3_REG_RSV_NAME, 4},
174 {HNS3_REG_RSV_NAME, 4},
175 {"ssu_bp_status_0", 4},
176 {"ssu_bp_status_1", 4},
177 {"ssu_bp_status_2", 4},
178 {"ssu_bp_status_3", 4},
179 {"ssu_bp_status_4", 4},
180 {"ssu_bp_status_5", 4},
181 {"ssu_mac_tx_pfc_ind", 4},
182 {"mac_ssu_rx_pfc_ind", 4},
183 {"btmp_ageing_st_b0", 4},
184 {"btmp_ageing_st_b1", 4},
185 {"btmp_ageing_st_b2", 4},
186 {HNS3_REG_RSV_NAME, 8},
187 {"full_drop_num", 4},
188 {"part_drop_num", 4},
189 {"ppp_key_drop_num", 4},
190 {"ppp_rlt_drop_num", 4},
191 {"lo_pri_unicast_rlt_drop_num", 4},
192 {"hi_pri_multicast_rlt_drop_num", 4},
193 {"lo_pri_multicast_rlt_drop_num", 4},
194 {"ncsi_packet_curr_buffer_cnt", 4},
195 {HNS3_REG_RSV_NAME, 12},
196 {"ssu_mb_rd_rlt_drop_cnt", 4},
197 {"ssu_ppp_mac_key_num", 8},
198 {"ssu_ppp_host_key_num", 8},
199 {"ppp_ssu_mac_rlt_num", 8},
200 {"ppp_ssu_host_rlt_num", 8},
201 {"ncsi_rx_packet_in_cnt", 8},
202 {"ncsi_tx_packet_out_cnt", 8},
203 {"ssu_key_drop_num", 4},
204 {"mb_uncopy_num", 4},
205 {"rx_oq_drop_pkt_cnt", 4},
206 {"tx_oq_drop_pkt_cnt", 4},
207 {"bank_unbalance_drop_cnt", 4},
208 {"bank_unbalance_rx_drop_cnt", 4},
209 {"nic_l2_err_drop_pkt_cnt", 4},
210 {"roc_l2_err_drop_pkt_cnt", 4},
211 {"nic_l2_err_drop_pkt_cnt_rx", 4},
212 {"roc_l2_err_drop_pkt_cnt_rx", 4},
213 {"rx_oq_glb_drop_pkt_cnt", 4},
214 {HNS3_REG_RSV_NAME, 4},
215 {"lo_pri_unicast_cur_cnt", 4},
216 {"hi_pri_multicast_cur_cnt", 4},
217 {"lo_pri_multicast_cur_cnt", 4},
218 {HNS3_REG_RSV_NAME, 12},
219 };
220
221 const struct hns3_reg_info dfx_ssu_1_regs[] = {
222 {"prt_id", 4},
223 {"packet_tc_curr_buffer_cnt_0", 4},
224 {"packet_tc_curr_buffer_cnt_1", 4},
225 {"packet_tc_curr_buffer_cnt_2", 4},
226 {"packet_tc_curr_buffer_cnt_3", 4},
227 {"packet_tc_curr_buffer_cnt_4", 4},
228 {"packet_tc_curr_buffer_cnt_5", 4},
229 {"packet_tc_curr_buffer_cnt_6", 4},
230 {"packet_tc_curr_buffer_cnt_7", 4},
231 {"packet_curr_buffer_cnt", 4},
232 {HNS3_REG_RSV_NAME, 8},
233 {"rx_packet_in_cnt", 8},
234 {"rx_packet_out_cnt", 8},
235 {"tx_packet_in_cnt", 8},
236 {"tx_packet_out_cnt", 8},
237 {"roc_rx_packet_in_cnt", 8},
238 {"roc_tx_packet_out_cnt", 8},
239 {"rx_packet_tc_in_cnt_0", 8},
240 {"rx_packet_tc_in_cnt_1", 8},
241 {"rx_packet_tc_in_cnt_2", 8},
242 {"rx_packet_tc_in_cnt_3", 8},
243 {"rx_packet_tc_in_cnt_4", 8},
244 {"rx_packet_tc_in_cnt_5", 8},
245 {"rx_packet_tc_in_cnt_6", 8},
246 {"rx_packet_tc_in_cnt_7", 8},
247 {"rx_packet_tc_out_cnt_0", 8},
248 {"rx_packet_tc_out_cnt_1", 8},
249 {"rx_packet_tc_out_cnt_2", 8},
250 {"rx_packet_tc_out_cnt_3", 8},
251 {"rx_packet_tc_out_cnt_4", 8},
252 {"rx_packet_tc_out_cnt_5", 8},
253 {"rx_packet_tc_out_cnt_6", 8},
254 {"rx_packet_tc_out_cnt_7", 8},
255 {"tx_packet_tc_in_cnt_0", 8},
256 {"tx_packet_tc_in_cnt_1", 8},
257 {"tx_packet_tc_in_cnt_2", 8},
258 {"tx_packet_tc_in_cnt_3", 8},
259 {"tx_packet_tc_in_cnt_4", 8},
260 {"tx_packet_tc_in_cnt_5", 8},
261 {"tx_packet_tc_in_cnt_6", 8},
262 {"tx_packet_tc_in_cnt_7", 8},
263 {"tx_packet_tc_out_cnt_0", 8},
264 {"tx_packet_tc_out_cnt_1", 8},
265 {"tx_packet_tc_out_cnt_2", 8},
266 {"tx_packet_tc_out_cnt_3", 8},
267 {"tx_packet_tc_out_cnt_4", 8},
268 {"tx_packet_tc_out_cnt_5", 8},
269 {"tx_packet_tc_out_cnt_6", 8},
270 {"tx_packet_tc_out_cnt_7", 8},
271 {HNS3_REG_RSV_NAME, 8},
272 };
273
274 const struct hns3_reg_info dfx_igu_egu_regs[] = {
275 {"prt_id", 4},
276 {"igu_rx_err_pkt", 4},
277 {"igu_rx_no_sof_pkt", 4},
278 {"egu_tx_1588_short_pkt", 4},
279 {"egu_tx_1588_pkt", 4},
280 {"egu_tx_err_pkt", 4},
281 {"igu_rx_out_l2_pkt", 4},
282 {"igu_rx_out_l3_pkt", 4},
283 {"igu_rx_out_l4_pkt", 4},
284 {"igu_rx_in_l2_pkt", 4},
285 {"igu_rx_in_l3_pkt", 4},
286 {"igu_rx_in_l4_pkt", 4},
287 {"igu_rx_el3e_pkt", 4},
288 {"igu_rx_el4e_pkt", 4},
289 {"igu_rx_l3e_pkt", 4},
290 {"igu_rx_l4e_pkt", 4},
291 {"igu_rx_rocee_pkt", 4},
292 {"igu_rx_out_udp0_pkt", 4},
293 {"igu_rx_in_udp0_pkt", 4},
294 {"mul_car_drop_pkt_cnt", 8},
295 {"bro_car_drop_pkt_cnt", 8},
296 {HNS3_REG_RSV_NAME, 4},
297 {"igu_rx_oversize_pkt", 8},
298 {"igu_rx_undersize_pkt", 8},
299 {"igu_rx_out_all_pkt", 8},
300 {"igu_tx_out_all_pkt", 8},
301 {"igu_rx_uni_pkt", 8},
302 {"igu_rx_multi_pkt", 8},
303 {"igu_rx_broad_pkt", 8},
304 {"egu_tx_out_all_pkt", 8},
305 {"egu_tx_uni_pkt", 8},
306 {"egu_tx_multi_pkt", 8},
307 {"egu_tx_broad_pkt", 8},
308 {"igu_tx_key_num", 8},
309 {"igu_rx_non_tun_pkt", 8},
310 {"igu_rx_tun_pkt", 8},
311 {HNS3_REG_RSV_NAME, 8},
312 };
313
314 const struct hns3_reg_info dfx_rpu_0_regs[] = {
315 {HNS3_REG_RSV_NAME, 4},
316 {"fsm_dfx_st0", 4},
317 {"fsm_dfx_st1", 4},
318 {"rpu_rx_pkt_drop_cnt", 4},
319 {"buf_wait_timeout", 4},
320 {"buf_wait_timeout_qid", 4},
321 };
322
323 const struct hns3_reg_info dfx_rpu_1_regs[] = {
324 {HNS3_REG_RSV_NAME, 4},
325 {"fifo_dfx_st0", 4},
326 {"fifo_dfx_st1", 4},
327 {"fifo_dfx_st2", 4},
328 {"fifo_dfx_st3", 4},
329 {"fifo_dfx_st4", 4},
330 {"fifo_dfx_st5", 4},
331 {HNS3_REG_RSV_NAME, 20},
332 };
333
334 const struct hns3_reg_info dfx_ncsi_regs[] = {
335 {HNS3_REG_RSV_NAME, 4},
336 {"ncsi_egu_tx_fifo_sts", 4},
337 {"ncsi_pause_status", 4},
338 {"ncsi_rx_ctrl_dmac_err_cnt", 4},
339 {"ncsi_rx_ctrl_smac_err_cnt", 4},
340 {"ncsi_rx_ctrl_cks_err_cnt", 4},
341 {"ncsi_rx_ctrl_pkt_cnt", 4},
342 {"ncsi_rx_pt_dmac_err_cnt", 4},
343 {"ncsi_rx_pt_smac_err_cnt", 4},
344 {"ncsi_rx_pt_pkt_cnt", 4},
345 {"ncsi_rx_fcs_err_cnt", 4},
346 {"ncsi_tx_ctrl_dmac_err_cnt", 4},
347 {"ncsi_tx_ctrl_smac_err_cnt", 4},
348 {"ncsi_tx_ctrl_pkt_cnt", 4},
349 {"ncsi_tx_pt_dmac_err_cnt", 4},
350 {"ncsi_tx_pt_smac_err_cnt", 4},
351 {"ncsi_tx_pt_pkt_cnt", 4},
352 {"ncsi_tx_pt_pkt_trun_cnt", 4},
353 {"ncsi_tx_pt_pkt_err_cnt", 4},
354 {"ncsi_tx_ctrl_pkt_err_cnt", 4},
355 {"ncsi_rx_ctrl_pkt_trun_cnt", 4},
356 {"ncsi_rx_ctrl_pkt_cflit_cnt", 4},
357 {HNS3_REG_RSV_NAME, 8},
358 {"ncsi_mac_rx_octets_ok", 4},
359 {"ncsi_mac_rx_octets_bad", 4},
360 {"ncsi_mac_rx_uc_pkts", 4},
361 {"ncsi_mac_rx_mc_pkts", 4},
362 {"ncsi_mac_rx_bc_pkts", 4},
363 {"ncsi_mac_rx_pkts_64octets", 4},
364 {"ncsi_mac_rx_pkts_65to127octets", 4},
365 {"ncsi_mac_rx_pkts_128to255octets", 4},
366 {"ncsi_mac_rx_pkts_256to511octets", 4},
367 {"ncsi_mac_rx_pkts_512to1023octets", 4},
368 {"ncsi_mac_rx_pkts_1024to1518octets", 4},
369 {"ncsi_mac_rx_pkts_1519tomaxoctets", 4},
370 {"ncsi_mac_rx_fcs_errors", 4},
371 {"ncsi_mac_rx_long_errors", 4},
372 {"ncsi_mac_rx_jabber_errors", 4},
373 {"ncsi_mac_rx_runt_err_cnt", 4},
374 {"ncsi_mac_rx_short_err_cnt", 4},
375 {"ncsi_mac_rx_filt_pkt_cnt", 4},
376 {"ncsi_mac_rx_octets_total_filt", 4},
377 {"ncsi_mac_tx_octets_ok", 4},
378 {"ncsi_mac_tx_octets_bad", 4},
379 {"ncsi_mac_tx_uc_pkts", 4},
380 {"ncsi_mac_tx_mc_pkts", 4},
381 {"ncsi_mac_tx_bc_pkts", 4},
382 {"ncsi_mac_tx_pkts_64octets", 4},
383 {"ncsi_mac_tx_pkts_65to127octets", 4},
384 {"ncsi_mac_tx_pkts_128to255octets", 4},
385 {"ncsi_mac_tx_pkts_256to511octets", 4},
386 {"ncsi_mac_tx_pkts_512to1023octets", 4},
387 {"ncsi_mac_tx_pkts_1024to1518octets", 4},
388 {"ncsi_mac_tx_pkts_1519tomaxoctets", 4},
389 {"ncsi_mac_tx_underrun", 4},
390 {"ncsi_mac_tx_crc_error", 4},
391 {"ncsi_mac_tx_pause_frames", 4},
392 {"ncsi_mac_rx_pad_pkts", 4},
393 {"ncsi_mac_rx_pause_frames", 4},
394 };
395
396 const struct hns3_reg_info dfx_rtc_regs[] = {
397 {HNS3_REG_RSV_NAME, 4},
398 {"lge_igu_afifo_dfx_0", 4},
399 {"lge_igu_afifo_dfx_1", 4},
400 {"lge_igu_afifo_dfx_2", 4},
401 {"lge_igu_afifo_dfx_3", 4},
402 {"lge_igu_afifo_dfx_4", 4},
403 {"lge_igu_afifo_dfx_5", 4},
404 {"lge_igu_afifo_dfx_6", 4},
405 {"lge_igu_afifo_dfx_7", 4},
406 {"lge_egu_afifo_dfx_0", 4},
407 {"lge_egu_afifo_dfx_1", 4},
408 {"lge_egu_afifo_dfx_2", 4},
409 {"lge_egu_afifo_dfx_3", 4},
410 {"lge_egu_afifo_dfx_4", 4},
411 {"lge_egu_afifo_dfx_5", 4},
412 {"lge_egu_afifo_dfx_6", 4},
413 {"lge_egu_afifo_dfx_7", 4},
414 {"cge_igu_afifo_dfx_0", 4},
415 {"cge_igu_afifo_dfx_1", 4},
416 {"cge_egu_afifo_dfx_0", 4},
417 {"cge_egu_afifo_dfx_1", 4},
418 {HNS3_REG_RSV_NAME, 12},
419 };
420
421 const struct hns3_reg_info dfx_ppp_regs[] = {
422 {HNS3_REG_RSV_NAME, 4},
423 {"drop_from_prt_pkt_cnt", 4},
424 {"drop_from_host_pkt_cnt", 4},
425 {"drop_tx_vlan_proc_cnt", 4},
426 {"drop_mng_cnt", 4},
427 {"drop_fd_cnt", 4},
428 {"drop_no_dst_cnt", 4},
429 {"drop_mc_mbid_full_cnt", 4},
430 {"drop_sc_filtered", 4},
431 {"ppp_mc_drop_pkt_cnt", 4},
432 {"drop_pt_cnt", 4},
433 {"drop_mac_anti_spoof_cnt", 4},
434 {"drop_ig_vfv_cnt", 4},
435 {"drop_ig_prtv_cnt", 4},
436 {"drop_cnm_pfc_pause_cnt", 4},
437 {"drop_torus_tc_cnt", 4},
438 {"drop_torus_lpbk_cnt", 4},
439 {"ppp_hfs_sts", 4},
440 {"ppp_mc_rslt_sts", 4},
441 {"ppp_p3u_sts", 4},
442 {HNS3_REG_RSV_NAME, 4},
443 {"ppp_umv_sts_0", 4},
444 {"ppp_umv_sts_1", 4},
445 {"ppp_vfv_sts", 4},
446 {"ppp_gro_key_cnt", 4},
447 {"ppp_gro_info_cnt", 4},
448 {"ppp_gro_drop_cnt", 4},
449 {"ppp_gro_out_cnt", 4},
450 {"ppp_gro_key_match_data_cnt", 4},
451 {"ppp_gro_key_match_tcam_cnt", 4},
452 {"ppp_gro_info_match_cnt", 4},
453 {"ppp_gro_free_entry_cnt", 4},
454 {"ppp_gro_inner_dfx_signal", 4},
455 {HNS3_REG_RSV_NAME, 12},
456 {"get_rx_pkt_cnt", 8},
457 {"get_tx_pkt_cnt", 8},
458 {"send_uc_prt2host_pkt_cnt", 8},
459 {"send_uc_prt2prt_pkt_cnt", 8},
460 {"send_uc_host2host_pkt_cnt", 8},
461 {"send_uc_host2prt_pkt_cnt", 8},
462 {"send_mc_from_prt_cnt", 8},
463 {"send_mc_from_host_cnt", 8},
464 {"ssu_mc_rd_cnt", 8},
465 {"ssu_mc_drop_cnt", 8},
466 {"ssu_mc_rd_pkt_cnt", 8},
467 {"ppp_mc_2host_pkt_cnt", 8},
468 {"ppp_mc_2prt_pkt_cnt", 8},
469 {"ntsnos_pkt_cnt", 8},
470 {"ntup_pkt_cnt", 8},
471 {"ntlcl_pkt_cnt", 8},
472 {"nttgt_pkt_cnt", 8},
473 {"rtns_pkt_cnt", 8},
474 {"rtlpbk_pkt_cnt", 8},
475 {"nr_pkt_cnt", 8},
476 {"rr_pkt_cnt", 8},
477 {"mng_tbl_hit_cnt", 8},
478 {"fd_tbl_hit_cnt", 8},
479 {"fd_lkup_cnt", 8},
480 {"bc_hit_cnt", 8},
481 {"um_tbl_uc_hit_cnt", 8},
482 {"um_tbl_mc_hit_cnt", 8},
483 {"um_tbl_snq_hit_cnt", 8},
484 {HNS3_REG_RSV_NAME, 8},
485 {"fwd_bonding_hit_cnt", 8},
486 {"promis_tbl_hit_cnt", 8},
487 {"get_tunl_pkt_cnt", 8},
488 {"get_bmc_pkt_cnt", 8},
489 {"send_uc_prt2bmc_pkt_cnt", 8},
490 {"send_uc_host2bmc_pkt_cnt", 8},
491 {"send_uc_bmc2host_pkt_cnt", 8},
492 {"send_uc_bmc2prt_pkt_cnt", 8},
493 {"ppp_mc_2bmc_pkt_cnt", 8},
494 {HNS3_REG_RSV_NAME, 24},
495 {"rx_default_host_hit_cnt", 8},
496 {"lan_pair_cnt", 8},
497 {"um_tbl_mc_hit_pkt_cnt", 8},
498 {"mta_tbl_hit_pkt_cnt", 8},
499 {"promis_tbl_hit_pkt_cnt", 8},
500 {HNS3_REG_RSV_NAME, 16},
501 };
502
503 const struct hns3_reg_info dfx_rcb_regs[] = {
504 {HNS3_REG_RSV_NAME, 4},
505 {"fsm_dfx_st0", 4},
506 {"fsm_dfx_st1", 4},
507 {"fsm_dfx_st2", 4},
508 {"fifo_dfx_st0", 4},
509 {"fifo_dfx_st1", 4},
510 {"fifo_dfx_st2", 4},
511 {"fifo_dfx_st3", 4},
512 {"fifo_dfx_st4", 4},
513 {"fifo_dfx_st5", 4},
514 {"fifo_dfx_st6", 4},
515 {"fifo_dfx_st7", 4},
516 {"fifo_dfx_st8", 4},
517 {"fifo_dfx_st9", 4},
518 {"fifo_dfx_st10", 4},
519 {"fifo_dfx_st11", 4},
520 {"q_credit_vld_0", 4},
521 {"q_credit_vld_1", 4},
522 {"q_credit_vld_2", 4},
523 {"q_credit_vld_3", 4},
524 {"q_credit_vld_4", 4},
525 {"q_credit_vld_5", 4},
526 {"q_credit_vld_6", 4},
527 {"q_credit_vld_7", 4},
528 {"q_credit_vld_8", 4},
529 {"q_credit_vld_9", 4},
530 {"q_credit_vld_10", 4},
531 {"q_credit_vld_11", 4},
532 {"q_credit_vld_12", 4},
533 {"q_credit_vld_13", 4},
534 {"q_credit_vld_14", 4},
535 {"q_credit_vld_15", 4},
536 {"q_credit_vld_16", 4},
537 {"q_credit_vld_17", 4},
538 {"q_credit_vld_18", 4},
539 {"q_credit_vld_19", 4},
540 {"q_credit_vld_20", 4},
541 {"q_credit_vld_21", 4},
542 {"q_credit_vld_22", 4},
543 {"q_credit_vld_23", 4},
544 {"q_credit_vld_24", 4},
545 {"q_credit_vld_25", 4},
546 {"q_credit_vld_26", 4},
547 {"q_credit_vld_27", 4},
548 {"q_credit_vld_28", 4},
549 {"q_credit_vld_29", 4},
550 {"q_credit_vld_30", 4},
551 {"q_credit_vld_31", 4},
552 {"gro_bd_serr_cnt", 4},
553 {"gro_context_serr_cnt", 4},
554 {"rx_stash_cfg_serr_cnt", 4},
555 {"rcb_tx_mem_serr_cnt", 4},
556 {"gro_bd_merr_cnt", 4},
557 {"gro_context_merr_cnt", 4},
558 {"rx_stash_cfg_merr_cnt", 4},
559 {"rcb_tx_mem_merr_cnt", 4},
560 {HNS3_REG_RSV_NAME, 16},
561 };
562
563 const struct hns3_reg_info dfx_tqp_regs[] = {
564 {"q_num", 4},
565 {"rcb_cfg_rx_ring_tail", 4},
566 {"rcb_cfg_rx_ring_head", 4},
567 {"rcb_cfg_rx_ring_fbdnum", 4},
568 {"rcb_cfg_rx_ring_offset", 4},
569 {"rcb_cfg_rx_ring_fbdoffset", 4},
570 {"rcb_cfg_rx_ring_pktnum_record", 4},
571 {"rcb_cfg_tx_ring_tail", 4},
572 {"rcb_cfg_tx_ring_head", 4},
573 {"rcb_cfg_tx_ring_fbdnum", 4},
574 {"rcb_cfg_tx_ring_offset", 4},
575 {"rcb_cfg_tx_ring_ebdnum", 4},
576 };
577
578 const struct hns3_reg_info dfx_ssu_2_regs[] = {
579 {"oq_index", 4},
580 {"queue_cnt", 4},
581 {HNS3_REG_RSV_NAME, 16},
582 };
583
584 const struct hns3_reg_info vf_cmdq_regs[] = {
585 {"comm_nic_csq_baseaddr_l", 4},
586 {"comm_nic_csq_baseaddr_h", 4},
587 {"comm_nic_csq_depth", 4},
588 {"comm_nic_csq_tail", 4},
589 {"comm_nic_csq_head", 4},
590 {"comm_nic_crq_baseaddr_l", 4},
591 {"comm_nic_crq_baseaddr_h", 4},
592 {"comm_nic_crq_depth", 4},
593 {"comm_nic_crq_tail", 4},
594 {"comm_nic_crq_head", 4},
595 {"comm_vector0_cmdq_src", 4},
596 {"comm_vector0_cmdq_state", 4},
597 {"comm_cmdq_intr_en", 4},
598 {"comm_cmdq_intr_gen", 4},
599 };
600
601 const struct hns3_reg_info vf_common_regs[] = {
602 {"misc_vector_base", 4},
603 {"rst_ing", 4},
604 {"gro_en", 4},
605 };
606
607 const struct hns3_reg_info vf_ring_regs[] = {
608 {"ring_rx_addr_l", 4},
609 {"ring_rx_addr_h", 4},
610 {"ring_rx_bd_num", 4},
611 {"ring_rx_bd_length", 4},
612 {"ring_rx_merge_en", 4},
613 {"ring_rx_tail", 4},
614 {"ring_rx_head", 4},
615 {"ring_rx_fbd_num", 4},
616 {"ring_rx_offset", 4},
617 {"ring_rx_fbd_offset", 4},
618 {"ring_rx_stash", 4},
619 {"ring_rx_bd_err", 4},
620 {"ring_tx_addr_l", 4},
621 {"ring_tx_addr_h", 4},
622 {"ring_tx_bd_num", 4},
623 {"ring_tx_priority", 4},
624 {"ring_tx_tc", 4},
625 {"ring_tx_merge_en", 4},
626 {"ring_tx_tail", 4},
627 {"ring_tx_head", 4},
628 {"ring_tx_fbd_num", 4},
629 {"ring_tx_offset", 4},
630 {"ring_tx_ebd_num", 4},
631 {"ring_tx_ebd_offset", 4},
632 {"ring_tx_bd_err", 4},
633 {"ring_en", 4},
634 };
635
636 const struct hns3_reg_info vf_tqp_intr_regs[] = {
637 {"tqp_intr_ctrl", 4},
638 {"tqp_intr_gl0", 4},
639 {"tqp_intr_gl1", 4},
640 {"tqp_intr_gl2", 4},
641 {"tqp_intr_rl", 4},
642 };
643
644 const struct hns3_regs_group pf_regs_groups[] = {
645 [HNS3_TAG_CMDQ] = {"cmdq_regs", pf_cmdq_regs, ARRAY_SIZE(pf_cmdq_regs)},
646 [HNS3_TAG_COMMON] = {"common_regs", pf_common_regs,
647 ARRAY_SIZE(pf_common_regs)},
648 [HNS3_TAG_RING] = {"ring_regs", pf_ring_regs, ARRAY_SIZE(pf_ring_regs)},
649 [HNS3_TAG_TQP_INTR] = {"tqp_intr_regs", pf_tqp_intr_regs,
650 ARRAY_SIZE(pf_tqp_intr_regs)},
651 [HNS3_TAG_QUERY_32_BIT] = {"dfx_32_regs", query_32_bit_regs,
652 ARRAY_SIZE(query_32_bit_regs)},
653 [HNS3_TAG_QUERY_64_BIT] = {"dfx_64_regs", query_64_bit_regs,
654 ARRAY_SIZE(query_64_bit_regs)},
655 [HNS3_TAG_DFX_BIOS_COMMON] = {"dfx_bios_common_regs",
656 dfx_bios_common_regs,
657 ARRAY_SIZE(dfx_bios_common_regs)},
658 [HNS3_TAG_DFX_SSU_0] = {"dfx_ssu_0_regs", dfx_ssu_0_regs,
659 ARRAY_SIZE(dfx_ssu_0_regs)},
660 [HNS3_TAG_DFX_SSU_1] = {"dfx_ssu_1_regs", dfx_ssu_1_regs,
661 ARRAY_SIZE(dfx_ssu_1_regs)},
662 [HNS3_TAG_DFX_IGU_EGU] = {"dfx_igu_egu_regs", dfx_igu_egu_regs,
663 ARRAY_SIZE(dfx_igu_egu_regs)},
664 [HNS3_TAG_DFX_RPU_0] = {"dfx_rpu_0_regs", dfx_rpu_0_regs,
665 ARRAY_SIZE(dfx_rpu_0_regs)},
666 [HNS3_TAG_DFX_RPU_1] = {"dfx_rpu_1_regs", dfx_rpu_1_regs,
667 ARRAY_SIZE(dfx_rpu_1_regs)},
668 [HNS3_TAG_DFX_NCSI] = {"dfx_ncsi_regs", dfx_ncsi_regs,
669 ARRAY_SIZE(dfx_ncsi_regs)},
670 [HNS3_TAG_DFX_RTC] = {"dfx_rtc_regs", dfx_rtc_regs,
671 ARRAY_SIZE(dfx_rtc_regs)},
672 [HNS3_TAG_DFX_PPP] = {"dfx_ppp_regs", dfx_ppp_regs,
673 ARRAY_SIZE(dfx_ppp_regs)},
674 [HNS3_TAG_DFX_RCB] = {"dfx_rcb_regs", dfx_rcb_regs,
675 ARRAY_SIZE(dfx_rcb_regs)},
676 [HNS3_TAG_DFX_TQP] = {"dfx_tqp_regs", dfx_tqp_regs,
677 ARRAY_SIZE(dfx_tqp_regs)},
678 [HNS3_TAG_DFX_SSU_2] = {"dfx_ssu_2_regs", dfx_ssu_2_regs,
679 ARRAY_SIZE(dfx_ssu_2_regs)},
680 [HNS3_TAG_DFX_RPU_TNL] = {"dfx_rpu_tnl", dfx_rpu_0_regs,
681 ARRAY_SIZE(dfx_rpu_0_regs)},
682 };
683
684 const struct hns3_regs_group vf_regs_groups[] = {
685 [HNS3_TAG_CMDQ] = {"cmdq_regs", vf_cmdq_regs, ARRAY_SIZE(vf_cmdq_regs)},
686 [HNS3_TAG_COMMON] = {"common_regs", vf_common_regs,
687 ARRAY_SIZE(vf_common_regs)},
688 [HNS3_TAG_RING] = {"ring_regs", vf_ring_regs, ARRAY_SIZE(vf_ring_regs)},
689 [HNS3_TAG_TQP_INTR] = {"tqp_intr_regs", vf_tqp_intr_regs,
690 ARRAY_SIZE(vf_tqp_intr_regs)},
691 };
692
hns3_dump_reg_hex(const char * regs_name,const u8 * regs_data,u16 value_len,u32 name_max_len)693 static void hns3_dump_reg_hex(const char *regs_name, const u8 *regs_data,
694 u16 value_len, u32 name_max_len)
695 {
696 if (strcmp(regs_name, HNS3_REG_RSV_NAME) == 0)
697 return;
698
699 fprintf(stdout, " %-*s : ", name_max_len, regs_name);
700 if (value_len == 4) /* 4 bytes register */
701 fprintf(stdout, "0x%08x\n", *(u32 *)regs_data);
702 if (value_len == 8) /* 8 bytes register */
703 fprintf(stdout, "0x%016llx\n", *(u64 *)regs_data);
704 }
705
hns3_get_group_regs_name_max_len(const struct hns3_regs_group * group)706 static u32 hns3_get_group_regs_name_max_len(const struct hns3_regs_group *group)
707 {
708 const struct hns3_reg_info *reg;
709 u32 max_len = 0;
710 u16 i;
711
712 for (i = 0; i < group->regs_count; i++) {
713 reg = &group->regs[i];
714 max_len = strlen(reg->name) > max_len ?
715 strlen(reg->name) : max_len;
716 }
717
718 return max_len;
719 }
720
hns3_get_group_name(const struct hns3_regs_group * group,u32 tag)721 static const char *hns3_get_group_name(const struct hns3_regs_group *group,
722 u32 tag)
723 {
724 static u32 pre_tag = HNS3_TAG_MAX;
725 static char group_name[256];
726 static u32 index;
727
728 if (!hns3_reg_is_repeat_tag_array[tag])
729 return group->group_name;
730
731 if (tag != pre_tag)
732 index = 0;
733
734 pre_tag = tag;
735 sprintf(group_name, "%s_%u", group->group_name, index++);
736 return group_name;
737 }
738
hns3_dump_reg_group(const struct hns3_regs_group * group,u32 tag,u32 expected_len,const u8 * regs_data)739 static void hns3_dump_reg_group(const struct hns3_regs_group *group, u32 tag,
740 u32 expected_len, const u8 *regs_data)
741 {
742 u32 name_max_len = hns3_get_group_regs_name_max_len(group);
743 const struct hns3_reg_info *reg;
744 u32 dump_offset = 0;
745 u16 i;
746
747 fprintf(stdout, "[%s]\n", hns3_get_group_name(group, tag));
748 for (i = 0; i < group->regs_count && dump_offset < expected_len; i++) {
749 reg = &group->regs[i];
750 hns3_dump_reg_hex(reg->name, regs_data + dump_offset,
751 reg->value_len, name_max_len);
752 dump_offset += reg->value_len;
753 }
754
755 /* the driver may add new register.
756 * In this case, the register name is unknown.
757 * The register can be parsed as unknown:value format.
758 */
759 while (dump_offset < expected_len) {
760 hns3_dump_reg_hex(HNS3_REG_UNKNOW_NAME, regs_data + dump_offset,
761 HNS3_REG_UNKNOW_VALUE_LEN, name_max_len);
762 dump_offset += HNS3_REG_UNKNOW_VALUE_LEN;
763 }
764 }
765
hns3_dump_as_groups(const struct hns3_regs_group * groups,const u8 * regs_data,u32 regs_len)766 static void hns3_dump_as_groups(const struct hns3_regs_group *groups,
767 const u8 *regs_data, u32 regs_len)
768 {
769 u32 tlv_size = sizeof(struct hns3_reg_tlv);
770 const struct hns3_reg_tlv *tlv;
771 u32 dump_offset = 0;
772
773 while (dump_offset < regs_len) {
774 tlv = (const struct hns3_reg_tlv *)(regs_data + dump_offset);
775 hns3_dump_reg_group(&groups[tlv->tag], tlv->tag,
776 tlv->len - tlv_size,
777 regs_data + dump_offset + tlv_size);
778 dump_offset += tlv->len;
779 }
780 }
781
hns3_dump_validate(const u8 * regs_data,u32 regs_len)782 static bool hns3_dump_validate(const u8 *regs_data, u32 regs_len)
783 {
784 u32 tlv_size = sizeof(struct hns3_reg_tlv);
785 const struct hns3_reg_tlv *tlv;
786 u32 dump_offset = 0;
787
788 while (dump_offset < regs_len) {
789 tlv = (const struct hns3_reg_tlv *)(regs_data + dump_offset);
790
791 /* register value length is 4 bytes or 8 bytes */
792 if ((tlv->len - tlv_size) % 4)
793 return false;
794
795 if (tlv->tag >= HNS3_TAG_MAX)
796 return false;
797
798 dump_offset += tlv->len;
799 }
800
801 return dump_offset == regs_len;
802 }
803
hns3_dump_regs(struct ethtool_drvinfo * info __maybe_unused,struct ethtool_regs * regs)804 int hns3_dump_regs(struct ethtool_drvinfo *info __maybe_unused,
805 struct ethtool_regs *regs)
806 {
807 const struct hns3_regs_group *groups = pf_regs_groups;
808 u32 header_len = sizeof(struct hns3_reg_header);
809 const struct hns3_reg_header *header;
810
811 /* must contain header and register data */
812 if (regs->len <= header_len)
813 return -ENODATA;
814
815 header = (struct hns3_reg_header *)regs->data;
816 if (header->magic_number != HNS3_REG_MAGIC_NUMBER)
817 return -EOPNOTSUPP;
818
819 if (!hns3_dump_validate(regs->data + header_len,
820 regs->len - header_len))
821 return -EINVAL;
822
823 if (header->is_vf)
824 groups = vf_regs_groups;
825
826 hns3_dump_as_groups(groups, regs->data + header_len,
827 regs->len - header_len);
828 return 0;
829 }
830