1 /* 2 * This file is part of the flashrom project. 3 * 4 * Copyright (C) 2000 Silicon Integrated System Corporation 5 * Copyright (C) 2000 Ronald G. Minnich <[email protected]> 6 * Copyright (C) 2005-2009 coresystems GmbH 7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #ifndef __FLASH_H__ 21 #define __FLASH_H__ 1 22 23 #include <inttypes.h> 24 #include <stdio.h> 25 #include <stdint.h> 26 #include <stddef.h> 27 #include <stdarg.h> 28 #include <stdbool.h> 29 #if IS_WINDOWS 30 #include <windows.h> 31 #undef min 32 #undef max 33 #endif 34 35 #include "libflashrom.h" 36 #include "layout.h" 37 #include "writeprotect.h" 38 39 #define KiB (1024) 40 #define MiB (1024 * KiB) 41 42 #define BIT(x) (1<<(x)) 43 44 /* Assumes `n` and `a` are at most 64-bit wide (to avoid typeof() operator). */ 45 #define ALIGN_DOWN(n, a) ((n) & ~((uint64_t)(a) - 1)) 46 47 #define ERROR_PTR ((void*)-1) 48 49 /* Error codes */ 50 #define ERROR_OOM -100 51 #define TIMEOUT_ERROR -101 52 53 /* TODO: check using code for correct usage of types */ 54 typedef uintptr_t chipaddr; 55 #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) 56 57 int register_shutdown(int (*function) (void *data), void *data); 58 struct registered_master; 59 void *master_map_flash_region(const struct registered_master *mast, 60 const char *descr, uintptr_t phys_addr, size_t len); 61 void master_unmap_flash_region(const struct registered_master *mast, 62 void *virt_addr, size_t len); 63 /* NOTE: flashctx is not used in default_delay. In this case, a context should be NULL. */ 64 void programmer_delay(const struct flashrom_flashctx *flash, unsigned int usecs); 65 66 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) 67 68 enum chipbustype { 69 BUS_NONE = 0, 70 BUS_PARALLEL = 1 << 0, 71 BUS_LPC = 1 << 1, 72 BUS_FWH = 1 << 2, 73 BUS_SPI = 1 << 3, 74 BUS_PROG = 1 << 4, 75 BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, 76 }; 77 78 /* 79 * The following enum defines possible write granularities of flash chips. These tend to reflect the properties 80 * of the actual hardware not necessarily the write function(s) defined by the respective struct flashchip. 81 * The latter might (and should) be more precisely specified, e.g. they might bail out early if their execution 82 * would result in undefined chip contents. 83 */ 84 enum write_granularity { 85 /* We assume 256 byte granularity by default. */ 86 WRITE_GRAN_256BYTES = 0,/* If less than 256 bytes are written, the unwritten bytes are undefined. */ 87 WRITE_GRAN_1BIT, /* Each bit can be cleared individually. */ 88 WRITE_GRAN_1BYTE, /* A byte can be written once. Further writes to an already written byte cause 89 * its contents to be either undefined or to stay unchanged. */ 90 WRITE_GRAN_128BYTES, /* If less than 128 bytes are written, the unwritten bytes are undefined. */ 91 WRITE_GRAN_264BYTES, /* If less than 264 bytes are written, the unwritten bytes are undefined. */ 92 WRITE_GRAN_512BYTES, /* If less than 512 bytes are written, the unwritten bytes are undefined. */ 93 WRITE_GRAN_528BYTES, /* If less than 528 bytes are written, the unwritten bytes are undefined. */ 94 WRITE_GRAN_1024BYTES, /* If less than 1024 bytes are written, the unwritten bytes are undefined. */ 95 WRITE_GRAN_1056BYTES, /* If less than 1056 bytes are written, the unwritten bytes are undefined. */ 96 WRITE_GRAN_1BYTE_IMPLICIT_ERASE, /* EEPROMs and other chips with implicit erase and 1-byte writes. */ 97 }; 98 99 /* 100 * How many different contiguous runs of erase blocks with one size each do 101 * we have for a given erase function? 102 */ 103 #define NUM_ERASEREGIONS 5 104 105 /* 106 * How many different erase functions do we have per chip? 107 * Macronix MX25L25635F has 8 different functions. 108 */ 109 #define NUM_ERASEFUNCTIONS 8 110 111 #define MAX_CHIP_RESTORE_FUNCTIONS 4 112 113 /* Feature bits used for non-SPI only */ 114 #define FEATURE_REGISTERMAP (1 << 0) 115 #define FEATURE_LONG_RESET (0 << 4) 116 #define FEATURE_SHORT_RESET (1 << 4) 117 #define FEATURE_EITHER_RESET FEATURE_LONG_RESET 118 #define FEATURE_RESET_MASK (FEATURE_LONG_RESET | FEATURE_SHORT_RESET) 119 #define FEATURE_ADDR_FULL (0 << 2) 120 #define FEATURE_ADDR_MASK (3 << 2) 121 #define FEATURE_ADDR_2AA (1 << 2) 122 #define FEATURE_ADDR_AAA (2 << 2) 123 #define FEATURE_ADDR_SHIFTED (1 << 5) 124 /* Feature bits used for SPI only */ 125 #define FEATURE_WRSR_EWSR (1 << 6) 126 #define FEATURE_WRSR_WREN (1 << 7) 127 #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) 128 #define FEATURE_OTP (1 << 8) 129 #define FEATURE_QPI (1 << 9) 130 #define FEATURE_4BA_ENTER (1 << 10) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN */ 131 #define FEATURE_4BA_ENTER_WREN (1 << 11) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN */ 132 #define FEATURE_4BA_ENTER_EAR7 (1 << 12) /**< Can enter/exit 4BA mode by setting bit7 of the ext addr reg */ 133 #define FEATURE_4BA_EAR_C5C8 (1 << 13) /**< Regular 3-byte operations can be used by writing the most 134 significant address byte into an extended address register 135 (using 0xc5/0xc8 instructions). */ 136 #define FEATURE_4BA_EAR_1716 (1 << 14) /**< Like FEATURE_4BA_EAR_C5C8 but with 0x17/0x16 instructions. */ 137 #define FEATURE_4BA_READ (1 << 15) /**< Native 4BA read instruction (0x13) is supported. */ 138 #define FEATURE_4BA_FAST_READ (1 << 16) /**< Native 4BA fast read instruction (0x0c) is supported. */ 139 #define FEATURE_4BA_WRITE (1 << 17) /**< Native 4BA byte program (0x12) is supported. */ 140 /* 4BA Shorthands */ 141 #define FEATURE_4BA_EAR_ANY (FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_EAR_1716) 142 #define FEATURE_4BA_NATIVE (FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE) 143 #define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) 144 #define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) 145 #define FEATURE_4BA_EAR7 (FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) 146 /* 147 * Most flash chips are erased to ones and programmed to zeros. However, some 148 * other flash chips, such as the ENE KB9012 internal flash, work the opposite way. 149 */ 150 #define FEATURE_ERASED_ZERO (1 << 18) 151 /* 152 * Feature indicates that the chip does not require erase before writing: 153 * write operations can set any bit to any value without first doing an erase, 154 * but bulk erase operations may still be supported. 155 * 156 * EEPROMs usually behave this way (compare to Flash, which requires erase), 157 * for example the ST M95M02. 158 */ 159 #define FEATURE_NO_ERASE (1 << 19) 160 161 #define FEATURE_WRSR_EXT2 (1 << 20) 162 #define FEATURE_WRSR2 (1 << 21) 163 #define FEATURE_WRSR_EXT3 ((1 << 22) | FEATURE_WRSR_EXT2) 164 #define FEATURE_WRSR3 (1 << 23) 165 166 /* 167 * Whether chip has security register (RDSCUR/WRSCUR commands). 168 * Not to be confused with "secure registers" of OTP. 169 */ 170 #define FEATURE_SCUR (1 << 24) 171 172 /* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */ 173 #define FEATURE_CFGR (1 << 25) 174 175 #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) 176 #define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00) 177 178 enum test_state { 179 OK = 0, 180 NT = 1, /* Not tested */ 181 BAD, /* Known to not work */ 182 DEP, /* Support depends on configuration (e.g. Intel flash descriptor) */ 183 NA, /* Not applicable (e.g. write support on ROM chips) */ 184 }; 185 186 #define TEST_UNTESTED (struct tested){ .probe = NT, .read = NT, .erase = NT, .write = NT, .wp = NT } 187 188 #define TEST_OK_PROBE (struct tested){ .probe = OK, .read = NT, .erase = NT, .write = NT, .wp = NT } 189 #define TEST_OK_PR (struct tested){ .probe = OK, .read = OK, .erase = NT, .write = NT, .wp = NT } 190 #define TEST_OK_PRE (struct tested){ .probe = OK, .read = OK, .erase = OK, .write = NT, .wp = NT } 191 #define TEST_OK_PREW (struct tested){ .probe = OK, .read = OK, .erase = OK, .write = OK, .wp = NT } 192 #define TEST_OK_PREWB (struct tested){ .probe = OK, .read = OK, .erase = OK, .write = OK, .wp = OK } 193 194 #define TEST_BAD_PROBE (struct tested){ .probe = BAD, .read = NT, .erase = NT, .write = NT, .wp = NT } 195 #define TEST_BAD_PR (struct tested){ .probe = BAD, .read = BAD, .erase = NT, .write = NT, .wp = NT } 196 #define TEST_BAD_PRE (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = NT, .wp = NT } 197 #define TEST_BAD_PREW (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = BAD, .wp = NT } 198 #define TEST_BAD_PREWB (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = BAD, .wp = BAD } 199 200 struct flashrom_flashctx; 201 #define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurrences. */ 202 typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); 203 204 enum flash_reg { 205 INVALID_REG = 0, 206 STATUS1, 207 STATUS2, 208 STATUS3, 209 SECURITY, 210 CONFIG, 211 MAX_REGISTERS 212 }; 213 214 struct reg_bit_info { 215 /* Register containing the bit */ 216 enum flash_reg reg; 217 218 /* Bit index within register */ 219 uint8_t bit_index; 220 221 /* 222 * Writability of the bit. RW does not guarantee the bit will be 223 * writable, for example if status register protection is enabled. 224 */ 225 enum { 226 RO, /* Read only */ 227 RW, /* Readable and writable */ 228 OTP /* One-time programmable */ 229 } writability; 230 }; 231 232 struct wp_bits; 233 234 enum decode_range_func { 235 NO_DECODE_RANGE_FUNC = 0, /* 0 indicates no range decode function is set. */ 236 DECODE_RANGE_SPI25 = 1, 237 DECODE_RANGE_SPI25_64K_BLOCK = 2, 238 DECODE_RANGE_SPI25_BIT_CMP = 3, 239 DECODE_RANGE_SPI25_2X_BLOCK = 4, 240 }; 241 typedef void (decode_range_func_t)(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); 242 243 enum probe_func { 244 NO_PROBE_FUNC = 0, /* 0 indicates no probe function set. */ 245 PROBE_JEDEC = 1, 246 PROBE_JEDEC_29GL, 247 PROBE_OPAQUE, 248 PROBE_EDI_KB9012, 249 PROBE_AT82802AB, 250 PROBE_W29EE011, 251 PROBE_EN29LV640B, 252 PROBE_SPI_AT25F, 253 PROBE_SPI_AT45DB, 254 PROBE_SPI_BIG_SPANSION, 255 PROBE_SPI_RDID, 256 PROBE_SPI_RDID4, 257 PROBE_SPI_REMS, 258 PROBE_SPI_RES1, 259 PROBE_SPI_RES2, 260 PROBE_SPI_SFDP, 261 PROBE_SPI_ST95, 262 }; 263 264 enum write_func { 265 NO_WRITE_FUNC = 0, /* 0 indicates no write function set. */ 266 WRITE_JEDEC = 1, 267 WRITE_JEDEC1, 268 WRITE_OPAQUE, 269 SPI_CHIP_WRITE1, 270 SPI_CHIP_WRITE256, 271 SPI_WRITE_AAI, 272 SPI_WRITE_AT45DB, 273 WRITE_28SF040, 274 WRITE_82802AB, 275 WRITE_EN29LV640B, 276 EDI_CHIP_WRITE, 277 TEST_WRITE_INJECTOR, /* special case must come last. */ 278 }; 279 typedef int (write_func_t)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); 280 281 enum read_func { 282 NO_READ_FUNC = 0, /* 0 indicates no read function set. */ 283 SPI_CHIP_READ = 1, 284 READ_OPAQUE, 285 READ_MEMMAPPED, 286 EDI_CHIP_READ, 287 SPI_READ_AT45DB, 288 SPI_READ_AT45DB_E8, 289 TEST_READ_INJECTOR, /* special case must come last. */ 290 }; 291 typedef int (read_func_t)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); 292 int read_flash(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); 293 294 enum block_erase_func { 295 NO_BLOCK_ERASE_FUNC = 0, /* 0 indicates no block erase function set. */ 296 SPI_BLOCK_ERASE_EMULATION = 1, 297 SPI_BLOCK_ERASE_20, 298 SPI_BLOCK_ERASE_21, 299 SPI_BLOCK_ERASE_40, 300 SPI_BLOCK_ERASE_50, 301 SPI_BLOCK_ERASE_52, 302 SPI_BLOCK_ERASE_53, 303 SPI_BLOCK_ERASE_5C, 304 SPI_BLOCK_ERASE_60, 305 SPI_BLOCK_ERASE_62, 306 SPI_BLOCK_ERASE_81, 307 SPI_BLOCK_ERASE_C4, 308 SPI_BLOCK_ERASE_C7, 309 SPI_BLOCK_ERASE_D7, 310 SPI_BLOCK_ERASE_D8, 311 SPI_BLOCK_ERASE_DB, 312 SPI_BLOCK_ERASE_DC, 313 S25FL_BLOCK_ERASE, 314 S25FS_BLOCK_ERASE_D8, 315 JEDEC_SECTOR_ERASE, 316 JEDEC_BLOCK_ERASE, 317 JEDEC_CHIP_BLOCK_ERASE, 318 OPAQUE_ERASE, 319 SPI_ERASE_AT45CS_SECTOR, 320 SPI_ERASE_AT45DB_BLOCK, 321 SPI_ERASE_AT45DB_CHIP, 322 SPI_ERASE_AT45DB_PAGE, 323 SPI_ERASE_AT45DB_SECTOR, 324 ERASE_CHIP_28SF040, 325 ERASE_SECTOR_28SF040, 326 ERASE_BLOCK_82802AB, 327 ERASE_SECTOR_49LFXXXC, 328 STM50_SECTOR_ERASE, 329 EDI_CHIP_BLOCK_ERASE, 330 CROS_EC_BLOCK_ERASE, 331 TEST_ERASE_INJECTOR, /* special case must come last. */ 332 }; 333 334 enum blockprotect_func { 335 NO_BLOCKPROTECT_FUNC = 0, /* 0 indicates no unlock function set. */ 336 SPI_DISABLE_BLOCKPROTECT, 337 SPI_DISABLE_BLOCKPROTECT_BP2_EP_SRWD, 338 SPI_DISABLE_BLOCKPROTECT_BP1_SRWD, 339 SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, 340 SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, 341 SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, 342 SPI_DISABLE_BLOCKPROTECT_AT45DB, 343 SPI_DISABLE_BLOCKPROTECT_AT25F, 344 SPI_DISABLE_BLOCKPROTECT_AT25FS010, 345 SPI_DISABLE_BLOCKPROTECT_AT25FS040, 346 SPI_DISABLE_BLOCKPROTECT_AT25F512A, 347 SPI_DISABLE_BLOCKPROTECT_AT25F512B, 348 SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT, 349 SPI_DISABLE_BLOCKPROTECT_AT2X_GLOBAL_UNPROTECT_SEC, 350 SPI_DISABLE_BLOCKPROTECT_SST26_GLOBAL_UNPROTECT, 351 SPI_DISABLE_BLOCKPROTECT_N25Q, 352 UNLOCK_REGSPACE2_BLOCK_ERASER_0, 353 UNLOCK_REGSPACE2_BLOCK_ERASER_1, 354 UNLOCK_REGSPACE2_UNIFORM_32K, 355 UNLOCK_REGSPACE2_UNIFORM_64K, 356 UNLOCK_28F004S5, 357 UNLOCK_LH28F008BJT, 358 UNLOCK_SST_FWHUB, 359 UNPROTECT_28SF040, 360 }; 361 362 enum printlock_func { 363 NO_PRINTLOCK_FUNC, 364 PRINTLOCK_AT49F, 365 PRINTLOCK_REGSPACE2_BLOCK_ERASER_0, 366 PRINTLOCK_REGSPACE2_BLOCK_ERASER_1, 367 PRINTLOCK_SST_FWHUB, 368 PRINTLOCK_W39F010, 369 PRINTLOCK_W39L010, 370 PRINTLOCK_W39L020, 371 PRINTLOCK_W39L040, 372 PRINTLOCK_W39V040A, 373 PRINTLOCK_W39V040B, 374 PRINTLOCK_W39V040C, 375 PRINTLOCK_W39V040FA, 376 PRINTLOCK_W39V040FB, 377 PRINTLOCK_W39V040FC, 378 PRINTLOCK_W39V080A, 379 PRINTLOCK_W39V080FA, 380 PRINTLOCK_W39V080FA_DUAL, 381 SPI_PRETTYPRINT_STATUS_REGISTER_AT25DF, 382 SPI_PRETTYPRINT_STATUS_REGISTER_AT25DF_SEC, 383 SPI_PRETTYPRINT_STATUS_REGISTER_AT25F, 384 SPI_PRETTYPRINT_STATUS_REGISTER_AT25F4096, 385 SPI_PRETTYPRINT_STATUS_REGISTER_AT25F512A, 386 SPI_PRETTYPRINT_STATUS_REGISTER_AT25F512B, 387 SPI_PRETTYPRINT_STATUS_REGISTER_AT25FS010, 388 SPI_PRETTYPRINT_STATUS_REGISTER_AT25FS040, 389 SPI_PRETTYPRINT_STATUS_REGISTER_AT26DF081A, 390 SPI_PRETTYPRINT_STATUS_REGISTER_AT45DB, 391 SPI_PRETTYPRINT_STATUS_REGISTER_BP1_SRWD, 392 SPI_PRETTYPRINT_STATUS_REGISTER_BP2_BPL, 393 SPI_PRETTYPRINT_STATUS_REGISTER_BP2_EP_SRWD, 394 SPI_PRETTYPRINT_STATUS_REGISTER_BP2_SRWD, 395 SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, 396 SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, 397 SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, 398 SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, 399 SPI_PRETTYPRINT_STATUS_REGISTER_DEFAULT_WELWIP, 400 SPI_PRETTYPRINT_STATUS_REGISTER_EN25S_WP, 401 SPI_PRETTYPRINT_STATUS_REGISTER_N25Q, 402 SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, 403 SPI_PRETTYPRINT_STATUS_REGISTER_SST25, 404 SPI_PRETTYPRINT_STATUS_REGISTER_SST25VF016, 405 SPI_PRETTYPRINT_STATUS_REGISTER_SST25VF040B, 406 }; 407 typedef int (printlockfunc_t)(struct flashctx *flash); 408 printlockfunc_t *lookup_printlock_func_ptr(struct flashctx *flash); 409 410 struct flashchip { 411 const char *vendor; 412 const char *name; 413 414 enum chipbustype bustype; 415 416 /* 417 * With 32bit manufacture_id and model_id we can cover IDs up to 418 * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's 419 * Identification code. 420 */ 421 uint32_t manufacture_id; 422 uint32_t model_id; 423 424 /* Total chip size in kilobytes */ 425 unsigned int total_size; 426 /* Chip page size in bytes */ 427 unsigned int page_size; 428 int feature_bits; 429 430 /* Indicate how well flashrom supports different operations of this flash chip. */ 431 struct tested { 432 enum test_state probe; 433 enum test_state read; 434 enum test_state erase; 435 enum test_state write; 436 enum test_state wp; 437 } tested; 438 439 /* 440 * Group chips that have common command sets. This should ensure that 441 * no chip gets confused by a probing command for a very different class 442 * of chips. 443 */ 444 enum { 445 /* SPI25 is very common. Keep it at zero so we don't have 446 to specify it for each and every chip in the database.*/ 447 SPI25 = 0, 448 SPI_EDI = 1, 449 } spi_cmd_set; 450 451 enum probe_func probe; 452 453 /* Delay after "enter/exit ID mode" commands in microseconds. 454 * NB: negative values have special meanings, see TIMING_* below. 455 */ 456 signed int probe_timing; 457 458 /* 459 * Erase blocks and associated erase function. Any chip erase function 460 * is stored as chip-sized virtual block together with said function. 461 * The logic for how to optimally select erase functions is in erasure_layout.c 462 */ 463 struct block_eraser { 464 struct eraseblock { 465 unsigned int size; /* Eraseblock size in bytes */ 466 unsigned int count; /* Number of contiguous blocks with that size */ 467 } eraseblocks[NUM_ERASEREGIONS]; 468 /* a block_erase function should try to erase one block of size 469 * 'blocklen' at address 'blockaddr' and return 0 on success. */ 470 enum block_erase_func block_erase; 471 } block_erasers[NUM_ERASEFUNCTIONS]; 472 473 enum printlock_func printlock; 474 enum blockprotect_func unlock; 475 enum write_func write; 476 enum read_func read; 477 struct voltage { 478 uint16_t min; 479 uint16_t max; 480 } voltage; 481 enum write_granularity gran; 482 483 struct reg_bit_map { 484 /* Status register protection bit (SRP) */ 485 struct reg_bit_info srp; 486 487 /* Status register lock bit (SRP) */ 488 struct reg_bit_info srl; 489 490 /* 491 * Note: some datasheets refer to configuration bits that 492 * function like TB/SEC/CMP bits as BP bits (e.g. BP3 for a bit 493 * that functions like TB). 494 * 495 * As a convention, any config bit that functions like a 496 * TB/SEC/CMP bit should be assigned to the respective 497 * tb/sec/cmp field in this structure, even if the datasheet 498 * uses a different name. 499 */ 500 501 /* Block protection bits (BP) */ 502 /* Extra element for terminator */ 503 struct reg_bit_info bp[MAX_BP_BITS + 1]; 504 505 /* Top/bottom protection bit (TB) */ 506 struct reg_bit_info tb; 507 508 /* Sector/block protection bit (SEC) */ 509 struct reg_bit_info sec; 510 511 /* Complement bit (CMP) */ 512 struct reg_bit_info cmp; 513 514 /* Write Protect Selection (per sector protection when set) */ 515 struct reg_bit_info wps; 516 } reg_bits; 517 518 /* 519 * Function that takes a set of WP config bits (e.g. BP, SEC, TB, etc) 520 * and determines what protection range they select. 521 */ 522 enum decode_range_func decode_range; 523 }; 524 525 typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, void *data); 526 typedef int (blockprotect_func_t)(struct flashctx *flash); 527 blockprotect_func_t *lookup_blockprotect_func_ptr(const struct flashchip *const chip); 528 529 struct flashrom_flashctx { 530 struct flashchip *chip; 531 /* FIXME: The memory mappings should be saved in a more structured way. */ 532 /* The physical_* fields store the respective addresses in the physical address space of the CPU. */ 533 uintptr_t physical_memory; 534 /* The virtual_* fields store where the respective physical address is mapped into flashrom's address 535 * space. A value equivalent to (chipaddr)ERROR_PTR indicates an invalid mapping (or none at all). */ 536 chipaddr virtual_memory; 537 /* Some flash devices have an additional register space; semantics are like above. */ 538 uintptr_t physical_registers; 539 chipaddr virtual_registers; 540 struct registered_master *mst; 541 const struct flashrom_layout *layout; 542 struct flashrom_layout *default_layout; 543 struct { 544 bool force; 545 bool force_boardmismatch; 546 bool verify_after_write; 547 bool verify_whole_chip; 548 bool skip_unreadable_regions; 549 bool skip_unwritable_regions; 550 } flags; 551 /* We cache the state of the extended address register (highest byte 552 * of a 4BA for 3BA instructions) and the state of the 4BA mode here. 553 * If possible, we enter 4BA mode early. If that fails, we make use 554 * of the extended address register. 555 */ 556 int address_high_byte; 557 bool in_4ba_mode; 558 559 int chip_restore_fn_count; 560 struct chip_restore_func_data { 561 chip_restore_fn_cb_t func; 562 void *data; 563 } chip_restore_fn[MAX_CHIP_RESTORE_FUNCTIONS]; 564 /* Progress reporting */ 565 flashrom_progress_callback *progress_callback; 566 struct flashrom_progress *progress_state; 567 }; 568 569 /* Timing used in probe routines. ZERO is -2 to differentiate between an unset 570 * field and zero delay. 571 * 572 * SPI devices will always have zero delay and ignore this field. 573 */ 574 #define TIMING_FIXME -1 575 /* this is intentionally same value as fixme */ 576 #define TIMING_IGNORED -1 577 #define TIMING_ZERO -2 578 579 extern const struct flashchip flashchips[]; 580 extern const unsigned int flashchips_size; 581 582 /* parallel.c */ 583 void chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); 584 void chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr); 585 void chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr); 586 void chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len); 587 uint8_t chip_readb(const struct flashctx *flash, const chipaddr addr); 588 uint16_t chip_readw(const struct flashctx *flash, const chipaddr addr); 589 uint32_t chip_readl(const struct flashctx *flash, const chipaddr addr); 590 void chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); 591 592 /* print.c */ 593 int print_supported(void); 594 void print_supported_wiki(void); 595 596 /* helpers.c */ 597 uint32_t address_to_bits(uint32_t addr); 598 unsigned int bitcount(unsigned long a); 599 #undef MIN 600 #define MIN(a, b) ((a) < (b) ? (a) : (b)) 601 #undef MAX 602 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 603 int max(int a, int b); 604 int min(int a, int b); 605 char *strcat_realloc(char *dest, const char *src); 606 void tolower_string(char *str); 607 uint8_t reverse_byte(uint8_t x); 608 void reverse_bytes(uint8_t *dst, const uint8_t *src, size_t length); 609 #ifdef __MINGW32__ 610 char* strtok_r(char *str, const char *delim, char **nextp); 611 char *strndup(const char *str, size_t size); 612 #endif 613 #if defined(__DJGPP__) || (!defined(__LIBPAYLOAD__) && !defined(HAVE_STRNLEN)) 614 size_t strnlen(const char *str, size_t n); 615 #endif 616 617 /* flashchips_crosbl.c */ 618 bool is_chipname_duplicate(const struct flashchip *chip); 619 620 /* flashrom.c */ 621 extern const char flashrom_version[]; 622 char *flashbuses_to_text(enum chipbustype bustype); 623 int map_flash(struct flashctx *flash); 624 void unmap_flash(struct flashctx *flash); 625 int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); 626 int erase_flash(struct flashctx *flash); 627 int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force, const char *const chip_to_probe); 628 int verify_range(struct flashctx *flash, const uint8_t *cmpbuf, unsigned int start, unsigned int len); 629 void emergency_help_message(void); 630 void print_version(void); 631 void print_buildinfo(void); 632 void print_banner(void); 633 void list_programmers_linebreak(int startcol, int cols, int paren); 634 int selfcheck(void); 635 int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename); 636 int write_buf_to_file(const unsigned char *buf, unsigned long size, const char *filename); 637 int prepare_flash_access(struct flashctx *, bool read_it, bool write_it, bool erase_it, bool verify_it); 638 void finalize_flash_access(struct flashctx *); 639 int register_chip_restore(chip_restore_fn_cb_t func, struct flashctx *flash, void *data); 640 int check_block_eraser(const struct flashctx *flash, int k, int log); 641 unsigned int count_usable_erasers(const struct flashctx *flash); 642 int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, enum write_granularity gran, const uint8_t erased_value); 643 erasefunc_t *lookup_erase_func_ptr(const struct block_eraser *const eraser); 644 int check_erased_range(struct flashctx *flash, unsigned int start, unsigned int len); 645 unsigned int get_next_write(const uint8_t *have, const uint8_t *want, unsigned int len, unsigned int *first_start, enum write_granularity gran); 646 int write_flash(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); 647 648 erasefunc_t *lookup_erase_func_ptr(const struct block_eraser *const eraser); 649 650 /* Something happened that shouldn't happen, but we can go on. */ 651 #define ERROR_FLASHROM_NONFATAL 0x100 652 653 /* Something happened that shouldn't happen, we'll abort. */ 654 #define ERROR_FLASHROM_FATAL -0xee 655 #define ERROR_FLASHROM_BUG -200 656 /* We reached one of the hardcoded limits of flashrom. This can be fixed by 657 * increasing the limit of a compile-time allocation or by switching to dynamic 658 * allocation. 659 * Note: If this warning is triggered, check first for runaway registrations. 660 */ 661 #define ERROR_FLASHROM_LIMIT -201 662 663 /* cli_common.c */ 664 void print_chip_support_status(const struct flashchip *chip); 665 666 /* cli_output.c */ 667 extern enum flashrom_log_level verbose_screen; 668 extern enum flashrom_log_level verbose_logfile; 669 int open_logfile(const char * const filename); 670 int close_logfile(void); 671 void start_logging(void); 672 int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap); 673 void flashrom_progress_cb(struct flashrom_flashctx *flashctx); 674 /* Let gcc and clang check for correct printf-style format strings. */ 675 int print(enum flashrom_log_level level, const char *fmt, ...) 676 #ifdef __MINGW32__ 677 # ifndef __MINGW_PRINTF_FORMAT 678 # define __MINGW_PRINTF_FORMAT gnu_printf 679 # endif 680 __attribute__((format(__MINGW_PRINTF_FORMAT, 2, 3))); 681 #else 682 __attribute__((format(printf, 2, 3))); 683 #endif 684 #define msg_gerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* general errors */ 685 #define msg_perr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* programmer errors */ 686 #define msg_cerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* chip errors */ 687 #define msg_gwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* general warnings */ 688 #define msg_pwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* programmer warnings */ 689 #define msg_cwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* chip warnings */ 690 #define msg_ginfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* general info */ 691 #define msg_pinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* programmer info */ 692 #define msg_cinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* chip info */ 693 #define msg_gdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* general debug */ 694 #define msg_pdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* programmer debug */ 695 #define msg_cdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* chip debug */ 696 #define msg_gdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* general debug2 */ 697 #define msg_pdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* programmer debug2 */ 698 #define msg_cdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ 699 #define msg_gspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* general debug spew */ 700 #define msg_pspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ 701 #define msg_cspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* chip debug spew */ 702 void update_progress(struct flashctx *flash, enum flashrom_progress_stage stage, size_t current, size_t total); 703 704 /* spi.c */ 705 struct spi_command { 706 unsigned int writecnt; 707 unsigned int readcnt; 708 const unsigned char *writearr; 709 unsigned char *readarr; 710 }; 711 #define NULL_SPI_CMD { 0, 0, NULL, NULL, } 712 int spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); 713 int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds); 714 715 enum chipbustype get_buses_supported(void); 716 #endif /* !__FLASH_H__ */ 717