1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <[email protected]>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #ifndef __PROGRAMMER_H__
21 #define __PROGRAMMER_H__ 1
22
23 #include <stdbool.h>
24 #include <stdint.h>
25
26 #include "flash.h" /* for chipaddr and flashctx */
27
28
29 /*
30 * This function returns 'true' if current flashrom invocation is programming
31 * the EC.
32 */
33 bool programming_ec(void);
34
35 enum programmer_type {
36 PCI = 1, /* to detect uninitialized values */
37 USB,
38 OTHER,
39 };
40 struct board_cfg;
41 struct programmer_cfg {
42 char *params;
43 struct board_cfg *bcfg;
44 };
45
46 struct dev_entry {
47 uint16_t vendor_id;
48 uint16_t device_id;
49 const enum test_state status;
50 const char *vendor_name;
51 const char *device_name;
52 };
53
54 struct programmer_entry {
55 const char *name;
56 const enum programmer_type type;
57 union {
58 const struct dev_entry *const dev;
59 const char *const note;
60 } devs;
61
62 int (*init) (const struct programmer_cfg *cfg);
63 };
64
65 extern const struct programmer_entry *const programmer_table[];
66 extern const size_t programmer_table_size;
67
68 /* programmer drivers */
69 extern const struct programmer_entry programmer_asm106x;
70 extern const struct programmer_entry programmer_atahpt;
71 extern const struct programmer_entry programmer_atapromise;
72 extern const struct programmer_entry programmer_atavia;
73 extern const struct programmer_entry programmer_buspirate_spi;
74 extern const struct programmer_entry programmer_ch341a_spi;
75 extern const struct programmer_entry programmer_ch347_spi;
76 extern const struct programmer_entry programmer_dediprog;
77 extern const struct programmer_entry programmer_developerbox;
78 extern const struct programmer_entry programmer_digilent_spi;
79 extern const struct programmer_entry programmer_drkaiser;
80 extern const struct programmer_entry programmer_dummy;
81 extern const struct programmer_entry programmer_ft2232_spi;
82 extern const struct programmer_entry programmer_gfxnvidia;
83 extern const struct programmer_entry programmer_internal;
84 extern const struct programmer_entry programmer_it8212;
85 extern const struct programmer_entry programmer_jlink_spi;
86 extern const struct programmer_entry programmer_linux_mtd;
87 extern const struct programmer_entry programmer_linux_spi;
88 extern const struct programmer_entry programmer_parade_lspcon;
89 extern const struct programmer_entry programmer_mediatek_i2c_spi;
90 extern const struct programmer_entry programmer_mstarddc_spi;
91 extern const struct programmer_entry programmer_ni845x_spi;
92 extern const struct programmer_entry programmer_nic3com;
93 extern const struct programmer_entry programmer_nicintel;
94 extern const struct programmer_entry programmer_nicintel_eeprom;
95 extern const struct programmer_entry programmer_nicintel_spi;
96 extern const struct programmer_entry programmer_nicnatsemi;
97 extern const struct programmer_entry programmer_nicrealtek;
98 extern const struct programmer_entry programmer_ogp_spi;
99 extern const struct programmer_entry programmer_pickit2_spi;
100 extern const struct programmer_entry programmer_pony_spi;
101 extern const struct programmer_entry programmer_raiden_debug_spi;
102 extern const struct programmer_entry programmer_rayer_spi;
103 extern const struct programmer_entry programmer_realtek_mst_i2c_spi;
104 extern const struct programmer_entry programmer_satamv;
105 extern const struct programmer_entry programmer_satasii;
106 extern const struct programmer_entry programmer_serprog;
107 extern const struct programmer_entry programmer_stlinkv3_spi;
108 extern const struct programmer_entry programmer_usbblaster_spi;
109 extern const struct programmer_entry programmer_dirtyjtag_spi;
110
111 extern const struct programmer_entry programmer_cros_ec;
112
113 int programmer_init(const struct programmer_entry *prog, const char *param);
114 int programmer_shutdown(void);
115
116 struct bitbang_spi_master {
117 /* Note that CS# is active low, so val=0 means the chip is active. */
118 void (*set_cs) (int val, void *spi_data);
119 void (*set_sck) (int val, void *spi_data);
120 void (*set_mosi) (int val, void *spi_data);
121 int (*get_miso) (void *spi_data);
122 void (*request_bus) (void *spi_data);
123 void (*release_bus) (void *spi_data);
124 /* optional functions to optimize xfers */
125 void (*set_sck_set_mosi) (int sck, int mosi, void *spi_data);
126 int (*set_sck_get_miso) (int sck, void *spi_data);
127 /* Length of half a clock period in usecs. */
128 unsigned int half_period;
129 };
130
131 struct pci_dev;
132 struct pci_filter;
133
134 /* pcidev.c */
135 // FIXME: This needs to be local, not global(?)
136 extern struct pci_access *pacc;
137 int pci_init_common(void);
138 uintptr_t pcidev_readbar(struct pci_dev *dev, int bar);
139 struct pci_dev *pcidev_init(const struct programmer_cfg *cfg, const struct dev_entry *devs, int bar);
140 struct pci_dev *pcidev_scandev(struct pci_filter *filter, struct pci_dev *start);
141 struct pci_dev *pcidev_getdevfn(struct pci_dev *dev, const int func);
142 struct pci_dev *pcidev_find_vendorclass(uint16_t vendor, uint16_t devclass);
143 struct pci_dev *pcidev_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device);
144 struct pci_dev *pcidev_find(uint16_t vendor, uint16_t device);
145 /* rpci_write_* are reversible writes. The original PCI config space register
146 * contents will be restored on shutdown.
147 * To clone the pci_dev instances internally, the `pacc` global
148 * variable has to reference a pci_access method that is compatible
149 * with the given pci_dev handle. The referenced pci_access (not
150 * the variable) has to stay valid until the shutdown handlers are
151 * finished.
152 */
153 int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
154 int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
155 int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
156
157 #if CONFIG_INTERNAL == 1
158 struct penable {
159 uint16_t vendor_id;
160 uint16_t device_id;
161 enum chipbustype buses;
162 const enum test_state status;
163 const char *vendor_name;
164 const char *device_name;
165 int (*doit) (const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name);
166 };
167
168 extern const struct penable chipset_enables[];
169
170 enum board_match_phase {
171 P1,
172 P2,
173 P3
174 };
175
176 struct board_cfg {
177 int is_laptop;
178 bool laptop_ok;
179 };
180
181 struct board_match {
182 /* Any device, but make it sensible, like the ISA bridge. */
183 uint16_t first_vendor;
184 uint16_t first_device;
185 uint16_t first_card_vendor;
186 uint16_t first_card_device;
187
188 /* Any device, but make it sensible, like
189 * the host bridge. May be NULL.
190 */
191 uint16_t second_vendor;
192 uint16_t second_device;
193 uint16_t second_card_vendor;
194 uint16_t second_card_device;
195
196 /* Pattern to match DMI entries. May be NULL. */
197 const char *dmi_pattern;
198
199 /* The vendor / part name from the coreboot table. May be NULL. */
200 const char *lb_vendor;
201 const char *lb_part;
202
203 enum board_match_phase phase;
204
205 const char *vendor_name;
206 const char *board_name;
207
208 int max_rom_decode_parallel;
209 const enum test_state status;
210 int (*enable) (struct board_cfg *cfg); /* May be NULL. */
211 };
212
213 extern const struct board_match board_matches[];
214 extern const size_t board_matches_size;
215
216 struct board_info {
217 const char *vendor;
218 const char *name;
219 const enum test_state working;
220 #ifdef CONFIG_PRINT_WIKI
221 const char *url;
222 const char *note;
223 #endif
224 };
225
226 extern const struct board_info boards_known[];
227 extern const struct board_info laptops_known[];
228 #endif
229
230 /* udelay.c */
231 void internal_sleep(unsigned int usecs);
232 void default_delay(unsigned int usecs);
233
234 #if CONFIG_INTERNAL == 1
235 /* board_enable.c */
236 int selfcheck_board_enables(void);
237 int board_parse_parameter(const char *boardstring, char **vendor, char **model);
238 void w836xx_ext_enter(uint16_t port);
239 void w836xx_ext_leave(uint16_t port);
240 void probe_superio_winbond(void);
241 int it8705f_write_enable(uint8_t port);
242 uint8_t sio_read(uint16_t port, uint8_t reg);
243 void sio_write(uint16_t port, uint8_t reg, uint8_t data);
244 void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
245 void board_handle_before_superio(struct board_cfg *cfg, bool force_boardenable);
246 void board_handle_before_laptop(struct board_cfg *cfg, bool force_boardenable);
247 int board_flash_enable(struct board_cfg *cfg, const char *vendor, const char *model, const char *cb_vendor, const char *cb_model, bool force_boardenable);
248
249 /* chipset_enable.c */
250 int chipset_flash_enable(const struct programmer_cfg *cfg);
251
252 /* processor_enable.c */
253 int processor_flash_enable(void);
254 #endif
255
256 #if CONFIG_INTERNAL == 1
257 /* cbtable.c */
258 int cb_parse_table(const char **vendor, const char **model);
259 int cb_check_image(const uint8_t *bios, unsigned int size);
260
261 /* dmi.c */
262 #if defined(__i386__) || defined(__x86_64__)
263 void dmi_init(int *is_laptop);
264 bool dmi_is_supported(void);
265 int dmi_match(const char *pattern);
266 #endif // defined(__i386__) || defined(__x86_64__)
267
268 /* internal.c */
269 struct superio {
270 uint16_t vendor;
271 uint16_t port;
272 uint16_t model;
273 };
274 extern struct superio superios[];
275 extern int superio_count;
276 #define SUPERIO_VENDOR_NONE 0x0
277 #define SUPERIO_VENDOR_ITE 0x1
278 #define SUPERIO_VENDOR_WINBOND 0x2
279 #endif
280
281 #if CONFIG_INTERNAL == 1
282 extern bool force_boardmismatch;
283 void probe_superio(void);
284 int register_superio(struct superio s);
285 extern enum chipbustype internal_buses_supported;
286 int internal_init(const struct programmer_cfg *cfg);
287 #endif
288
289 /* bitbang_spi.c */
290 int register_spi_bitbang_master(const struct bitbang_spi_master *master, void *spi_data);
291
292
293 /* flashrom.c */
294 struct decode_sizes {
295 uint32_t parallel;
296 uint32_t lpc;
297 uint32_t fwh;
298 uint32_t spi;
299 };
300 // FIXME: These need to be local, not global
301 extern struct decode_sizes max_rom_decode;
302 extern bool programmer_may_write;
303 extern uintptr_t flashbase; /* used in programmer_enable.c */
304 char *extract_programmer_param_str(const struct programmer_cfg *cfg, const char *param_name);
305
306 /* spi.c */
307 #define MAX_DATA_UNSPECIFIED 0
308 #define MAX_DATA_READ_UNLIMITED 64 * 1024
309 #define MAX_DATA_WRITE_UNLIMITED 256
310
311 #define SPI_MASTER_4BA (1U << 0) /**< Can handle 4-byte addresses */
312 #define SPI_MASTER_NO_4BA_MODES (1U << 1) /**< Compatibility modes (i.e. extended address
313 register, 4BA mode switch) don't work */
314
315 struct spi_master {
316 uint32_t features;
317 unsigned int max_data_read; // (Ideally,) maximum data read size in one go (excluding opcode+address).
318 unsigned int max_data_write; // (Ideally,) maximum data write size in one go (excluding opcode+address).
319 int (*command)(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
320 const unsigned char *writearr, unsigned char *readarr);
321 int (*multicommand)(const struct flashctx *flash, struct spi_command *cmds);
322
323 /* Optimized functions for this master */
324 void *(*map_flash_region) (const char *descr, uintptr_t phys_addr, size_t len);
325 void (*unmap_flash_region) (void *virt_addr, size_t len);
326 int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
327 int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
328 int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
329 int (*shutdown)(void *data);
330 bool (*probe_opcode)(const struct flashctx *flash, uint8_t opcode); /* NULL func implies true. */
331 void (*delay) (const struct flashctx *flash, unsigned int usecs);
332 void (*get_region)(const struct flashctx *flash, unsigned int addr, struct flash_region *region);
333 void *data;
334 };
335
336 int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
337 int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
338 int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
339 int register_spi_master(const struct spi_master *mst, void *data);
340
341 /* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */
342 enum ich_chipset {
343 CHIPSET_ICH_UNKNOWN,
344 CHIPSET_ICH,
345 CHIPSET_ICH2345,
346 CHIPSET_ICH6,
347 CHIPSET_POULSBO, /* SCH U* */
348 CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
349 CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
350 CHIPSET_ICH7,
351 CHIPSET_ICH8,
352 CHIPSET_ICH9,
353 CHIPSET_ICH10,
354 CHIPSET_5_SERIES_IBEX_PEAK,
355 CHIPSET_6_SERIES_COUGAR_POINT,
356 CHIPSET_7_SERIES_PANTHER_POINT,
357 CHIPSET_8_SERIES_LYNX_POINT,
358 CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */
359 CHIPSET_8_SERIES_LYNX_POINT_LP,
360 CHIPSET_8_SERIES_WELLSBURG,
361 CHIPSET_9_SERIES_WILDCAT_POINT,
362 CHIPSET_9_SERIES_WILDCAT_POINT_LP,
363 CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
364 CHIPSET_C620_SERIES_LEWISBURG,
365 CHIPSET_C740_SERIES_EMMITSBURG,
366 CHIPSET_300_SERIES_CANNON_POINT,
367 CHIPSET_400_SERIES_COMET_POINT,
368 CHIPSET_500_SERIES_TIGER_POINT,
369 CHIPSET_600_SERIES_ALDER_POINT,
370 CHIPSET_700_SERIES_RAPTOR_POINT,
371 CHIPSET_APOLLO_LAKE,
372 CHIPSET_GEMINI_LAKE,
373 CHIPSET_JASPER_LAKE,
374 CHIPSET_ELKHART_LAKE,
375 /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */
376 CHIPSET_METEOR_LAKE,
377 CHIPSET_PANTHER_LAKE,
378 };
379
380 /* ichspi.c */
381 #if CONFIG_INTERNAL == 1
382 int ich_init_spi(const struct programmer_cfg *cfg, void *spibar, enum ich_chipset ich_generation);
383 int via_init_spi(uint32_t mmio_base);
384
385 /* amd_imc.c */
386 int amd_imc_shutdown(struct pci_dev *dev);
387
388 /* it87spi.c */
389 void enter_conf_mode_ite(uint16_t port);
390 void exit_conf_mode_ite(uint16_t port);
391 void probe_superio_ite(void);
392 int init_superio_ite(const struct programmer_cfg *cfg);
393
394 /* trivial wrapper to avoid cluttering internal_init() with #if */
try_mtd(const struct programmer_cfg * cfg)395 static inline int try_mtd(const struct programmer_cfg *cfg)
396 {
397 #if CONFIG_LINUX_MTD == 1
398 return programmer_linux_mtd.init(cfg);
399 #else
400 return 1;
401 #endif
402 }
403
404 /* mcp6x_spi.c */
405 int mcp6x_spi_init(int want_spi);
406
407 /* internal_par.c */
408 void internal_par_init(enum chipbustype buses);
409
410 /* sb600spi.c */
411 int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev);
412
413 /* wbsio_spi.c */
414 int wbsio_check_for_spi(struct board_cfg *);
415 #endif
416
417 /* opaque.c */
418 struct opaque_master {
419 int max_data_read;
420 int max_data_write;
421 /* Specific functions for this master */
422 int (*probe) (struct flashctx *flash);
423 int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
424 int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
425 int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen);
426 /*
427 * Callbacks for accessing flash registers. An opaque programmer must
428 * provide these functions for writeprotect operations to be available,
429 * unless it provides custom wp operations instead.
430 */
431 int (*read_register)(const struct flashctx *flash, enum flash_reg reg, uint8_t *value);
432 int (*write_register)(const struct flashctx *flash, enum flash_reg reg, uint8_t value);
433 /* Callbacks for overiding default writeprotect operations with custom ones. */
434 enum flashrom_wp_result (*wp_write_cfg)(struct flashctx *, const struct flashrom_wp_cfg *);
435 enum flashrom_wp_result (*wp_read_cfg)(struct flashrom_wp_cfg *, struct flashctx *);
436 enum flashrom_wp_result (*wp_get_ranges)(struct flashrom_wp_ranges **, struct flashctx *);
437 void (*get_region)(const struct flashctx *flash, unsigned int addr, struct flash_region *region);
438 int (*shutdown)(void *data);
439 void (*delay) (const struct flashctx *flash, unsigned int usecs);
440 void *data;
441 };
442 int register_opaque_master(const struct opaque_master *mst, void *data);
443
444 /* parallel.c */
445 struct par_master {
446 void *(*map_flash_region) (const char *descr, uintptr_t phys_addr, size_t len);
447 void (*unmap_flash_region) (void *virt_addr, size_t len);
448 void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr);
449 void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr);
450 void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr);
451 void (*chip_writen) (const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
452 uint8_t (*chip_readb) (const struct flashctx *flash, const chipaddr addr);
453 uint16_t (*chip_readw) (const struct flashctx *flash, const chipaddr addr);
454 uint32_t (*chip_readl) (const struct flashctx *flash, const chipaddr addr);
455 void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
456 int (*shutdown)(void *data);
457 void (*delay) (const struct flashctx *flash, unsigned int usecs);
458 void *data;
459 };
460 int register_par_master(const struct par_master *mst, const enum chipbustype buses, void *data);
461
462 /* programmer.c */
463 struct registered_master {
464 enum chipbustype buses_supported;
465 struct {
466 struct par_master par;
467 struct spi_master spi;
468 struct opaque_master opaque;
469 };
470 };
471 extern struct registered_master registered_masters[];
472 extern int registered_master_count;
473 int register_master(const struct registered_master *mst);
474
475
476
477 /* serial.c */
478 #if IS_WINDOWS
479 typedef HANDLE fdtype;
480 #define SER_INV_FD INVALID_HANDLE_VALUE
481 #else
482 typedef int fdtype;
483 #define SER_INV_FD -1
484 #endif
485
486 /* cros_ec.c */
487 /**
488 * Probe the Google Chrome OS EC device
489 *
490 * @return 0 if found correct, non-zero if not found or error
491 */
492 int cros_ec_need_2nd_pass(void);
493 bool cros_ec_erasure_failed(void);
494 int cros_ec_finish(void);
495 int cros_ec_prepare(struct flashctx *flash, const uint8_t *const image, uint32_t flash_size);
496 int cros_ec_block_erase(struct flashctx *flash, unsigned int blockaddr, unsigned int len);
497
498 void sp_flush_incoming(void);
499 fdtype sp_openserport(char *dev, int baud);
500 extern fdtype sp_fd;
501 int serialport_config(fdtype fd, int baud);
502 int serialport_shutdown(void *data);
503 int serialport_write(const unsigned char *buf, unsigned int writecnt);
504 int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, unsigned int timeout, unsigned int *really_wrote);
505 int serialport_read(unsigned char *buf, unsigned int readcnt);
506 int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned int timeout, unsigned int *really_read);
507
508 /* Serial port/pin mapping:
509
510 1 CD <-
511 2 RXD <-
512 3 TXD ->
513 4 DTR ->
514 5 GND --
515 6 DSR <-
516 7 RTS ->
517 8 CTS <-
518 9 RI <-
519 */
520 enum SP_PIN {
521 PIN_CD = 1,
522 PIN_RXD,
523 PIN_TXD,
524 PIN_DTR,
525 PIN_GND,
526 PIN_DSR,
527 PIN_RTS,
528 PIN_CTS,
529 PIN_RI,
530 };
531
532 void sp_set_pin(enum SP_PIN pin, int val);
533 int sp_get_pin(enum SP_PIN pin);
534
535 /* spi_master feature checks */
spi_master_4ba(const struct flashctx * const flash)536 static inline bool spi_master_4ba(const struct flashctx *const flash)
537 {
538 return flash->mst->buses_supported & BUS_SPI &&
539 flash->mst->spi.features & SPI_MASTER_4BA;
540 }
spi_master_no_4ba_modes(const struct flashctx * const flash)541 static inline bool spi_master_no_4ba_modes(const struct flashctx *const flash)
542 {
543 return flash->mst->buses_supported & BUS_SPI &&
544 flash->mst->spi.features & SPI_MASTER_NO_4BA_MODES;
545 }
546 /* spi_chip feature checks */
spi_chip_4ba(const struct flashctx * const flash)547 static inline bool spi_chip_4ba(const struct flashctx *const flash)
548 {
549 return flash->chip->bustype == BUS_SPI &&
550 (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_ENTER_EAR7));
551 }
552
553 /* usbdev.c */
554 struct libusb_device_handle;
555 struct libusb_context;
556 struct libusb_device_handle *usb_dev_get_by_vid_pid_serial(
557 struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, const char *serialno);
558 struct libusb_device_handle *usb_dev_get_by_vid_pid_number(
559 struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, unsigned int num);
560
561
562 #endif /* !__PROGRAMMER_H__ */
563