1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Peter Stuge <[email protected]>
5 * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <stdlib.h>
18
19 #include "flash.h"
20 #include "chipdrivers.h"
21 #include "programmer.h"
22 #include "hwaccess_physmap.h"
23 #include "hwaccess_x86_io.h"
24 #include "spi.h"
25
26 #define WBSIO_PORT1 0x2e
27 #define WBSIO_PORT2 0x4e
28
29 struct wbsio_spi_data {
30 uint16_t spibase;
31 };
32
wbsio_get_spibase(uint16_t port)33 static uint16_t wbsio_get_spibase(uint16_t port)
34 {
35 uint8_t id;
36 uint16_t flashport = 0;
37
38 w836xx_ext_enter(port);
39 id = sio_read(port, 0x20);
40 if (id != 0xa0) {
41 msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
42 goto done;
43 }
44
45 if (0 == (sio_read(port, 0x24) & 2)) {
46 msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
47 goto done;
48 }
49
50 sio_write(port, 0x07, 0x06);
51 if (0 == (sio_read(port, 0x30) & 1)) {
52 msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
53 goto done;
54 }
55
56 flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63);
57
58 done:
59 w836xx_ext_leave(port);
60 return flashport;
61 }
62
63 /* W83627DHG has 11 command modes:
64 * 1=1 command only
65 * 2=1 command+1 data write
66 * 3=1 command+2 data read
67 * 4=1 command+3 address
68 * 5=1 command+3 address+1 data write
69 * 6=1 command+3 address+4 data write
70 * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read
71 * 8=1 command+3 address+1 data read
72 * 9=1 command+3 address+2 data read
73 * a=1 command+3 address+3 data read
74 * b=1 command+3 address+4 data read
75 *
76 * mode[7:4] holds the command mode
77 * mode[3:0] holds SPI address bits [19:16]
78 *
79 * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\
80 * Would one more byte of RAM in the chip (to get all 24 bits) really make
81 * such a big difference?
82 */
wbsio_spi_send_command(const struct flashctx * flash,unsigned int writecnt,unsigned int readcnt,const unsigned char * writearr,unsigned char * readarr)83 static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
84 unsigned int readcnt,
85 const unsigned char *writearr,
86 unsigned char *readarr)
87 {
88 unsigned int i;
89 uint8_t mode = 0;
90
91 msg_pspew("%s:", __func__);
92
93 const struct wbsio_spi_data *data =
94 (const struct wbsio_spi_data *)flash->mst->spi.data;
95
96 if (1 == writecnt && 0 == readcnt) {
97 mode = 0x10;
98 } else if (2 == writecnt && 0 == readcnt) {
99 OUTB(writearr[1], data->spibase + 4);
100 msg_pspew(" data=0x%02x", writearr[1]);
101 mode = 0x20;
102 } else if (1 == writecnt && 2 == readcnt) {
103 mode = 0x30;
104 } else if (4 == writecnt && 0 == readcnt) {
105 msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
106 for (i = 2; i < writecnt; i++) {
107 OUTB(writearr[i], data->spibase + i);
108 msg_pspew("%02x", writearr[i]);
109 }
110 mode = 0x40 | (writearr[1] & 0x0f);
111 } else if (5 == writecnt && 0 == readcnt) {
112 msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
113 for (i = 2; i < 4; i++) {
114 OUTB(writearr[i], data->spibase + i);
115 msg_pspew("%02x", writearr[i]);
116 }
117 OUTB(writearr[i], data->spibase + i);
118 msg_pspew(" data=0x%02x", writearr[i]);
119 mode = 0x50 | (writearr[1] & 0x0f);
120 } else if (8 == writecnt && 0 == readcnt) {
121 msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
122 for (i = 2; i < 4; i++) {
123 OUTB(writearr[i], data->spibase + i);
124 msg_pspew("%02x", writearr[i]);
125 }
126 msg_pspew(" data=0x");
127 for (; i < writecnt; i++) {
128 OUTB(writearr[i], data->spibase + i);
129 msg_pspew("%02x", writearr[i]);
130 }
131 mode = 0x60 | (writearr[1] & 0x0f);
132 } else if (5 == writecnt && 4 == readcnt) {
133 /* XXX: TODO not supported by flashrom infrastructure!
134 * This mode, 7, discards the fifth byte in writecnt,
135 * but since we can not express that in flashrom, fail
136 * the operation for now.
137 */
138 ;
139 } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) {
140 msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
141 for (i = 2; i < writecnt; i++) {
142 OUTB(writearr[i], data->spibase + i);
143 msg_pspew("%02x", writearr[i]);
144 }
145 mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f);
146 }
147 msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode);
148
149 if (!mode) {
150 msg_perr("%s: unsupported command type wr=%d rd=%d\n",
151 __func__, writecnt, readcnt);
152 /* Command type refers to the number of bytes read/written. */
153 return SPI_INVALID_LENGTH;
154 }
155
156 OUTB(writearr[0], data->spibase);
157 OUTB(mode, data->spibase + 1);
158 default_delay(10);
159
160 if (!readcnt)
161 return 0;
162
163 msg_pspew("%s: returning data =", __func__);
164 for (i = 0; i < readcnt; i++) {
165 readarr[i] = INB(data->spibase + 4 + i);
166 msg_pspew(" 0x%02x", readarr[i]);
167 }
168 msg_pspew("\n");
169 return 0;
170 }
171
wbsio_spi_read(struct flashctx * flash,uint8_t * buf,unsigned int start,unsigned int len)172 static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf,
173 unsigned int start, unsigned int len)
174 {
175 mmio_readn((void *)(flash->virtual_memory + start), buf, len);
176 return 0;
177 }
178
wbsio_spi_shutdown(void * data)179 static int wbsio_spi_shutdown(void *data)
180 {
181 free(data);
182 return 0;
183 }
184
185 static const struct spi_master spi_master_wbsio = {
186 .max_data_read = MAX_DATA_UNSPECIFIED,
187 .max_data_write = MAX_DATA_UNSPECIFIED,
188 .command = wbsio_spi_send_command,
189 .map_flash_region = physmap,
190 .unmap_flash_region = physunmap,
191 .read = wbsio_spi_read,
192 .write_256 = spi_chip_write_1,
193 .write_aai = spi_chip_write_1,
194 .shutdown = wbsio_spi_shutdown,
195 };
196
wbsio_check_for_spi(struct board_cfg * cfg)197 int wbsio_check_for_spi(struct board_cfg *cfg)
198 {
199 uint16_t wbsio_spibase = 0;
200
201 if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
202 if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2)))
203 return 1;
204
205 msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
206
207 msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
208 "1024 kB!\n", __func__);
209 max_rom_decode.spi = 1024 * 1024;
210
211 struct wbsio_spi_data *data = calloc(1, sizeof(*data));
212 if (!data) {
213 msg_perr("Unable to allocate space for extra SPI master data.\n");
214 return SPI_GENERIC_ERROR;
215 }
216 data->spibase = wbsio_spibase;
217
218 return register_spi_master(&spi_master_wbsio, data);
219 }
220