1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file cm_rt.h 24 //! \brief Contains all exposed APIs and Definitions for CM 25 //! 26 27 #ifndef __CM_RT_H__ 28 #define __CM_RT_H__ 29 30 //********************************************************************** 31 // Version 32 //********************************************************************** 33 #ifndef CM_1_0 34 #define CM_1_0 100 35 #endif 36 #ifndef CM_2_0 37 #define CM_2_0 200 38 #endif 39 #ifndef CM_2_1 40 #define CM_2_1 201 41 #endif 42 #ifndef CM_2_2 43 #define CM_2_2 202 44 #endif 45 #ifndef CM_2_3 46 #define CM_2_3 203 47 #endif 48 #ifndef CM_2_4 49 #define CM_2_4 204 50 #endif 51 #ifndef CM_3_0 52 #define CM_3_0 300 53 #endif 54 #ifndef CM_4_0 55 #define CM_4_0 400 56 #endif 57 #ifndef CM_5_0 58 #define CM_5_0 500 59 #endif 60 #ifndef CM_6_0 61 #define CM_6_0 600 62 #endif 63 #ifndef CM_7_0 64 #define CM_7_0 700 65 #endif 66 #ifndef CM_7_2 67 #define CM_7_2 702 //for MDFRT API refreshment. 68 #endif 69 70 //Legacy MACRO, will be removed later 71 #ifndef __INTEL_MDF 72 #define __INTEL_MDF (CM_7_2) 73 #endif 74 75 //New MACRO 76 #ifndef __INTEL_CM 77 #define __INTEL_CM (CM_7_2) 78 #endif 79 80 //********************************************************************** 81 // external headers 82 //********************************************************************** 83 #include <stdint.h> 84 85 //********************************************************************** 86 // Macros 87 //********************************************************************** 88 #ifdef __cplusplus 89 #define EXTERN_C extern "C" 90 #else 91 #define EXTERN_C 92 #endif 93 #define CM_RT_API 94 #define CM_KERNEL_FUNCTION(...) CM_KERNEL_FUNCTION2(__VA_ARGS__) 95 96 #define _NAME_MERGE_(x, y) x ## y 97 #define _NAME_LABEL_(name, id) _NAME_MERGE_(name, id) 98 #define __CODEGEN_UNIQUE(name) _NAME_LABEL_(name, __LINE__) 99 #define BITFIELD_RANGE( startbit, endbit ) ((endbit)-(startbit)+1) 100 #define BITFIELD_BIT(bit) 1 101 102 #define CM_MIN_SURF_WIDTH 1 103 #define CM_MIN_SURF_HEIGHT 1 104 #define CM_MIN_SURF_DEPTH 2 105 106 #define CM_MAX_1D_SURF_WIDTH 0x80000000 // 2^31 2 GB 107 108 #define CM_MAX_2D_SURF_WIDTH 16384 109 #define CM_MAX_2D_SURF_HEIGHT 16384 110 111 #define CM_MAX_3D_SURF_WIDTH 2048 112 #define CM_MAX_3D_SURF_HEIGHT 2048 113 #define CM_MAX_3D_SURF_DEPTH 2048 114 115 #define CM_MAX_OPTION_SIZE_IN_BYTE 512 116 #define CM_MAX_KERNEL_NAME_SIZE_IN_BYTE 256 117 #define CM_MAX_ISA_FILE_NAME_SIZE_IN_BYTE 256 118 119 #define CM_MAX_THREADSPACE_WIDTH_FOR_MW 511 120 #define CM_MAX_THREADSPACE_HEIGHT_FOR_MW 511 121 #define CM_MAX_THREADSPACE_WIDTH_FOR_MO 512 122 #define CM_MAX_THREADSPACE_HEIGHT_FOR_MO 512 123 #define CM_MAX_THREADSPACE_WIDTH_SKLUP_FOR_MW 2047 124 #define CM_MAX_THREADSPACE_HEIGHT_SKLUP_FOR_MW 2047 125 126 127 //Time in seconds before kernel should timeout 128 #define CM_MAX_TIMEOUT 2 129 //Time in milliseconds before kernel should timeout 130 #define CM_MAX_TIMEOUT_MS CM_MAX_TIMEOUT*1000 131 132 #define CM_NO_EVENT ((CmEvent *)(-1)) //NO Event 133 134 // Cm Device Create Option 135 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_DISABLE 1 136 #define CM_DEVICE_CREATE_OPTION_TDR_DISABLE 64 137 138 #define CM_DEVICE_CONFIG_DISABLE_TASKFLUSHEDSEMAPHORE_OFFSET 6 139 #define CM_DEVICE_CONFIG_DISABLE_TASKFLUSHEDSEMAPHORE_MASK (1<<CM_DEVICE_CONFIG_DISABLE_TASKFLUSHEDSEMAPHORE_OFFSET) 140 #define CM_DEVICE_CREATE_OPTION_TASKFLUSHEDSEMAPHORE_DISABLE 1 //to disable the semaphore for task flushed 141 #define CM_DEVICE_CONFIG_MIDTHREADPREEMPTION_OFFSET 22 142 #define CM_DEVICE_CONFIG_MIDTHREADPREEMPTION_DISENABLE (1 << CM_DEVICE_CONFIG_MIDTHREADPREEMPTION_OFFSET) 143 #define CM_DEVICE_CONFIG_KERNEL_DEBUG_OFFSET 23 144 #define CM_DEVICE_CONFIG_KERNEL_DEBUG_ENABLE (1 << CM_DEVICE_CONFIG_KERNEL_DEBUG_OFFSET) 145 #define CM_DEVICE_CONFIG_VEBOX_OFFSET 28 146 #define CM_DEVICE_CONFIG_VEBOX_DISABLE (1 << CM_DEVICE_CONFIG_VEBOX_OFFSET) 147 #define CM_DEVICE_CONFIG_GPUCOPY_OFFSET 29 148 #define CM_DEVICE_CONFIG_GPUCOPY_DISABLE (1 << CM_DEVICE_CONFIG_GPUCOPY_OFFSET) 149 #define CM_DEVICE_CONFIG_FAST_PATH_OFFSET 30 150 #define CM_DEVICE_CONFIG_FAST_PATH_ENABLE (1 << CM_DEVICE_CONFIG_FAST_PATH_OFFSET) 151 152 #define CM_DEVICE_CREATE_OPTION_DEFAULT CM_DEVICE_CONFIG_FAST_PATH_ENABLE 153 154 #define CM_MAX_DEPENDENCY_COUNT 8 155 #define CM_NUM_DWORD_FOR_MW_PARAM 16 156 157 #define CM_NUM_COEFF_ROWS 17 158 #define CM_NUM_COEFF_ROWS_SKL 32 159 160 #define CM_NUM_CONVOLVE_ROWS 16 161 #define CM_NUM_CONVOLVE_ROWS_SKL 32 162 163 #define CM_CHROMA_SITING_NONE 0, 164 #define CM_CHROMA_SITING_HORZ_LEFT 1 << 0 165 #define CM_CHROMA_SITING_HORZ_CENTER 1 << 1 166 #define CM_CHROMA_SITING_HORZ_RIGHT 1 << 2 167 #define CM_CHROMA_SITING_VERT_TOP 1 << 4 168 #define CM_CHROMA_SITING_VERT_CENTER 1 << 5 169 #define CM_CHROMA_SITING_VERT_BOTTOM 1 << 6 170 171 #define CM_NULL_SURFACE 0xFFFF 172 173 #define CM_FUSED_EU_DISABLE 0 174 #define CM_FUSED_EU_ENABLE 1 175 #define CM_FUSED_EU_DEFAULT CM_FUSED_EU_DISABLE 176 177 #define CM_TURBO_BOOST_DISABLE 0 178 #define CM_TURBO_BOOST_ENABLE 1 179 #define CM_TURBO_BOOST_DEFAULT CM_TURBO_BOOST_ENABLE 180 181 #define CM_CALLBACK __cdecl 182 183 // SVM buffer access flags definition 184 #define CM_SVM_ACCESS_FLAG_COARSE_GRAINED (0) //Coarse-grained SVM buffer, IA/GT cache coherency disabled 185 #define CM_SVM_ACCESS_FLAG_FINE_GRAINED (1 << 0) //Fine-grained SVM buffer, IA/GT cache coherency enabled 186 #define CM_SVM_ACCESS_FLAG_ATOMICS (1 << 1) //Crosse IA/GT atomics supported SVM buffer, need CM_SVM_ACCESS_FLAG_FINE_GRAINED flag is set as well 187 #define CM_SVM_ACCESS_FLAG_DEFAULT CM_SVM_ACCESS_FLAG_COARSE_GRAINED //default is coarse-grained SVM buffer 188 189 #define CM_BUFFER_STATELESS_CREATE_OPTION_GFX_MEM 0 190 #define CM_BUFFER_STATELESS_CREATE_OPTION_SYS_MEM 1 191 #define CM_BUFFER_STATELESS_CREATE_OPTION_DEGAULT CM_BUFFER_STATELESS_CREATE_OPTION_GFX_MEM 192 193 //********************************************************************** 194 // OS-specific includings and types 195 //********************************************************************** 196 #include "cm_rt_def_os.h" 197 198 //********************************************************************** 199 // Enumerations 200 //********************************************************************** 201 typedef enum _CM_RETURN_CODE 202 { 203 CM_SUCCESS = 0, 204 /* 205 * RANGE -1 ~ -9999 FOR EXTERNAL ERROR CODE 206 */ 207 CM_FAILURE = -1, 208 CM_NOT_IMPLEMENTED = -2, 209 CM_SURFACE_ALLOCATION_FAILURE = -3, 210 CM_OUT_OF_HOST_MEMORY = -4, 211 CM_SURFACE_FORMAT_NOT_SUPPORTED = -5, 212 CM_EXCEED_SURFACE_AMOUNT = -6, 213 CM_EXCEED_KERNEL_ARG_AMOUNT = -7, 214 CM_EXCEED_KERNEL_ARG_SIZE_IN_BYTE = -8, 215 CM_INVALID_ARG_INDEX = -9, 216 CM_INVALID_ARG_VALUE = -10, 217 CM_INVALID_ARG_SIZE = -11, 218 CM_INVALID_THREAD_INDEX = -12, 219 CM_INVALID_WIDTH = -13, 220 CM_INVALID_HEIGHT = -14, 221 CM_INVALID_DEPTH = -15, 222 CM_INVALID_COMMON_ISA = -16, 223 CM_OPEN_VIDEO_DEVICE_FAILURE = -17, 224 CM_VIDEO_DEVICE_LOCKED = -18, // Video device is already locked. 225 CM_LOCK_VIDEO_DEVICE_FAILURE = -19, // Video device is not locked but can't be locked. 226 CM_EXCEED_SAMPLER_AMOUNT = -20, 227 CM_EXCEED_MAX_KERNEL_PER_ENQUEUE = -21, 228 CM_EXCEED_MAX_KERNEL_SIZE_IN_BYTE = -22, 229 CM_EXCEED_MAX_THREAD_AMOUNT_PER_ENQUEUE = -23, 230 CM_EXCEED_VME_STATE_G6_AMOUNT = -24, 231 CM_INVALID_THREAD_SPACE = -25, 232 CM_EXCEED_MAX_TIMEOUT = -26, 233 CM_JITDLL_LOAD_FAILURE = -27, 234 CM_JIT_COMPILE_FAILURE = -28, 235 CM_JIT_COMPILESIM_FAILURE = -29, 236 CM_INVALID_THREAD_GROUP_SPACE = -30, 237 CM_THREAD_ARG_NOT_ALLOWED = -31, 238 CM_INVALID_GLOBAL_BUFFER_INDEX = -32, 239 CM_INVALID_BUFFER_HANDLER = -33, 240 CM_EXCEED_MAX_SLM_SIZE = -34, 241 CM_JITDLL_OLDER_THAN_ISA = -35, 242 CM_INVALID_HARDWARE_THREAD_NUMBER = -36, 243 CM_GTPIN_INVOKE_FAILURE = -37, 244 CM_INVALIDE_L3_CONFIGURATION = -38, 245 CM_INVALID_TEXTURE2D_USAGE = -39, 246 CM_INTEL_GFX_NOTFOUND = -40, 247 CM_GPUCOPY_INVALID_SYSMEM = -41, 248 CM_GPUCOPY_INVALID_WIDTH = -42, 249 CM_GPUCOPY_INVALID_STRIDE = -43, 250 CM_EVENT_DRIVEN_FAILURE = -44, 251 CM_LOCK_SURFACE_FAIL = -45, // Lock surface failed 252 CM_INVALID_GENX_BINARY = -46, 253 CM_FEATURE_NOT_SUPPORTED_IN_DRIVER = -47, // driver out-of-sync 254 CM_QUERY_DLL_VERSION_FAILURE = -48, //Fail in getting DLL file version 255 CM_KERNELPAYLOAD_PERTHREADARG_MUTEX_FAIL = -49, 256 CM_KERNELPAYLOAD_PERKERNELARG_MUTEX_FAIL = -50, 257 CM_KERNELPAYLOAD_SETTING_FAILURE = -51, 258 CM_KERNELPAYLOAD_SURFACE_INVALID_BTINDEX = -52, 259 CM_NOT_SET_KERNEL_ARGUMENT = -53, 260 CM_GPUCOPY_INVALID_SURFACES = -54, 261 CM_GPUCOPY_INVALID_SIZE = -55, 262 CM_GPUCOPY_OUT_OF_RESOURCE = -56, 263 CM_INVALID_VIDEO_DEVICE = -57, 264 CM_SURFACE_DELAY_DESTROY = -58, 265 CM_INVALID_VEBOX_STATE = -59, 266 CM_INVALID_VEBOX_SURFACE = -60, 267 CM_FEATURE_NOT_SUPPORTED_BY_HARDWARE = -61, 268 CM_RESOURCE_USAGE_NOT_SUPPORT_READWRITE = -62, 269 CM_MULTIPLE_MIPLEVELS_NOT_SUPPORTED = -63, 270 CM_INVALID_UMD_CONTEXT = -64, 271 CM_INVALID_LIBVA_SURFACE = -65, 272 CM_INVALID_LIBVA_INITIALIZE = -66, 273 CM_KERNEL_THREADSPACE_NOT_SET = -67, 274 CM_INVALID_KERNEL_THREADSPACE = -68, 275 CM_KERNEL_THREADSPACE_THREADS_NOT_ASSOCIATED= -69, 276 CM_KERNEL_THREADSPACE_INTEGRITY_FAILED = -70, 277 CM_INVALID_USERPROVIDED_GENBINARY = -71, 278 CM_INVALID_PRIVATE_DATA = -72, 279 CM_INVALID_MOS_RESOURCE_HANDLE = -73, 280 CM_SURFACE_CACHED = -74, 281 CM_SURFACE_IN_USE = -75, 282 CM_INVALID_GPUCOPY_KERNEL = -76, 283 CM_INVALID_DEPENDENCY_WITH_WALKING_PATTERN = -77, 284 CM_INVALID_MEDIA_WALKING_PATTERN = -78, 285 CM_FAILED_TO_ALLOCATE_SVM_BUFFER = -79, 286 CM_EXCEED_MAX_POWER_OPTION_FOR_PLATFORM = -80, 287 CM_INVALID_KERNEL_THREADGROUPSPACE = -81, 288 CM_INVALID_KERNEL_SPILL_CODE = -82, 289 CM_UMD_DRIVER_NOT_SUPPORTED = -83, 290 CM_INVALID_GPU_FREQUENCY_VALUE = -84, 291 CM_SYSTEM_MEMORY_NOT_4KPAGE_ALIGNED = -85, 292 CM_KERNEL_ARG_SETTING_FAILED = -86, 293 CM_NO_AVAILABLE_SURFACE = -87, 294 CM_VA_SURFACE_NOT_SUPPORTED = -88, 295 CM_TOO_MUCH_THREADS = -89, 296 CM_NULL_POINTER = -90, 297 CM_EXCEED_MAX_NUM_2D_ALIASES = -91, 298 CM_INVALID_PARAM_SIZE = -92, 299 CM_GT_UNSUPPORTED = -93, 300 CM_GTPIN_FLAG_NO_LONGER_SUPPORTED = -94, 301 CM_PLATFORM_UNSUPPORTED_FOR_API = -95, 302 CM_TASK_MEDIA_RESET = -96, 303 CM_KERNELPAYLOAD_SAMPLER_INVALID_BTINDEX = -97, 304 CM_EXCEED_MAX_NUM_BUFFER_ALIASES = -98, 305 CM_SYSTEM_MEMORY_NOT_4PIXELS_ALIGNED = -99, 306 CM_FAILED_TO_CREATE_CURBE_SURFACE = -100, 307 CM_INVALID_CAP_NAME = -101, 308 CM_INVALID_PARAM_FOR_CREATE_QUEUE_EX = -102, 309 CM_INVALID_CREATE_OPTION_FOR_BUFFER_STATELESS = -103, 310 CM_INVALID_KERNEL_ARG_POINTER = -104, 311 CM_LOAD_LIBRARY_FAILED = -105, 312 CM_NO_SUPPORTED_ADAPTER = -106, 313 314 /* 315 * RANGE <=-10000 FOR INTERNAL ERROR CODE 316 */ 317 CM_INTERNAL_ERROR_CODE_OFFSET = -10000, 318 } CM_RETURN_CODE; 319 320 typedef enum _CM_STATUS 321 { 322 CM_STATUS_QUEUED = 0, 323 CM_STATUS_FLUSHED = 1, 324 CM_STATUS_FINISHED = 2, 325 CM_STATUS_STARTED = 3, 326 CM_STATUS_RESET = 4 327 328 } CM_STATUS; 329 330 typedef enum _CM_PIXEL_TYPE 331 { 332 CM_PIXEL_UINT, 333 CM_PIXEL_SINT, 334 CM_PIXEL_OTHER 335 } CM_PIXEL_TYPE; 336 337 enum GPU_PLATFORM{ 338 PLATFORM_INTEL_UNKNOWN = 0, 339 PLATFORM_INTEL_BDW = 4, 340 PLATFORM_INTEL_SKL = 7, 341 PLATFORM_INTEL_BXT = 8, 342 PLATFORM_INTEL_KBL = 11, 343 PLATFORM_INTEL_ICLLP = 13, 344 PLATFORM_INTEL_TGLLP = 15, 345 PLATFORM_INTEL_GLK = 16, 346 PLATFORM_INTEL_CFL = 17, 347 }; 348 349 enum GPU_GT_PLATFORM{ 350 PLATFORM_INTEL_GT_UNKNOWN = 0, 351 PLATFORM_INTEL_GT1 = 1, 352 PLATFORM_INTEL_GT2 = 2, 353 PLATFORM_INTEL_GT3 = 3, 354 PLATFORM_INTEL_GT4 = 4, 355 PLATFORM_INTEL_GT1_5 = 10 356 }; 357 358 typedef enum _CM_DEVICE_CAP_NAME 359 { 360 CAP_KERNEL_COUNT_PER_TASK, 361 CAP_KERNEL_BINARY_SIZE, 362 CAP_SAMPLER_COUNT , 363 CAP_SAMPLER_COUNT_PER_KERNEL, 364 CAP_BUFFER_COUNT , 365 CAP_SURFACE2D_COUNT, 366 CAP_SURFACE3D_COUNT, 367 CAP_SURFACE_COUNT_PER_KERNEL, 368 CAP_ARG_COUNT_PER_KERNEL, 369 CAP_ARG_SIZE_PER_KERNEL , 370 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK, 371 CAP_HW_THREAD_COUNT, 372 CAP_SURFACE2D_FORMAT_COUNT, 373 CAP_SURFACE2D_FORMATS, 374 CAP_SURFACE3D_FORMAT_COUNT, 375 CAP_SURFACE3D_FORMATS, 376 CAP_VME_STATE_COUNT, 377 CAP_GPU_PLATFORM, 378 CAP_GT_PLATFORM, 379 CAP_MIN_FREQUENCY, 380 CAP_MAX_FREQUENCY, 381 CAP_L3_CONFIG, 382 CAP_GPU_CURRENT_FREQUENCY, 383 CAP_USER_DEFINED_THREAD_COUNT_PER_TASK_NO_THREAD_ARG, 384 CAP_USER_DEFINED_THREAD_COUNT_PER_MEDIA_WALKER, 385 CAP_USER_DEFINED_THREAD_COUNT_PER_THREAD_GROUP, 386 CAP_SURFACE2DUP_COUNT, 387 CAP_PLATFORM_INFO, 388 CAP_MAX_BUFFER_SIZE, 389 CAP_MAX_SUBDEV_COUNT //for app to retrieve the total count of sub devices 390 } CM_DEVICE_CAP_NAME; 391 392 typedef enum _CM_FASTCOPY_OPTION 393 { 394 CM_FASTCOPY_OPTION_NONBLOCKING = 0x00, 395 CM_FASTCOPY_OPTION_BLOCKING = 0x01 396 } CM_FASTCOPY_OPTION; 397 398 typedef enum _CM_DEPENDENCY_PATTERN 399 { 400 CM_NONE_DEPENDENCY = 0, //All threads run parallel, scanline dispatch 401 CM_WAVEFRONT = 1, 402 CM_WAVEFRONT26 = 2, 403 CM_VERTICAL_WAVE = 3, 404 CM_HORIZONTAL_WAVE = 4, 405 CM_WAVEFRONT26Z = 5, 406 CM_WAVEFRONT26X = 6, 407 CM_WAVEFRONT26ZIG = 7, 408 CM_WAVEFRONT26ZI = 8 409 } CM_DEPENDENCY_PATTERN; 410 411 typedef enum _CM_WALKING_PATTERN 412 { 413 CM_WALK_DEFAULT = 0, 414 CM_WALK_WAVEFRONT = 1, 415 CM_WALK_WAVEFRONT26 = 2, 416 CM_WALK_VERTICAL = 3, 417 CM_WALK_HORIZONTAL = 4, 418 CM_WALK_WAVEFRONT26X = 5, 419 CM_WALK_WAVEFRONT26ZIG = 6, 420 CM_WALK_WAVEFRONT45D = 7, 421 CM_WALK_WAVEFRONT45XD_2 = 8 422 } CM_WALKING_PATTERN; 423 424 typedef enum _CM_26ZI_DISPATCH_PATTERN 425 { 426 VVERTICAL_HVERTICAL_26 = 0, 427 VVERTICAL_HHORIZONTAL_26 = 1, 428 VVERTICAL26_HHORIZONTAL26 = 2, 429 VVERTICAL1X26_HHORIZONTAL1X26 = 3 430 } CM_26ZI_DISPATCH_PATTERN; 431 432 typedef enum _CM_MW_GROUP_SELECT 433 { 434 CM_MW_GROUP_NONE = 0, 435 CM_MW_GROUP_COLORLOOP = 1, 436 CM_MW_GROUP_INNERLOCAL = 2, 437 CM_MW_GROUP_MIDLOCAL = 3, 438 CM_MW_GROUP_OUTERLOCAL = 4, 439 CM_MW_GROUP_INNERGLOBAL = 5, 440 } CM_MW_GROUP_SELECT; 441 442 /**************** L3/Cache ***************/ 443 enum MEMORY_OBJECT_CONTROL 444 { 445 MEMORY_OBJECT_CONTROL_SKL_DEFAULT = 0, 446 MEMORY_OBJECT_CONTROL_SKL_NO_L3, 447 MEMORY_OBJECT_CONTROL_SKL_NO_LLC_ELLC, 448 MEMORY_OBJECT_CONTROL_SKL_NO_LLC, 449 MEMORY_OBJECT_CONTROL_SKL_NO_ELLC, 450 MEMORY_OBJECT_CONTROL_SKL_NO_LLC_L3, 451 MEMORY_OBJECT_CONTROL_SKL_NO_ELLC_L3, 452 MEMORY_OBJECT_CONTROL_SKL_NO_CACHE, 453 MEMORY_OBJECT_CONTROL_SKL_COUNT, 454 455 MEMORY_OBJECT_CONTROL_CNL_DEFAULT = 0, 456 MEMORY_OBJECT_CONTROL_CNL_NO_L3, 457 MEMORY_OBJECT_CONTROL_CNL_NO_LLC_ELLC, 458 MEMORY_OBJECT_CONTROL_CNL_NO_LLC, 459 MEMORY_OBJECT_CONTROL_CNL_NO_ELLC, 460 MEMORY_OBJECT_CONTROL_CNL_NO_LLC_L3, 461 MEMORY_OBJECT_CONTROL_CNL_NO_ELLC_L3, 462 MEMORY_OBJECT_CONTROL_CNL_NO_CACHE, 463 MEMORY_OBJECT_CONTROL_CNL_COUNT, 464 465 // Unified memory object control type for SKL+ 466 MEMORY_OBJECT_CONTROL_DEFAULT = 0x0, 467 MEMORY_OBJECT_CONTROL_NO_L3, 468 MEMORY_OBJECT_CONTROL_NO_LLC_ELLC, 469 MEMORY_OBJECT_CONTROL_NO_LLC, 470 MEMORY_OBJECT_CONTROL_NO_ELLC, 471 MEMORY_OBJECT_CONTROL_NO_LLC_L3, 472 MEMORY_OBJECT_CONTROL_NO_ELLC_L3, 473 MEMORY_OBJECT_CONTROL_NO_CACHE, 474 MEMORY_OBJECT_CONTROL_L1_ENABLED, 475 476 MEMORY_OBJECT_CONTROL_UNKNOWN = 0xff 477 }; 478 479 typedef enum _MEMORY_TYPE { 480 CM_USE_PTE, 481 CM_UN_CACHEABLE, 482 CM_WRITE_THROUGH, 483 CM_WRITE_BACK, 484 485 // BDW 486 MEMORY_TYPE_BDW_UC_WITH_FENCE = 0, 487 MEMORY_TYPE_BDW_UC, 488 MEMORY_TYPE_BDW_WT, 489 MEMORY_TYPE_BDW_WB 490 491 } MEMORY_TYPE; 492 493 typedef enum _L3_SUGGEST_CONFIG 494 { 495 CM_L3_PLANE_DEFAULT = 0, 496 CM_L3_PLANE_1, 497 CM_L3_PLANE_2, 498 CM_L3_PLANE_3, 499 CM_L3_PLANE_4, 500 CM_L3_PLANE_5, 501 CM_L3_PLANE_6, 502 CM_L3_PLANE_7, 503 CM_L3_PLANE_8, 504 } L3_SUGGEST_CONFIG; 505 506 typedef enum _CM_SAMPLER8x8_SURFACE_ 507 { 508 CM_AVS_SURFACE = 0, 509 CM_VA_SURFACE = 1 510 }CM_SAMPLER8x8_SURFACE; 511 512 typedef enum _CM_SURFACE_ADDRESS_CONTROL_MODE_ 513 { 514 CM_SURFACE_CLAMP = 0, 515 CM_SURFACE_MIRROR = 1 516 }CM_SURFACE_ADDRESS_CONTROL_MODE; 517 518 typedef enum _CM_MESSAGE_SEQUENCE_ 519 { 520 CM_MS_1x1 = 0, 521 CM_MS_16x1 = 1, 522 CM_MS_16x4 = 2, 523 CM_MS_32x1 = 3, 524 CM_MS_32x4 = 4, 525 CM_MS_64x1 = 5, 526 CM_MS_64x4 = 6 527 }CM_MESSAGE_SEQUENCE; 528 529 typedef enum _CM_MIN_MAX_FILTER_CONTROL_ 530 { 531 CM_MIN_FILTER = 0, 532 CM_MAX_FILTER = 1, 533 CM_BOTH_FILTER = 3 534 }CM_MIN_MAX_FILTER_CONTROL; 535 536 typedef enum _CM_VA_FUNCTION_ 537 { 538 CM_VA_MINMAXFILTER = 0, 539 CM_VA_DILATE = 1, 540 CM_VA_ERODE = 2 541 } CM_VA_FUNCTION; 542 543 typedef enum _CM_EVENT_PROFILING_INFO 544 { 545 CM_EVENT_PROFILING_HWSTART, 546 CM_EVENT_PROFILING_HWEND, 547 CM_EVENT_PROFILING_SUBMIT, 548 CM_EVENT_PROFILING_COMPLETE, 549 CM_EVENT_PROFILING_KERNELCOUNT, 550 CM_EVENT_PROFILING_KERNELNAMES, 551 CM_EVENT_PROFILING_THREADSPACE 552 }CM_EVENT_PROFILING_INFO; 553 554 // CM Convolve type for SKL+ 555 typedef enum _CM_CONVOLVE_SKL_TYPE 556 { 557 CM_CONVOLVE_SKL_TYPE_2D = 0, 558 CM_CONVOLVE_SKL_TYPE_1D = 1, 559 CM_CONVOLVE_SKL_TYPE_1P = 2 560 } CM_CONVOLVE_SKL_TYPE; 561 562 typedef enum _CM_ROTATION 563 { 564 CM_ROTATION_IDENTITY = 0, //!< Rotation 0 degrees 565 CM_ROTATION_90, //!< Rotation 90 degrees 566 CM_ROTATION_180, //!< Rotation 180 degrees 567 CM_ROTATION_270, //!< Rotation 270 degrees 568 } CM_ROTATION; 569 570 // to define frame type for interlace frame support 571 typedef enum _CM_FRAME_TYPE 572 { 573 CM_FRAME, // singe frame, not interlaced 574 CM_TOP_FIELD, 575 CM_BOTTOM_FIELD, 576 MAX_FRAME_TYPE 577 } CM_FRAME_TYPE; 578 579 enum CM_QUEUE_TYPE 580 { 581 CM_QUEUE_TYPE_NONE = 0, 582 CM_QUEUE_TYPE_RENDER = 1, 583 CM_QUEUE_TYPE_COMPUTE = 2 584 }; 585 586 enum CM_QUEUE_SSEU_USAGE_HINT_TYPE 587 { 588 CM_QUEUE_SSEU_USAGE_HINT_DEFAULT = 0, 589 CM_QUEUE_SSEU_USAGE_HINT_VME = 1 590 }; 591 592 //********************************************************************** 593 // Structures 594 //********************************************************************** 595 typedef struct _CM_SAMPLER_STATE 596 { 597 CM_TEXTURE_FILTER_TYPE minFilterType; 598 CM_TEXTURE_FILTER_TYPE magFilterType; 599 CM_TEXTURE_ADDRESS_TYPE addressU; 600 CM_TEXTURE_ADDRESS_TYPE addressV; 601 CM_TEXTURE_ADDRESS_TYPE addressW; 602 } CM_SAMPLER_STATE; 603 604 typedef struct _CM_SAMPLER_STATE_EX 605 { 606 CM_TEXTURE_FILTER_TYPE minFilterType; 607 CM_TEXTURE_FILTER_TYPE magFilterType; 608 CM_TEXTURE_ADDRESS_TYPE addressU; 609 CM_TEXTURE_ADDRESS_TYPE addressV; 610 CM_TEXTURE_ADDRESS_TYPE addressW; 611 612 CM_PIXEL_TYPE SurfaceFormat; 613 union { 614 DWORD BorderColorRedU; 615 INT BorderColorRedS; 616 FLOAT BorderColorRedF; 617 }; 618 619 union { 620 DWORD BorderColorGreenU; 621 INT BorderColorGreenS; 622 FLOAT BorderColorGreenF; 623 }; 624 625 union { 626 DWORD BorderColorBlueU; 627 INT BorderColorBlueS; 628 FLOAT BorderColorBlueF; 629 }; 630 631 union { 632 DWORD BorderColorAlphaU; 633 INT BorderColorAlphaS; 634 FLOAT BorderColorAlphaF; 635 }; 636 } CM_SAMPLER_STATE_EX; 637 638 typedef struct _CM_PLATFORM_INFO 639 { 640 UINT numSlices; 641 UINT numSubSlices; 642 UINT numEUsPerSubSlice; 643 UINT numHWThreadsPerEU; 644 UINT numMaxEUsPerPool; 645 }CM_PLATFORM_INFO, *PCM_PLATFORM_INFO; 646 647 // CM RT DLL File Version 648 typedef struct _CM_DLL_FILE_VERSION 649 { 650 WORD wMANVERSION; 651 WORD wMANREVISION; 652 WORD wSUBREVISION; 653 WORD wBUILD_NUMBER; 654 //Version constructed as : "wMANVERSION.wMANREVISION.wSUBREVISION.wBUILD_NUMBER" 655 } CM_DLL_FILE_VERSION, *PCM_DLL_FILE_VERSION; 656 657 // parameters used to set the surface state of the CmSurface 658 struct CM_VME_SURFACE_STATE_PARAM 659 { 660 UINT width; 661 UINT height; 662 }; 663 664 typedef struct _CM_WALKING_PARAMETERS 665 { 666 DWORD Value[CM_NUM_DWORD_FOR_MW_PARAM]; 667 } CM_WALKING_PARAMETERS, *PCM_WALKING_PARAMETERS; 668 669 typedef struct _CM_DEPENDENCY 670 { 671 UINT count; 672 INT deltaX[CM_MAX_DEPENDENCY_COUNT]; 673 INT deltaY[CM_MAX_DEPENDENCY_COUNT]; 674 }CM_DEPENDENCY; 675 676 typedef struct _CM_COORDINATE 677 { 678 INT x; 679 INT y; 680 } CM_COORDINATE, *PCM_COORDINATE; 681 682 typedef struct _CM_THREAD_PARAM 683 { 684 CM_COORDINATE scoreboardCoordinates; 685 BYTE scoreboardColor; 686 BYTE sliceDestinationSelect; 687 BYTE subSliceDestinationSelect; 688 } CM_THREAD_PARAM, *PCM_THREAD_PARAM; 689 690 struct L3ConfigRegisterValues 691 { 692 unsigned int config_register0; 693 unsigned int config_register1; 694 unsigned int config_register2; 695 unsigned int config_register3; 696 }; 697 698 //GT-PIN 699 typedef struct _CM_SURFACE_DETAILS{ 700 UINT width; 701 UINT height; 702 UINT depth; 703 CM_SURFACE_FORMAT format; 704 UINT planeIndex; 705 UINT pitch; 706 UINT slicePitch; 707 UINT SurfaceBaseAddress; 708 UINT8 TiledSurface; 709 UINT8 TileWalk; 710 UINT XOffset; 711 UINT YOffset; 712 713 }CM_SURFACE_DETAILS; 714 715 /* 716 * AVS SAMPLER8x8 STATE 717 */ 718 typedef struct _CM_AVS_COEFF_TABLE{ 719 float FilterCoeff_0_0; 720 float FilterCoeff_0_1; 721 float FilterCoeff_0_2; 722 float FilterCoeff_0_3; 723 float FilterCoeff_0_4; 724 float FilterCoeff_0_5; 725 float FilterCoeff_0_6; 726 float FilterCoeff_0_7; 727 }CM_AVS_COEFF_TABLE; 728 729 typedef struct _CM_AVS_INTERNEL_COEFF_TABLE{ 730 BYTE FilterCoeff_0_0; 731 BYTE FilterCoeff_0_1; 732 BYTE FilterCoeff_0_2; 733 BYTE FilterCoeff_0_3; 734 BYTE FilterCoeff_0_4; 735 BYTE FilterCoeff_0_5; 736 BYTE FilterCoeff_0_6; 737 BYTE FilterCoeff_0_7; 738 }CM_AVS_INTERNEL_COEFF_TABLE; 739 740 typedef struct _CM_AVS_NONPIPLINED_STATE{ 741 bool BypassXAF; 742 bool BypassYAF; 743 BYTE DefaultSharpLvl; 744 BYTE maxDerivative4Pixels; 745 BYTE maxDerivative8Pixels; 746 BYTE transitionArea4Pixels; 747 BYTE transitionArea8Pixels; 748 CM_AVS_COEFF_TABLE Tbl0X[ CM_NUM_COEFF_ROWS_SKL ]; 749 CM_AVS_COEFF_TABLE Tbl0Y[ CM_NUM_COEFF_ROWS_SKL ]; 750 CM_AVS_COEFF_TABLE Tbl1X[ CM_NUM_COEFF_ROWS_SKL ]; 751 CM_AVS_COEFF_TABLE Tbl1Y[ CM_NUM_COEFF_ROWS_SKL ]; 752 bool bEnableRGBAdaptive; 753 bool bAdaptiveFilterAllChannels; 754 }CM_AVS_NONPIPLINED_STATE; 755 756 typedef struct _CM_AVS_INTERNEL_NONPIPLINED_STATE{ 757 bool BypassXAF; 758 bool BypassYAF; 759 BYTE DefaultSharpLvl; 760 BYTE maxDerivative4Pixels; 761 BYTE maxDerivative8Pixels; 762 BYTE transitionArea4Pixels; 763 BYTE transitionArea8Pixels; 764 CM_AVS_INTERNEL_COEFF_TABLE Tbl0X[ CM_NUM_COEFF_ROWS_SKL ]; 765 CM_AVS_INTERNEL_COEFF_TABLE Tbl0Y[ CM_NUM_COEFF_ROWS_SKL ]; 766 CM_AVS_INTERNEL_COEFF_TABLE Tbl1X[ CM_NUM_COEFF_ROWS_SKL ]; 767 CM_AVS_INTERNEL_COEFF_TABLE Tbl1Y[ CM_NUM_COEFF_ROWS_SKL ]; 768 bool bEnableRGBAdaptive; 769 bool bAdaptiveFilterAllChannels; 770 }CM_AVS_INTERNEL_NONPIPLINED_STATE; 771 772 typedef struct _CM_AVS_STATE_MSG{ 773 bool AVSTYPE; //true nearest, false adaptive 774 bool EightTapAFEnable; //HSW+ 775 bool BypassIEF; //ignored for BWL, moved to sampler8x8 payload. 776 bool ShuffleOutputWriteback; //SKL mode only to be set when AVS msg sequence is 4x4 or 8x4 777 bool HDCDirectWriteEnable; 778 unsigned short GainFactor; 779 unsigned char GlobalNoiseEstm; 780 unsigned char StrongEdgeThr; 781 unsigned char WeakEdgeThr; 782 unsigned char StrongEdgeWght; 783 unsigned char RegularWght; 784 unsigned char NonEdgeWght; 785 unsigned short wR3xCoefficient; 786 unsigned short wR3cCoefficient; 787 unsigned short wR5xCoefficient; 788 unsigned short wR5cxCoefficient; 789 unsigned short wR5cCoefficient; 790 //For Non-piplined states 791 unsigned short stateID; 792 CM_AVS_NONPIPLINED_STATE * AvsState; 793 } CM_AVS_STATE_MSG; 794 795 struct CM_AVS_STATE_MSG_EX { 796 CM_AVS_STATE_MSG_EX(); 797 798 bool enable_all_channel_adaptive_filter; // adaptive filter for all channels. validValues => [true..false] 799 bool enable_rgb_adaptive_filter; // adaptive filter for all channels. validValues => [true..false] 800 bool enable_8_tap_adaptive_filter; // enable 8-tap filter. validValues => [true..false] 801 bool enable_uv_8_tap_filter; // enable 8-tap filter on UV/RB channels. validValues => [true..false] 802 bool writeback_format; // true sampleunorm, false standard. validValues => [true..false] 803 bool writeback_mode; // true vsa, false ief. validValues => [true..false] 804 BYTE state_selection; // 0=>first,1=>second scaler8x8 state. validValues => [0..1] 805 806 // Image enhancement filter settings. 807 bool enable_ief; // image enhancement filter enable. validValues => [true..false] 808 bool ief_type; // true "basic" or false "advanced". validValues => [true..false] 809 bool enable_ief_smooth; // true based on 3x3, false based on 5x5 validValues => [true..false] 810 float r3c_coefficient; // smoothing coeffient. Valid values => [0.0..0.96875] 811 float r3x_coefficient; // smoothing coeffient. Valid values => [0.0..0.96875] 812 float r5c_coefficient; // smoothing coeffient. validValues => [0.0..0.96875] 813 float r5cx_coefficient; // smoothing coeffient. validValues => [0.0..0.96875] 814 float r5x_coefficient; // smoothing coeffient. validValues => [0.0..0.96875] 815 816 // Edge processing settings. 817 BYTE strong_edge_threshold; // validValues => [0..64] 818 BYTE strong_edge_weight; // Sharpening strength when a strong edge. validValues => [0..7] 819 BYTE weak_edge_threshold; // validValues => [0..64] 820 BYTE regular_edge_weight; // Sharpening strength when a weak edge. validValues => [0..7] 821 BYTE non_edge_weight; // Sharpening strength when no edge. validValues => [0..7] 822 823 // Chroma key. 824 bool enable_chroma_key; // Chroma keying be performed. validValues => [true..false] 825 BYTE chroma_key_index; // ChromaKey Table entry. validValues => [0..3] 826 827 // Skin tone settings. 828 bool enable_skin_tone; // SkinToneTunedIEF_Enable. validValues => [true..false] 829 bool enable_vy_skin_tone_detection; // Enables STD in the VY subspace. validValues => [true..false] 830 bool skin_detail_factor; // validValues => [true..false] 831 BYTE skin_types_margin; // validValues => [0..255] 832 BYTE skin_types_threshold; // validValues => [0..255] 833 834 // Miscellaneous settings. 835 BYTE gain_factor; // validValues => [0..63] 836 BYTE global_noise_estimation; // validValues => [0..255] 837 bool mr_boost; // validValues => [true..false] 838 BYTE mr_smooth_threshold; // validValues => [0..3] 839 BYTE mr_threshold; 840 bool steepness_boost; // validValues => [true..false] 841 BYTE steepness_threshold; // validValues => [0..15] 842 bool texture_coordinate_mode; // true: clamp, false: mirror. validValues => [true..false] 843 BYTE max_hue; // Rectangle half width. validValued => [0..63] 844 BYTE max_saturation; // Rectangle half length. validValued => [0..63] 845 int angles; // validValued => [0..360] 846 BYTE diamond_margin ; // validValues => [0..7] 847 char diamond_du; // Rhombus center shift in the sat-direction. validValues => [-64..63] 848 char diamond_dv; // Rhombus center shift in the hue-direction. validValues => [-64..63] 849 float diamond_alpha; // validValues => [0.0..4.0] 850 BYTE diamond_threshold; // validValues => [0..63] 851 BYTE rectangle_margin; // validValues => [0..7] 852 BYTE rectangle_midpoint[2]; // validValues => [[0..255, 0..255]] 853 float vy_inverse_margin[2]; // validValues => [[0.0..1.0, 0.0..1.0]] 854 855 // Piecewise linear function settings. 856 BYTE piecewise_linear_y_points[4]; // validValues => [[0..255, 0..255, 0..255, 0..255]] 857 float piecewise_linear_y_slopes[2]; // validValues => [[-4.0...4.0, -4.0...4.0]] 858 BYTE piecewise_linear_points_lower[4]; // validValues => [[0..255, 0..255, 0..255, 0..255]] 859 BYTE piecewise_linear_points_upper[4]; // validValues => [[0..255, 0..255, 0..255, 0..255]] 860 float piecewise_linear_slopes_lower[4]; // validValues => [[-4.0...4.0, -4.0...4.0, -4.0...4.0, -4.0...4.0]] 861 float piecewise_linear_slopes_upper[4]; // validValues => [[-4.0...4.0, -4.0...4.0, -4.0...4.0, -4.0...4.0]] 862 BYTE piecewise_linear_biases_lower[4]; // validValues => [[0..255, 0..255, 0..255, 0..255]] 863 BYTE piecewise_linear_biases_upper[4]; // validValues => [[0..255, 0..255, 0..255, 0..255]] 864 865 // AVS non-pipelined states. 866 BYTE default_sharpness_level; // default coefficient between smooth and sharp filtering. validValues => [0..255] 867 bool enable_x_adaptive_filter; // validValues => [true, false] 868 bool enable_y_adaptive_filter; // validValues => [true, false] 869 BYTE max_derivative_4_pixels; // lower boundary of the smooth 4 pixel area. validValues => [0..255] 870 BYTE max_derivative_8_pixels; // lower boundary of the smooth 8 pixel area. validValues => [0..255] 871 BYTE transition_area_4_pixels; // used in adaptive filtering to specify the width of the transition area for the 4 pixel calculation. validValues => [0..8] 872 BYTE transition_area_8_pixels; // Used in adaptive filtering to specify the width of the transition area for the 8 pixel calculation. validValues => [0..8] 873 CM_AVS_COEFF_TABLE table0_x[CM_NUM_COEFF_ROWS_SKL]; 874 CM_AVS_COEFF_TABLE table0_y[CM_NUM_COEFF_ROWS_SKL]; 875 CM_AVS_COEFF_TABLE table1_x[CM_NUM_COEFF_ROWS_SKL]; 876 CM_AVS_COEFF_TABLE table1_y[CM_NUM_COEFF_ROWS_SKL]; 877 }; 878 879 /* 880 * CONVOLVE STATE DATA STRUCTURES 881 */ 882 883 typedef struct _CM_CONVOLVE_COEFF_TABLE{ 884 float FilterCoeff_0_0; 885 float FilterCoeff_0_1; 886 float FilterCoeff_0_2; 887 float FilterCoeff_0_3; 888 float FilterCoeff_0_4; 889 float FilterCoeff_0_5; 890 float FilterCoeff_0_6; 891 float FilterCoeff_0_7; 892 float FilterCoeff_0_8; 893 float FilterCoeff_0_9; 894 float FilterCoeff_0_10; 895 float FilterCoeff_0_11; 896 float FilterCoeff_0_12; 897 float FilterCoeff_0_13; 898 float FilterCoeff_0_14; 899 float FilterCoeff_0_15; 900 float FilterCoeff_0_16; 901 float FilterCoeff_0_17; 902 float FilterCoeff_0_18; 903 float FilterCoeff_0_19; 904 float FilterCoeff_0_20; 905 float FilterCoeff_0_21; 906 float FilterCoeff_0_22; 907 float FilterCoeff_0_23; 908 float FilterCoeff_0_24; 909 float FilterCoeff_0_25; 910 float FilterCoeff_0_26; 911 float FilterCoeff_0_27; 912 float FilterCoeff_0_28; 913 float FilterCoeff_0_29; 914 float FilterCoeff_0_30; 915 float FilterCoeff_0_31; 916 }CM_CONVOLVE_COEFF_TABLE; 917 918 typedef struct _CM_CONVOLVE_STATE_MSG{ 919 bool CoeffSize; //true 16-bit, false 8-bit 920 byte SclDwnValue; //Scale down value 921 byte Width; //Kernel Width 922 byte Height; //Kernel Height 923 //SKL mode 924 bool isVertical32Mode; 925 bool isHorizontal32Mode; 926 CM_CONVOLVE_SKL_TYPE nConvolveType; 927 CM_CONVOLVE_COEFF_TABLE Table[CM_NUM_CONVOLVE_ROWS_SKL]; 928 } CM_CONVOLVE_STATE_MSG; 929 930 /* 931 * MISC SAMPLER8x8 State 932 */ 933 typedef struct _CM_MISC_STATE { 934 //DWORD 0 935 union{ 936 struct{ 937 DWORD Row0 : 16; 938 DWORD Reserved : 8; 939 DWORD Width : 4; 940 DWORD Height : 4; 941 }; 942 struct{ 943 DWORD value; 944 }; 945 } DW0; 946 947 //DWORD 1 948 union{ 949 struct{ 950 DWORD Row1 : 16; 951 DWORD Row2 : 16; 952 }; 953 struct{ 954 DWORD value; 955 }; 956 } DW1; 957 958 //DWORD 2 959 union{ 960 struct{ 961 DWORD Row3 : 16; 962 DWORD Row4 : 16; 963 }; 964 struct{ 965 DWORD value; 966 }; 967 } DW2; 968 969 //DWORD 3 970 union{ 971 struct{ 972 DWORD Row5 : 16; 973 DWORD Row6 : 16; 974 }; 975 struct{ 976 DWORD value; 977 }; 978 } DW3; 979 980 //DWORD 4 981 union{ 982 struct{ 983 DWORD Row7 : 16; 984 DWORD Row8 : 16; 985 }; 986 struct{ 987 DWORD value; 988 }; 989 } DW4; 990 991 //DWORD 5 992 union{ 993 struct{ 994 DWORD Row9 : 16; 995 DWORD Row10 : 16; 996 }; 997 struct{ 998 DWORD value; 999 }; 1000 } DW5; 1001 1002 //DWORD 6 1003 union{ 1004 struct{ 1005 DWORD Row11 : 16; 1006 DWORD Row12 : 16; 1007 }; 1008 struct{ 1009 DWORD value; 1010 }; 1011 } DW6; 1012 1013 //DWORD 7 1014 union{ 1015 struct{ 1016 DWORD Row13 : 16; 1017 DWORD Row14 : 16; 1018 }; 1019 struct{ 1020 DWORD value; 1021 }; 1022 } DW7; 1023 } CM_MISC_STATE; 1024 1025 typedef struct _CM_MISC_STATE_MSG{ 1026 //DWORD 0 1027 union{ 1028 struct{ 1029 DWORD Row0 : 16; 1030 DWORD Reserved : 8; 1031 DWORD Width : 4; 1032 DWORD Height : 4; 1033 }; 1034 struct{ 1035 DWORD value; 1036 }; 1037 }DW0; 1038 1039 //DWORD 1 1040 union{ 1041 struct{ 1042 DWORD Row1 : 16; 1043 DWORD Row2 : 16; 1044 }; 1045 struct{ 1046 DWORD value; 1047 }; 1048 }DW1; 1049 1050 //DWORD 2 1051 union{ 1052 struct{ 1053 DWORD Row3 : 16; 1054 DWORD Row4 : 16; 1055 }; 1056 struct{ 1057 DWORD value; 1058 }; 1059 }DW2; 1060 1061 //DWORD 3 1062 union{ 1063 struct{ 1064 DWORD Row5 : 16; 1065 DWORD Row6 : 16; 1066 }; 1067 struct{ 1068 DWORD value; 1069 }; 1070 }DW3; 1071 1072 //DWORD 4 1073 union{ 1074 struct{ 1075 DWORD Row7 : 16; 1076 DWORD Row8 : 16; 1077 }; 1078 struct{ 1079 DWORD value; 1080 }; 1081 }DW4; 1082 1083 //DWORD 5 1084 union{ 1085 struct{ 1086 DWORD Row9 : 16; 1087 DWORD Row10 : 16; 1088 }; 1089 struct{ 1090 DWORD value; 1091 }; 1092 }DW5; 1093 1094 //DWORD 6 1095 union{ 1096 struct{ 1097 DWORD Row11 : 16; 1098 DWORD Row12 : 16; 1099 }; 1100 struct{ 1101 DWORD value; 1102 }; 1103 }DW6; 1104 1105 //DWORD 7 1106 union{ 1107 struct{ 1108 DWORD Row13 : 16; 1109 DWORD Row14 : 16; 1110 }; 1111 struct{ 1112 DWORD value; 1113 }; 1114 }DW7; 1115 } CM_MISC_STATE_MSG; 1116 1117 enum CM_SAMPLER_STATE_TYPE { 1118 CM_SAMPLER8X8_AVS = 0, 1119 CM_SAMPLER8X8_CONV = 1, 1120 CM_SAMPLER8X8_MISC = 3, 1121 CM_SAMPLER8X8_CONV1DH = 4, 1122 CM_SAMPLER8X8_CONV1DV = 5, 1123 CM_SAMPLER8X8_AVS_EX = 6, 1124 CM_SAMPLER8X8_NONE 1125 }; 1126 1127 struct CM_SAMPLER_8X8_DESCR { 1128 CM_SAMPLER_STATE_TYPE stateType; 1129 union { 1130 CM_AVS_STATE_MSG *avs; 1131 CM_AVS_STATE_MSG_EX *avs_ex; 1132 CM_CONVOLVE_STATE_MSG *conv; 1133 CM_MISC_STATE_MSG *misc; //ERODE/DILATE/MINMAX 1134 }; 1135 }; 1136 1137 typedef struct _CM_VEBOX_STATE 1138 { 1139 1140 DWORD ColorGamutExpansionEnable : 1; 1141 DWORD ColorGamutCompressionEnable : 1; 1142 DWORD GlobalIECPEnable : 1; 1143 DWORD DNEnable : 1; 1144 DWORD DIEnable : 1; 1145 DWORD DNDIFirstFrame : 1; 1146 DWORD DownsampleMethod422to420 : 1; 1147 DWORD DownsampleMethod444to422 : 1; 1148 DWORD DIOutputFrames : 2; 1149 DWORD DemosaicEnable : 1; 1150 DWORD VignetteEnable : 1; 1151 DWORD AlphaPlaneEnable : 1; 1152 DWORD HotPixelFilteringEnable : 1; 1153 DWORD SingleSliceVeboxEnable : 1; 1154 DWORD LaceCorrectionEnable : BITFIELD_BIT(16); 1155 DWORD DisableEncoderStatistics : BITFIELD_BIT(17); 1156 DWORD DisableTemporalDenoiseFilter : BITFIELD_BIT(18); 1157 DWORD SinglePipeEnable : BITFIELD_BIT(19); 1158 DWORD __CODEGEN_UNIQUE(Reserved) : BITFIELD_BIT(20); 1159 DWORD ForwardGammaCorrectionEnable : BITFIELD_BIT(21); 1160 DWORD __CODEGEN_UNIQUE(Reserved) : BITFIELD_RANGE(22, 24); 1161 DWORD StateSurfaceControlBits : BITFIELD_RANGE(25, 31); 1162 } CM_VEBOX_STATE, *PCM_VEBOX_STATE; 1163 1164 typedef struct _CM_POWER_OPTION 1165 { 1166 USHORT nSlice; // set number of slice to use: 0(default number), 1, 2... 1167 USHORT nSubSlice; // set number of subslice to use: 0(default number), 1, 2... 1168 USHORT nEU; // set number of EU to use: 0(default number), 1, 2... 1169 } CM_POWER_OPTION, *PCM_POWER_OPTION; 1170 1171 // to support new flag with current API 1172 // new flag/field could be add to the end of this structure 1173 // 1174 struct CM_FLAG { 1175 CM_FLAG(); 1176 CM_ROTATION rotationFlag; 1177 INT chromaSiting; 1178 }; 1179 1180 struct _CM_TASK_CONFIG { 1181 bool turboBoostFlag : 1; 1182 bool fusedEuDispatchFlag : 1; 1183 uint32_t reserved_bits :30; 1184 uint32_t reserved0; 1185 uint32_t reserved1; 1186 uint32_t reserved2; 1187 }; 1188 1189 typedef enum _CM_KERNEL_EXEC_MODE { 1190 CM_KERNEL_EXECUTION_MODE_MONOPOLIZED = 0, // Kernel can occupy all DSS for execution */ 1191 CM_KERNEL_EXECUTION_MODE_CONCURRENT, // Kernel can occupy part of DSS and concurrently execute together with other workloads. 1192 } CM_KERNEL_EXEC_MODE; 1193 1194 struct CM_EXECUTION_CONFIG { 1195 CM_KERNEL_EXEC_MODE kernelExecutionMode = CM_KERNEL_EXECUTION_MODE_MONOPOLIZED; 1196 int concurrentPolicy = 0; // Reserve for future extension. 1197 }; 1198 1199 #define CM_TASK_CONFIG _CM_TASK_CONFIG 1200 1201 // parameters used to set the surface state of the buffer 1202 typedef struct _CM_SURFACE_MEM_OBJ_CTRL { 1203 MEMORY_OBJECT_CONTROL mem_ctrl; 1204 MEMORY_TYPE mem_type; 1205 INT age; 1206 } CM_SURFACE_MEM_OBJ_CTRL; 1207 1208 typedef struct _CM_BUFFER_STATE_PARAM 1209 { 1210 UINT uiSize; // the new size of the buffer, if it is 0, set it as the (original width - offset) 1211 UINT uiBaseAddressOffset; // offset should be 16-aligned 1212 CM_SURFACE_MEM_OBJ_CTRL mocs; // if not set (all zeros), then the aliases mocs setting is the same as the origin 1213 }CM_BUFFER_STATE_PARAM; 1214 1215 typedef struct _CM_SURFACE2D_STATE_PARAM 1216 { 1217 UINT format; 1218 UINT width; 1219 UINT height; 1220 UINT depth; 1221 UINT pitch; 1222 WORD memory_object_control; 1223 UINT surface_x_offset; 1224 UINT surface_y_offset; 1225 UINT reserved[4]; // for future usage 1226 } CM_SURFACE2D_STATE_PARAM; 1227 1228 struct _CM_QUEUE_CREATE_OPTION 1229 { 1230 CM_QUEUE_TYPE QueueType : 3; 1231 bool RAMode : 1; 1232 unsigned int Reserved0 : 3; 1233 bool UserGPUContext : 1; // Is the user-provided GPU Context already created externally 1234 unsigned int GPUContext : 8; // user-provided GPU Context ordinal 1235 CM_QUEUE_SSEU_USAGE_HINT_TYPE SseuUsageHint : 3; 1236 unsigned int Reserved1 : 1; 1237 unsigned int Reserved2 : 12; 1238 }; 1239 #define CM_QUEUE_CREATE_OPTION _CM_QUEUE_CREATE_OPTION 1240 1241 typedef enum _CM_CONDITIONAL_END_OPERATOR_CODE { 1242 MAD_GREATER_THAN_IDD = 0, 1243 MAD_GREATER_THAN_OR_EQUAL_IDD, 1244 MAD_LESS_THAN_IDD, 1245 MAD_LESS_THAN_OR_EQUAL_IDD, 1246 MAD_EQUAL_IDD, 1247 MAD_NOT_EQUAL_IDD 1248 } CM_CONDITIONAL_END_OPERATOR_CODE; 1249 1250 struct CM_CONDITIONAL_END_PARAM { 1251 DWORD opValue; 1252 CM_CONDITIONAL_END_OPERATOR_CODE opCode; 1253 bool opMask; 1254 bool opLevel; 1255 }; 1256 1257 struct CM_KERNEL_SYNC_CONFIG { 1258 bool dataCacheFlush : 1; // true: cache will be flushed; 1259 uint32_t reserved : 31; 1260 }; 1261 1262 //********************************************************************** 1263 // Classes forward declarations 1264 //********************************************************************** 1265 class CmSampler8x8; 1266 class CmEvent; 1267 class CmThreadGroupSpace; 1268 class CmKernel; 1269 class CmTask; 1270 class CmProgram; 1271 class CmBuffer; 1272 class CmBufferUP; 1273 class CmBufferSVM; 1274 class CmBufferStateless; 1275 class CmSurface2D; 1276 class CmSurface2DUP; 1277 class CmSurface2DStateless; 1278 class CmSurface3D; 1279 class CmSampler; 1280 class CmThreadSpace; 1281 class CmVebox; 1282 class CmQueue; 1283 class SurfaceIndex; 1284 class SamplerIndex; 1285 1286 //********************************************************************** 1287 // Extended definitions if any 1288 //********************************************************************** 1289 #include "cm_rt_extension.h" 1290 1291 //********************************************************************** 1292 // Constants 1293 //********************************************************************** 1294 const CM_QUEUE_CREATE_OPTION CM_DEFAULT_QUEUE_CREATE_OPTION = { CM_QUEUE_TYPE_RENDER, false, 0, false, 0, CM_QUEUE_SSEU_USAGE_HINT_DEFAULT, 0, 0 }; 1295 1296 //********************************************************************** 1297 // Classes 1298 //********************************************************************** 1299 class CmSampler8x8 1300 { 1301 public: 1302 CM_RT_API virtual INT GetIndex( SamplerIndex* & pIndex ) = 0 ; 1303 protected: ~CmSampler8x8()1304 ~CmSampler8x8(){}; 1305 }; 1306 1307 class CmEvent 1308 { 1309 public: 1310 CM_RT_API virtual INT GetStatus( CM_STATUS& status) = 0 ; 1311 CM_RT_API virtual INT GetExecutionTime(UINT64& time) = 0; 1312 CM_RT_API virtual INT WaitForTaskFinished(DWORD dwTimeOutMs = CM_MAX_TIMEOUT_MS) = 0 ; 1313 CM_RT_API virtual INT GetSurfaceDetails( UINT kernIndex, UINT surfBTI,CM_SURFACE_DETAILS& outDetails )=0; 1314 CM_RT_API virtual INT GetProfilingInfo(CM_EVENT_PROFILING_INFO infoType, size_t paramSize, PVOID pInputValue, PVOID pValue) = 0; 1315 CM_RT_API virtual INT GetExecutionTickTime(UINT64& ticks) = 0; 1316 protected: ~CmEvent()1317 ~CmEvent(){}; 1318 }; 1319 1320 class CmKernel 1321 { 1322 public: 1323 CM_RT_API virtual INT SetThreadCount(UINT count ) = 0; 1324 CM_RT_API virtual INT SetKernelArg(UINT index, size_t size, const void * pValue ) = 0; 1325 CM_RT_API virtual INT SetThreadArg(UINT threadId, UINT index, size_t size, const void * pValue ) = 0; 1326 CM_RT_API virtual INT SetStaticBuffer(UINT index, const void * pValue ) = 0; 1327 CM_RT_API virtual INT SetSurfaceBTI(SurfaceIndex* pSurface, UINT BTIndex) = 0; 1328 CM_RT_API virtual INT AssociateThreadSpace(CmThreadSpace* & pTS) = 0; 1329 CM_RT_API virtual INT AssociateThreadGroupSpace(CmThreadGroupSpace* & pTGS) = 0; 1330 CM_RT_API virtual INT SetSamplerBTI(SamplerIndex* pSampler, UINT nIndex) = 0; 1331 CM_RT_API virtual INT DeAssociateThreadSpace(CmThreadSpace* & pTS) = 0; 1332 CM_RT_API virtual INT DeAssociateThreadGroupSpace(CmThreadGroupSpace* & pTGS) = 0; 1333 CM_RT_API virtual INT QuerySpillSize(unsigned int &spillSize) = 0; 1334 CM_RT_API virtual INT SetKernelArgPointer(UINT index, size_t size, const void *pValue) = 0; 1335 1336 protected: ~CmKernel()1337 ~CmKernel(){}; 1338 }; 1339 1340 class CmTask 1341 { 1342 public: 1343 CM_RT_API virtual INT AddKernel(CmKernel *pKernel) = 0; 1344 CM_RT_API virtual INT Reset(void) = 0; 1345 CM_RT_API virtual INT AddSync(void) = 0; 1346 CM_RT_API virtual INT SetPowerOption( PCM_POWER_OPTION pCmPowerOption ) = 0; 1347 CM_RT_API virtual INT AddConditionalEnd(SurfaceIndex* pSurface, UINT offset, CM_CONDITIONAL_END_PARAM *pCondParam) = 0; 1348 CM_RT_API virtual INT SetProperty(const CM_TASK_CONFIG &taskConfig) = 0; 1349 CM_RT_API virtual INT AddKernelWithConfig( CmKernel *pKernel, const CM_EXECUTION_CONFIG *config ) = 0; 1350 CM_RT_API virtual INT GetProperty(CM_TASK_CONFIG &taskConfig) = 0; 1351 CM_RT_API virtual INT AddSyncEx(const CM_KERNEL_SYNC_CONFIG *config) = 0; 1352 protected: ~CmTask()1353 ~CmTask(){}; 1354 }; 1355 1356 class CmBuffer 1357 { 1358 public: 1359 CM_RT_API virtual INT GetIndex( SurfaceIndex*& pIndex ) = 0; 1360 CM_RT_API virtual INT ReadSurface( unsigned char* pSysMem, CmEvent* pEvent, UINT64 sysMemSize = 0xFFFFFFFFFFFFFFFFULL ) = 0; 1361 CM_RT_API virtual INT WriteSurface( const unsigned char* pSysMem, CmEvent* pEvent, UINT64 sysMemSize = 0xFFFFFFFFFFFFFFFFULL ) = 0; 1362 CM_RT_API virtual INT InitSurface(const DWORD initValue, CmEvent* pEvent) = 0; 1363 CM_RT_API virtual INT SelectMemoryObjectControlSetting(MEMORY_OBJECT_CONTROL option) = 0; 1364 CM_RT_API virtual INT SetSurfaceStateParam(SurfaceIndex *pSurfIndex, const CM_BUFFER_STATE_PARAM *pSSParam) = 0; 1365 protected: ~CmBuffer()1366 ~CmBuffer(){}; 1367 }; 1368 1369 class CmBufferUP 1370 { 1371 public: 1372 CM_RT_API virtual INT GetIndex( SurfaceIndex*& pIndex ) = 0; 1373 CM_RT_API virtual INT SelectMemoryObjectControlSetting(MEMORY_OBJECT_CONTROL option) = 0; 1374 protected: ~CmBufferUP()1375 ~CmBufferUP(){}; 1376 }; 1377 1378 class CmBufferSVM 1379 { 1380 public: 1381 CM_RT_API virtual INT GetIndex( SurfaceIndex*& pIndex ) = 0; 1382 CM_RT_API virtual INT GetAddress( void * &pAddr) = 0; 1383 protected: ~CmBufferSVM()1384 ~CmBufferSVM(){}; 1385 }; 1386 1387 class CmBufferStateless 1388 { 1389 public: 1390 CM_RT_API virtual INT GetGfxAddress(uint64_t &gfxAddr) = 0; 1391 CM_RT_API virtual INT GetSysAddress(void *&pSysAddr) = 0; 1392 CM_RT_API virtual INT ReadSurface(unsigned char *pSysMem, 1393 CmEvent *pEvent, 1394 uint64_t sysMemSize = 0xFFFFFFFFFFFFFFFFULL) = 0; 1395 CM_RT_API virtual INT WriteSurface(const unsigned char *pSysMem, 1396 CmEvent *pEvent, 1397 uint64_t sysMemSize = 0xFFFFFFFFFFFFFFFFULL) = 0; 1398 protected: ~CmBufferStateless()1399 ~CmBufferStateless() {}; 1400 }; 1401 1402 class CmSurface2DUP 1403 { 1404 public: 1405 CM_RT_API virtual INT GetIndex( SurfaceIndex*& pIndex ) = 0; 1406 CM_RT_API virtual INT SelectMemoryObjectControlSetting(MEMORY_OBJECT_CONTROL option) = 0; 1407 CM_RT_API virtual INT SetProperty(CM_FRAME_TYPE frameType) = 0; 1408 protected: ~CmSurface2DUP()1409 ~CmSurface2DUP(){}; 1410 }; 1411 1412 class CmSurface2DStateless 1413 { 1414 public: 1415 CM_RT_API virtual INT GetGfxAddress(uint64_t &gfxAddr) = 0; 1416 CM_RT_API virtual INT ReadSurface(unsigned char *pSysMem, 1417 CmEvent *pEvent, 1418 uint64_t sysMemSize = 0xFFFFFFFFFFFFFFFFULL) = 0; 1419 CM_RT_API virtual INT WriteSurface(const unsigned char *pSysMem, 1420 CmEvent *pEvent, 1421 uint64_t sysMemSize = 0xFFFFFFFFFFFFFFFFULL) = 0; 1422 protected: ~CmSurface2DStateless()1423 ~CmSurface2DStateless(){}; 1424 }; 1425 1426 class CmSurface3D 1427 { 1428 public: 1429 CM_RT_API virtual INT GetIndex( SurfaceIndex*& pIndex ) = 0; 1430 CM_RT_API virtual INT ReadSurface( unsigned char* pSysMem, CmEvent* pEvent, UINT64 sysMemSize = 0xFFFFFFFFFFFFFFFFULL ) = 0; 1431 CM_RT_API virtual INT WriteSurface( const unsigned char* pSysMem, CmEvent* pEvent, UINT64 sysMemSize = 0xFFFFFFFFFFFFFFFFULL ) = 0; 1432 CM_RT_API virtual INT InitSurface(const DWORD initValue, CmEvent* pEvent) = 0; 1433 CM_RT_API virtual INT SelectMemoryObjectControlSetting(MEMORY_OBJECT_CONTROL option) = 0; 1434 protected: ~CmSurface3D()1435 ~CmSurface3D(){}; 1436 }; 1437 1438 class CmSampler 1439 { 1440 public: 1441 CM_RT_API virtual INT GetIndex( SamplerIndex* & pIndex ) = 0 ; 1442 protected: ~CmSampler()1443 ~CmSampler(){}; 1444 }; 1445 1446 class CmThreadSpace 1447 { 1448 public: 1449 CM_RT_API virtual INT AssociateThread( UINT x, UINT y, CmKernel* pKernel , UINT threadId ) = 0; 1450 CM_RT_API virtual INT SelectThreadDependencyPattern ( CM_DEPENDENCY_PATTERN pattern ) = 0; 1451 CM_RT_API virtual INT AssociateThreadWithMask( UINT x, UINT y, CmKernel* pKernel , UINT threadId, BYTE nDependencyMask ) = 0; 1452 CM_RT_API virtual INT SetThreadSpaceColorCount( UINT colorCount ) = 0; 1453 CM_RT_API virtual INT SelectMediaWalkingPattern( CM_WALKING_PATTERN pattern ) = 0; 1454 CM_RT_API virtual INT Set26ZIDispatchPattern( CM_26ZI_DISPATCH_PATTERN pattern ) = 0; 1455 CM_RT_API virtual INT Set26ZIMacroBlockSize( UINT width, UINT height ) = 0; 1456 CM_RT_API virtual INT SetMediaWalkerGroupSelect(CM_MW_GROUP_SELECT groupSelect) = 0; 1457 CM_RT_API virtual INT SelectMediaWalkingParameters( CM_WALKING_PARAMETERS paramaters ) = 0; 1458 CM_RT_API virtual INT SelectThreadDependencyVectors( CM_DEPENDENCY dependVectors ) = 0; 1459 CM_RT_API virtual INT SetThreadSpaceOrder(UINT threadCount, PCM_THREAD_PARAM pThreadSpaceOrder) = 0; 1460 protected: ~CmThreadSpace()1461 ~CmThreadSpace(){}; 1462 }; 1463 1464 class CmVebox 1465 { 1466 public: 1467 CM_RT_API virtual INT SetState(CM_VEBOX_STATE& VeBoxState) = 0; 1468 1469 CM_RT_API virtual INT SetCurFrameInputSurface( CmSurface2D* pSurf ) = 0; 1470 CM_RT_API virtual INT SetCurFrameInputSurfaceControlBits( const WORD ctrlBits ) = 0; 1471 1472 CM_RT_API virtual INT SetPrevFrameInputSurface( CmSurface2D* pSurf ) = 0; 1473 CM_RT_API virtual INT SetPrevFrameInputSurfaceControlBits( const WORD ctrlBits ) = 0; 1474 1475 CM_RT_API virtual INT SetSTMMInputSurface( CmSurface2D* pSurf ) = 0; 1476 CM_RT_API virtual INT SetSTMMInputSurfaceControlBits( const WORD ctrlBits ) = 0; 1477 1478 CM_RT_API virtual INT SetSTMMOutputSurface( CmSurface2D* pSurf ) = 0; 1479 CM_RT_API virtual INT SetSTMMOutputSurfaceControlBits( const WORD ctrlBits ) = 0; 1480 1481 CM_RT_API virtual INT SetDenoisedCurFrameOutputSurface( CmSurface2D* pSurf ) = 0; 1482 CM_RT_API virtual INT SetDenoisedCurOutputSurfaceControlBits( const WORD ctrlBits ) = 0; 1483 1484 CM_RT_API virtual INT SetCurFrameOutputSurface( CmSurface2D* pSurf ) = 0; 1485 CM_RT_API virtual INT SetCurFrameOutputSurfaceControlBits( const WORD ctrlBits ) = 0; 1486 1487 CM_RT_API virtual INT SetPrevFrameOutputSurface( CmSurface2D* pSurf ) = 0; 1488 CM_RT_API virtual INT SetPrevFrameOutputSurfaceControlBits( const WORD ctrlBits ) = 0; 1489 1490 CM_RT_API virtual INT SetStatisticsOutputSurface( CmSurface2D* pSurf ) = 0; 1491 CM_RT_API virtual INT SetStatisticsOutputSurfaceControlBits( const WORD ctrlBits ) = 0; 1492 CM_RT_API virtual INT SetParam(CmBufferUP *pParamBuffer) = 0; 1493 protected: ~CmVebox()1494 ~CmVebox(){}; 1495 }; 1496 1497 class CmQueue 1498 { 1499 public: 1500 CM_RT_API virtual INT Enqueue( CmTask* pTask, CmEvent* & pEvent, const CmThreadSpace* pTS = nullptr ) = 0; 1501 CM_RT_API virtual INT DestroyEvent( CmEvent* & pEvent ) = 0; 1502 CM_RT_API virtual INT EnqueueWithGroup( CmTask* pTask, CmEvent* & pEvent, const CmThreadGroupSpace* pTGS = nullptr )=0; 1503 CM_RT_API virtual INT EnqueueCopyCPUToGPU( CmSurface2D* pSurface, const unsigned char* pSysMem, CmEvent* & pEvent ) = 0; 1504 CM_RT_API virtual INT EnqueueCopyGPUToCPU( CmSurface2D* pSurface, unsigned char* pSysMem, CmEvent* & pEvent ) = 0; 1505 CM_RT_API virtual INT EnqueueInitSurface2D( CmSurface2D* pSurface, const DWORD initValue, CmEvent* &pEvent ) = 0; 1506 CM_RT_API virtual INT EnqueueCopyGPUToGPU( CmSurface2D* pOutputSurface, CmSurface2D* pInputSurface, UINT option, CmEvent* & pEvent ) = 0; 1507 CM_RT_API virtual INT EnqueueCopyCPUToCPU( unsigned char* pDstSysMem, unsigned char* pSrcSysMem, UINT size, UINT option, CmEvent* & pEvent ) = 0; 1508 1509 CM_RT_API virtual INT EnqueueCopyCPUToGPUFullStride( CmSurface2D* pSurface, const unsigned char* pSysMem, const UINT widthStride, const UINT heightStride, const UINT option, CmEvent* & pEvent ) = 0; 1510 CM_RT_API virtual INT EnqueueCopyGPUToCPUFullStride( CmSurface2D* pSurface, unsigned char* pSysMem, const UINT widthStride, const UINT heightStride, const UINT option, CmEvent* & pEvent ) = 0; 1511 1512 CM_RT_API virtual INT EnqueueCopyCPUToGPUFullStrideDup( CmSurface2D* pSurface, const unsigned char* pSysMem, const UINT widthStride, const UINT heightStride, const UINT option, CmEvent* & pEvent ) = 0; 1513 CM_RT_API virtual INT EnqueueCopyGPUToCPUFullStrideDup( CmSurface2D* pSurface, unsigned char* pSysMem, const UINT widthStride, const UINT heightStride, const UINT option, CmEvent* & pEvent ) = 0; 1514 1515 CM_RT_API virtual INT EnqueueWithHints( CmTask* pTask, CmEvent* & pEvent, UINT hints = 0) = 0; 1516 CM_RT_API virtual INT EnqueueVebox( CmVebox* pVebox, CmEvent* & pEvent ) = 0; 1517 1518 CM_RT_API virtual INT EnqueueFast(CmTask *task, 1519 CmEvent *&event, 1520 const CmThreadSpace *threadSpace = nullptr) = 0; 1521 CM_RT_API virtual INT DestroyEventFast(CmEvent *&event) = 0; 1522 CM_RT_API virtual INT EnqueueWithGroupFast(CmTask *task, 1523 CmEvent *&event, 1524 const CmThreadGroupSpace *threadGroupSpace = nullptr) = 0; 1525 1526 CM_RT_API virtual int32_t EnqueueReadBuffer(CmBuffer* buffer, size_t offset, const unsigned char* sysMem, uint64_t sysMemSize, CmEvent* wait_event, CmEvent*& event, unsigned option) = 0; 1527 CM_RT_API virtual int32_t EnqueueWriteBuffer(CmBuffer* buffer, size_t offset, const unsigned char* sysMem, uint64_t sysMemSize, CmEvent* wait_event, CmEvent*& event, unsigned option) = 0; 1528 1529 CM_RT_API virtual INT SetResidentGroupAndParallelThreadNum(uint32_t residentGroupNum, uint32_t parallelThreadNum) = 0; 1530 1531 protected: ~CmQueue()1532 ~CmQueue(){}; 1533 }; 1534 1535 //********************************************************************** 1536 // Function pointer types 1537 //********************************************************************** 1538 typedef void (CM_CALLBACK *callback_function)(CmEvent*, void *); 1539 typedef void (*IMG_WALKER_FUNTYPE)(void* img, void* arg); 1540 1541 //********************************************************************** 1542 // OS-specific APIs and classes 1543 //********************************************************************** 1544 #include "cm_rt_api_os.h" 1545 1546 //********************************************************************** 1547 // Functions declaration 1548 //********************************************************************** 1549 EXTERN_C CM_RT_API INT DestroyCmDevice(CmDevice* &device); 1550 EXTERN_C CM_RT_API INT CMRT_Enqueue(CmQueue* queue, CmTask* task, CmEvent** event, const CmThreadSpace* threadSpace = nullptr); 1551 EXTERN_C CM_RT_API const char* GetCmErrorString(int errCode); 1552 1553 //********************************************************************** 1554 // Platfom specific definitions 1555 //********************************************************************** 1556 #include "cm_rt_g8.h" 1557 #include "cm_rt_g9.h" 1558 #include "cm_rt_g10.h" 1559 #include "cm_rt_g11.h" 1560 #include "cm_rt_g12_tgl.h" 1561 #include "cm_rt_g12_dg1.h" 1562 1563 #endif //__CM_RT_H__ 1564