1 /* 2 * Copyright (c) 2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __DEVCONFIG_H__ 23 #define __DEVCONFIG_H__ 24 25 #include <stdint.h> 26 #include <string.h> 27 28 #define LOCAL_I915_PARAM_HAS_HUC 42 29 #define TEST_COUT std::cout << "[ INFO ] " 30 31 extern const char *g_platformName[]; 32 33 struct DeviceConfig 34 { 35 uint64_t aperture_size; // DRM_IOCTL_I915_GEM_GET_APERTURE 36 uint32_t DeviceId; // I915_PARAM_CHIPSET_ID 37 uint32_t revision; // I915_PARAM_REVISION 38 39 union 40 { 41 uint32_t flags; // Should put this before the struct, otherwise, it would be error in libdrm. 42 43 struct 44 { 45 uint32_t has_exec2 :1; // I915_PARAM_HAS_EXECBUF2 46 uint32_t has_bsd :1; // I915_PARAM_HAS_BSD 47 uint32_t has_blt :1; // I915_PARAM_HAS_BLT 48 uint32_t has_relaxed_fencing :1; // I915_PARAM_HAS_RELAXED_FENCING 49 uint32_t has_wait_timeout :1; // I915_PARAM_HAS_WAIT_TIMEOUT 50 uint32_t has_llc :1; // I915_PARAM_HAS_LLC 51 uint32_t has_vebox :1; // I915_PARAM_HAS_VEBOX 52 uint32_t has_ext_mmap :1; // I915_PARAM_MMAP_VERSION 53 uint32_t has_exec_softpin :1; // I915_PARAM_HAS_EXEC_SOFTPIN 54 uint32_t has_exec_async :1; // I915_PARAM_HAS_EXEC_ASYNC 55 uint32_t has_bsd2 :1; // I915_PARAM_HAS_BSD 56 uint32_t has_huc :1; // I915_PARAM_HAS_HUC 57 uint32_t reserved :20; 58 }; 59 }; 60 61 int32_t num_fences_avail; // I915_PARAM_NUM_FENCES_AVAIL 62 int32_t aliasing_ppgtt; // I915_PARAM_HAS_ALIASING_PPGTT 63 int32_t subslice_total; // I915_PARAM_SUBSLICE_TOTAL 64 int32_t eu_total; // I915_PARAM_EU_TOTAL 65 uint64_t edram_reg; 66 } const DeviceConfigTable[] = { 67 #define DEVICECONFIG( aper, devId, rev, flags, fences,ppgtt,subslice, eu, edram_reg ) { aper, devId, rev, flags, fences,ppgtt,subslice, eu, edram_reg}, 68 DEVICECONFIG( 4286468096, 0x191e, 0x7, 0x01ff, 32, 3, 3, 24, 0x0 ) // SKL 69 DEVICECONFIG( 4267114496, 0x5a84, 0xb, 0x03df, 32, 3, 3, 18, 0x0 ) // BXT 70 DEVICECONFIG( 4248690688, 0x1606, 0x9, 0x03ff, 32, 3, 2, 12, 0x0 ) // BDW 71 DEVICECONFIG( 4259069952, 0x5a49, 0x3, 0x03ff, 32, 3, 2, 16, 0x0 ) // CNL 72 DEVICECONFIG( 0, 0x0, 0x0, 0x0, 0, 0, 0, 0, 0x0 ) 73 #undef DEVICECONFIG 74 }; 75 76 typedef struct DeviceConfig DeviceConfig_t; 77 78 typedef enum 79 { 80 igfxSKLAKE = 0, 81 igfxBROXTON = 1, 82 igfxBROADWELL = 2, 83 igfxCANNONLAKE = 3, 84 igfx_MAX = 4, 85 } Platform_t; 86 87 extern const char *g_platformName[]; 88 89 #endif // __DEVCONFIG_H__ 90