1 /******************************************************************************
2 *
3 * Copyright (C) 2022 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /**
22 *******************************************************************************
23 * @file
24 * isvce_api.c
25 *
26 * @brief
27 * Contains api function definitions for H264 encoder
28 *
29 * @author
30 * ittiam
31 *
32 * @par List of Functions:
33 * - api_check_struct_sanity()
34 * - isvce_codec_update_config()
35 * - isvce_set_default_params()
36 * - isvce_init()
37 * - isvce_get_num_rec()
38 * - isvce_fill_num_mem_rec()
39 * - isvce_init_mem_rec()
40 * - isvce_retrieve_memrec()
41 * - isvce_set_flush_mode()
42 * - isvce_get_buf_info()
43 * - isvce_set_dimensions()
44 * - isvce_set_frame_rate()
45 * - isvce_set_bit_rate()
46 * - isvce_set_frame_type()
47 * - isvce_set_qp()
48 * - isvce_set_enc_mode()
49 * - isvce_set_vbv_params()
50 * - isvc_set_air_params()
51 * - isvc_set_me_params()
52 * - isvc_set_ipe_params()
53 * - isvc_set_gop_params()
54 * - isvc_set_profile_params()
55 * - isvc_set_deblock_params()
56 * - isvce_set_num_cores()
57 * - isvce_reset()
58 * - isvce_ctl()
59 * - isvce_api_function()
60 *
61 * @remarks
62 * None
63 *
64 *******************************************************************************
65 */
66
67 /*****************************************************************************/
68 /* File Includes */
69 /*****************************************************************************/
70
71 #include <stdio.h>
72 #include <stddef.h>
73 #include <stdlib.h>
74 #include <string.h>
75 #include <limits.h>
76 #include <assert.h>
77 #include <math.h>
78 #include <stdbool.h>
79
80 #include "ih264_typedefs.h"
81 /* Dependencies of ih264_buf_mgr.h */
82 /* Dependencies of ih264_list.h */
83 #include "ih264_error.h"
84 /* Dependencies of ih264_common_tables.h */
85 #include "ih264_defs.h"
86 #include "ih264_structs.h"
87 #include "ih264_buf_mgr.h"
88 #include "ih264_common_tables.h"
89 #include "ih264_dpb_mgr.h"
90 #include "ih264_list.h"
91 #include "ih264_platform_macros.h"
92 #include "ih264_trans_data.h"
93 #include "ih264_size_defs.h"
94 /* Dependencies of ih264e_cabac_structs.h */
95 #include "ih264_cabac_tables.h"
96 /* Dependencies of ime_structs.h */
97 #include "ime_defs.h"
98 #include "ime_distortion_metrics.h"
99 /* Dependencies of ih264e_structs.h */
100 #include "iv2.h"
101 #include "ive2.h"
102 #include "ih264_defs.h"
103 #include "ih264_deblk_edge_filters.h"
104 #include "ih264_inter_pred_filters.h"
105 #include "ih264_structs.h"
106 #include "ih264_trans_quant_itrans_iquant.h"
107 /* Dependencies of ih264e_bitstream.h */
108 #include "ih264e_error.h"
109 #include "ih264e_bitstream.h"
110 #include "ih264e_cabac_structs.h"
111 #include "irc_cntrl_param.h"
112 #include "irc_frame_info_collector.h"
113 #include "ime_statistics.h"
114 #include "ime_structs.h"
115 /* Dependencies of 'ih264e_utils.h' */
116 #include "ih264e_defs.h"
117 #include "irc_mem_req_and_acq.h"
118 #include "ih264e_rc_mem_interface.h"
119 #include "ih264e_structs.h"
120 #include "ih264e_utils.h"
121 #include "ih264e_version.h"
122 #include "ime.h"
123 #include "isvce.h"
124 #include "isvce_cabac.h"
125 #include "isvce_deblk.h"
126 #include "isvce_defs.h"
127 #include "isvce_downscaler.h"
128 #include "isvce_encode.h"
129 #include "isvce_encode_header.h"
130 #include "isvce_ibl_eval.h"
131 #include "isvce_ilp_mv.h"
132 #include "isvce_intra_modes_eval.h"
133 #include "isvce_me.h"
134 #include "isvce_platform_macros.h"
135 #include "isvce_rate_control.h"
136 #include "isvce_rc_mem_interface.h"
137 #include "isvce_residual_pred.h"
138 #include "isvce_sub_pic_rc.h"
139 #include "isvce_utils.h"
140
141 /*****************************************************************************/
142 /* Function Declarations */
143 /*****************************************************************************/
144
145 /*****************************************************************************/
146 /* Function Definitions */
147 /*****************************************************************************/
148
149 /**
150 *******************************************************************************
151 *
152 * @brief
153 * Used to test arguments for corresponding API call
154 *
155 * @par Description:
156 * For each command the arguments are validated
157 *
158 * @param[in] ps_handle
159 * Codec handle at API level
160 *
161 * @param[in] pv_api_ip
162 * Pointer to input structure
163 *
164 * @param[out] pv_api_op
165 * Pointer to output structure
166 *
167 * @returns error status
168 *
169 * @remarks none
170 *
171 *******************************************************************************
172 */
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op,isvce_api_cmds_t * ps_iv_api_cmds)173 static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, void *pv_api_ip, void *pv_api_op,
174 isvce_api_cmds_t *ps_iv_api_cmds)
175 {
176 WORD32 i, j;
177
178 /* output structure expected by the api call */
179 UWORD32 *pu4_api_op = pv_api_op;
180
181 ISVCE_API_COMMAND_TYPE_T e_cmd = ps_iv_api_cmds->e_cmd;
182 ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd = ps_iv_api_cmds->e_ctl_cmd;
183
184 if(NULL == pv_api_op || NULL == pv_api_ip)
185 {
186 return (IV_FAIL);
187 }
188
189 /* set error code */
190 pu4_api_op[1] = 0;
191
192 /* error checks on handle */
193 switch(e_cmd)
194 {
195 case ISVCE_CMD_GET_NUM_MEM_REC:
196 case ISVCE_CMD_FILL_NUM_MEM_REC:
197 {
198 break;
199 }
200
201 case ISVCE_CMD_INIT:
202 {
203 if(ps_handle == NULL)
204 {
205 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
206 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
207 return IV_FAIL;
208 }
209
210 if(ps_handle->u4_size != sizeof(iv_obj_t))
211 {
212 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
213 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
214 return IV_FAIL;
215 }
216
217 break;
218 }
219 case ISVCE_CMD_RETRIEVE_MEMREC:
220 case ISVCE_CMD_VIDEO_CTL:
221 case ISVCE_CMD_VIDEO_ENCODE:
222 {
223 if(ps_handle == NULL)
224 {
225 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
226 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
227 return IV_FAIL;
228 }
229
230 if(ps_handle->u4_size != sizeof(iv_obj_t))
231 {
232 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
233 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
234 return IV_FAIL;
235 }
236
237 if(ps_handle->pv_fxns != isvce_api_function)
238 {
239 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
240 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL;
241 return IV_FAIL;
242 }
243
244 if(ps_handle->pv_codec_handle == NULL)
245 {
246 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
247 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE;
248 return IV_FAIL;
249 }
250
251 break;
252 }
253 default:
254 {
255 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
256 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
257
258 return IV_FAIL;
259 }
260 }
261
262 /* error checks on input output structures */
263 switch(e_cmd)
264 {
265 case ISVCE_CMD_GET_NUM_MEM_REC:
266 {
267 isvce_num_mem_rec_ip_t *ps_ip = pv_api_ip;
268 isvce_num_mem_rec_op_t *ps_op = pv_api_op;
269
270 ps_op->s_ive_op.u4_error_code = 0;
271
272 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_num_mem_rec_ip_t))
273 {
274 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
275 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
276 return (IV_FAIL);
277 }
278
279 if(ps_op->s_ive_op.u4_size != sizeof(isvce_num_mem_rec_op_t))
280 {
281 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
282 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
283 return (IV_FAIL);
284 }
285
286 break;
287 }
288 case ISVCE_CMD_FILL_NUM_MEM_REC:
289 {
290 isvce_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
291 isvce_fill_mem_rec_op_t *ps_op = pv_api_op;
292
293 iv_mem_rec_t *ps_mem_rec = NULL;
294
295 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
296 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
297
298 ps_op->s_ive_op.u4_error_code = 0;
299
300 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_fill_mem_rec_ip_t))
301 {
302 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
303 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
304 return (IV_FAIL);
305 }
306
307 if(ps_op->s_ive_op.u4_size != sizeof(isvce_fill_mem_rec_op_t))
308 {
309 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
310 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
311 return (IV_FAIL);
312 }
313
314 if(max_wd < MIN_WD || max_wd > MAX_WD)
315 {
316 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
317 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
318 return (IV_FAIL);
319 }
320
321 if(max_ht < MIN_HT || max_ht > MAX_HT)
322 {
323 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
324 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
325 return (IV_FAIL);
326 }
327
328 /* verify number of mem rec ptr */
329 if(NULL == ps_ip->s_ive_ip.ps_mem_rec)
330 {
331 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
332 ps_op->s_ive_op.u4_error_code |= IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
333 return (IV_FAIL);
334 }
335
336 /* verify number of mem records */
337 if(ps_ip->s_ive_ip.u4_num_mem_rec != ISVCE_MEM_REC_CNT)
338 {
339 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
340 ps_op->s_ive_op.u4_error_code |= IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
341 return IV_FAIL;
342 }
343
344 /* check mem records sizes are correct */
345 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
346 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
347 {
348 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
349 {
350 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
351 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
352 return IV_FAIL;
353 }
354 }
355
356 break;
357 }
358 case ISVCE_CMD_INIT:
359 {
360 isvce_init_ip_t *ps_ip = pv_api_ip;
361 isvce_init_op_t *ps_op = pv_api_op;
362
363 iv_mem_rec_t *ps_mem_rec = NULL;
364
365 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
366 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
367 WORD32 wd = ALIGN16(ps_ip->u4_wd);
368 WORD32 ht = ALIGN16(ps_ip->u4_ht);
369
370 ps_op->s_ive_op.u4_error_code = 0;
371
372 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_init_ip_t))
373 {
374 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
375 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT;
376 return (IV_FAIL);
377 }
378
379 if(ps_op->s_ive_op.u4_size != sizeof(isvce_init_op_t))
380 {
381 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
382 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT;
383 return (IV_FAIL);
384 }
385
386 if(max_wd < MIN_WD || max_wd > MAX_WD)
387 {
388 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
389 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
390 return (IV_FAIL);
391 }
392
393 if(max_ht < MIN_HT || max_ht > MAX_HT)
394 {
395 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
396 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
397 return (IV_FAIL);
398 }
399
400 if(ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT ||
401 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT)
402 {
403 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
404 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
405 return (IV_FAIL);
406 }
407
408 if(ps_ip->s_ive_ip.u4_max_reorder_cnt != 0)
409 {
410 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
411 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
412 return (IV_FAIL);
413 }
414
415 if((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10) &&
416 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B) &&
417 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11) &&
418 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12) &&
419 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13) &&
420 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20) &&
421 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21) &&
422 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22) &&
423 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30) &&
424 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31) &&
425 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32) &&
426 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40) &&
427 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41) &&
428 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42) &&
429 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50) &&
430 (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51))
431 {
432 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
433 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
434 return (IV_FAIL);
435 }
436
437 if(ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P)
438 {
439 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
440 ps_op->s_ive_op.u4_error_code |= IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED;
441 return (IV_FAIL);
442 }
443
444 if((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE) &&
445 (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE) &&
446 (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY))
447 {
448 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
449 ps_op->s_ive_op.u4_error_code |= IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED;
450 return (IV_FAIL);
451 }
452
453 if(ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE)
454 {
455 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
456 ps_op->s_ive_op.u4_error_code |= IH264E_FRAME_RATE_NOT_SUPPORTED;
457 return (IV_FAIL);
458 }
459
460 for(i = 0; i < ps_ip->s_svc_inp_params.u1_num_spatial_layers; i++)
461 {
462 if(ps_ip->pu4_max_bitrate[i] > DEFAULT_MAX_BITRATE)
463 {
464 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
465 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
466 return (IV_FAIL);
467 }
468 }
469
470 if(ps_ip->s_ive_ip.u4_num_bframes > SVC_MAX_NUM_BFRAMES)
471 {
472 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
473 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
474 return (IV_FAIL);
475 }
476
477 if(ps_ip->s_ive_ip.u4_num_bframes && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2))
478 {
479 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
480 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
481 return (IV_FAIL);
482 }
483
484 if(ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE)
485 {
486 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
487 ps_op->s_ive_op.u4_error_code |= IH264E_CONTENT_TYPE_NOT_SUPPORTED;
488 return (IV_FAIL);
489 }
490
491 if(ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X)
492 {
493 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
494 ps_op->s_ive_op.u4_error_code |= IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
495 return (IV_FAIL);
496 }
497
498 if(ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y)
499 {
500 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
501 ps_op->s_ive_op.u4_error_code |= IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
502 return (IV_FAIL);
503 }
504
505 if(ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE)
506 {
507 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
508 ps_op->s_ive_op.u4_error_code |= IH264E_SLICE_TYPE_INPUT_INVALID;
509 return (IV_FAIL);
510 }
511
512 if(NULL == ps_ip->s_ive_ip.ps_mem_rec)
513 {
514 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
515 ps_op->s_ive_op.u4_error_code |= IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
516 return (IV_FAIL);
517 }
518
519 /* verify number of mem records */
520 if(ps_ip->s_ive_ip.u4_num_mem_rec != ISVCE_MEM_REC_CNT)
521 {
522 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
523 ps_op->s_ive_op.u4_error_code |= IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
524 return (IV_FAIL);
525 }
526
527 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
528
529 /* check memrecords sizes are correct */
530 for(i = 0; i < ((WORD32) ps_ip->s_ive_ip.u4_num_mem_rec); i++)
531 {
532 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
533 {
534 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
535 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
536 return IV_FAIL;
537 }
538
539 /* check memrecords pointers are not NULL */
540 if(ps_mem_rec[i].pv_base == NULL)
541 {
542 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
543 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_BASE_POINTER_NULL;
544 return IV_FAIL;
545 }
546 }
547
548 /* verify memtabs for overlapping regions */
549 {
550 void *start[ISVCE_MEM_REC_CNT];
551 void *end[ISVCE_MEM_REC_CNT];
552
553 start[0] = (ps_mem_rec[0].pv_base);
554 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
555
556 for(i = 1; i < ISVCE_MEM_REC_CNT; i++)
557 {
558 /* This array is populated to check memtab overlap */
559 start[i] = (ps_mem_rec[i].pv_base);
560 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
561
562 for(j = 0; j < i; j++)
563 {
564 if((start[i] >= start[j]) && (start[i] <= end[j]))
565 {
566 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
567 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_OVERLAP_ERR;
568 return IV_FAIL;
569 }
570
571 if((end[i] >= start[j]) && (end[i] <= end[j]))
572 {
573 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
574 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_OVERLAP_ERR;
575 return IV_FAIL;
576 }
577
578 if((start[i] < start[j]) && (end[i] > end[j]))
579 {
580 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
581 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_OVERLAP_ERR;
582 return IV_FAIL;
583 }
584 }
585 }
586 }
587
588 /* re-validate mem records with init config */
589 {
590 /* mem records */
591 iv_mem_rec_t s_mem_rec_ittiam_api[ISVCE_MEM_REC_CNT];
592
593 /* api interface structs */
594 isvce_fill_mem_rec_ip_t s_ip;
595 isvce_fill_mem_rec_op_t s_op;
596
597 /* error status */
598 IV_STATUS_T e_status;
599
600 /* temp var */
601 WORD32 i;
602
603 isvce_api_cmds_t s_api_cmds = {ISVCE_CMD_FILL_NUM_MEM_REC, ISVCE_CMD_CT_NA};
604
605 s_ip.s_ive_ip.u4_size = sizeof(isvce_fill_mem_rec_ip_t);
606 s_op.s_ive_op.u4_size = sizeof(isvce_fill_mem_rec_op_t);
607
608 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api;
609 s_ip.s_ive_ip.u4_max_wd = max_wd;
610 s_ip.s_ive_ip.u4_max_ht = max_ht;
611 s_ip.u4_wd = wd;
612 s_ip.u4_ht = ht;
613 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
614 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level;
615 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
616 s_ip.s_ive_ip.u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
617 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt;
618 s_ip.s_ive_ip.u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
619 s_ip.s_ive_ip.u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
620
621 s_ip.s_svc_inp_params = ps_ip->s_svc_inp_params;
622
623 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
624 {
625 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
626 }
627
628 /* fill mem records */
629 e_status = isvce_api_function(NULL, (void *) &s_ip, (void *) &s_op, &s_api_cmds);
630
631 if(IV_FAIL == e_status)
632 {
633 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code;
634 return (IV_FAIL);
635 }
636
637 /* verify mem records */
638 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
639 {
640 if(ps_mem_rec[i].u4_mem_size < s_mem_rec_ittiam_api[i].u4_mem_size)
641 {
642 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
643 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_INSUFFICIENT_SIZE;
644
645 return IV_FAIL;
646 }
647
648 if(ps_mem_rec[i].u4_mem_alignment != s_mem_rec_ittiam_api[i].u4_mem_alignment)
649 {
650 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
651 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_ALIGNMENT_ERR;
652
653 return IV_FAIL;
654 }
655
656 if(ps_mem_rec[i].e_mem_type != s_mem_rec_ittiam_api[i].e_mem_type)
657 {
658 UWORD32 check = IV_SUCCESS;
659 UWORD32 diff =
660 s_mem_rec_ittiam_api[i].e_mem_type - ps_mem_rec[i].e_mem_type;
661
662 if((ps_mem_rec[i].e_mem_type <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM) &&
663 (s_mem_rec_ittiam_api[i].e_mem_type >=
664 IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
665 {
666 check = IV_FAIL;
667 }
668
669 if(3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4))
670 {
671 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or
672 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */
673
674 if((diff < 1) || (diff > 3))
675 {
676 /* Difference between 1 and 3 is okay for all cases other than
677 * the two filtered with the MOD condition above */
678 check = IV_FAIL;
679 }
680 }
681 else
682 {
683 if(diff == 1)
684 {
685 /* This particular case is when codec asked for External
686 * Persistent, but got Internal Scratch */
687 check = IV_FAIL;
688 }
689 if((diff != 2) && (diff != 3))
690 {
691 check = IV_FAIL;
692 }
693 }
694
695 if(check == IV_FAIL)
696 {
697 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
698 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_INCORRECT_TYPE;
699
700 return IV_FAIL;
701 }
702 }
703 }
704 }
705
706 break;
707 }
708 case ISVCE_CMD_RETRIEVE_MEMREC:
709 {
710 isvce_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
711 isvce_retrieve_mem_rec_op_t *ps_op = pv_api_op;
712
713 iv_mem_rec_t *ps_mem_rec = NULL;
714
715 ps_op->s_ive_op.u4_error_code = 0;
716
717 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_retrieve_mem_rec_ip_t))
718 {
719 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
720 ps_op->s_ive_op.u4_error_code |=
721 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
722 return (IV_FAIL);
723 }
724
725 if(ps_op->s_ive_op.u4_size != sizeof(isvce_retrieve_mem_rec_op_t))
726 {
727 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
728 ps_op->s_ive_op.u4_error_code |=
729 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
730 return (IV_FAIL);
731 }
732
733 if(NULL == ps_ip->s_ive_ip.ps_mem_rec)
734 {
735 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
736 ps_op->s_ive_op.u4_error_code |= IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
737 return (IV_FAIL);
738 }
739
740 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
741
742 /* check memrecords sizes are correct */
743 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
744 {
745 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
746 {
747 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
748 ps_op->s_ive_op.u4_error_code |= IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
749 return IV_FAIL;
750 }
751 }
752
753 break;
754 }
755 case ISVCE_CMD_VIDEO_ENCODE:
756 {
757 isvce_video_encode_ip_t *ps_ip = pv_api_ip;
758 isvce_video_encode_op_t *ps_op = pv_api_op;
759
760 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_video_encode_ip_t))
761 {
762 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
763 ps_op->s_ive_op.u4_error_code |= IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT;
764 return (IV_FAIL);
765 }
766
767 if(ps_op->s_ive_op.u4_size != sizeof(isvce_video_encode_op_t))
768 {
769 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
770 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
771 return (IV_FAIL);
772 }
773
774 break;
775 }
776 case ISVCE_CMD_VIDEO_CTL:
777 {
778 switch(e_ctl_cmd)
779 {
780 case ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS:
781 {
782 break;
783 }
784 case ISVCE_CMD_CTL_SETDEFAULT:
785 {
786 isvce_ctl_setdefault_ip_t *ps_ip = pv_api_ip;
787 isvce_ctl_setdefault_op_t *ps_op = pv_api_op;
788
789 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_setdefault_ip_t))
790 {
791 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
792 ps_op->s_ive_op.u4_error_code |=
793 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
794 return IV_FAIL;
795 }
796
797 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_setdefault_op_t))
798 {
799 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
800 ps_op->s_ive_op.u4_error_code |=
801 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
802 return IV_FAIL;
803 }
804
805 break;
806 }
807 case ISVCE_CMD_CTL_GETBUFINFO:
808 {
809 isvce_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
810 isvce_ctl_getbufinfo_op_t *ps_op = pv_api_op;
811
812 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_getbufinfo_ip_t))
813 {
814 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
815 ps_op->s_ive_op.u4_error_code |=
816 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
817 return IV_FAIL;
818 }
819
820 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_getbufinfo_op_t))
821 {
822 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
823 ps_op->s_ive_op.u4_error_code |=
824 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
825 return IV_FAIL;
826 }
827
828 if(ps_ip->s_ive_ip.u4_max_wd < MIN_WD)
829 {
830 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
831 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
832 return (IV_FAIL);
833 }
834
835 if(ps_ip->s_ive_ip.u4_max_ht < MIN_HT)
836 {
837 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
838 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
839 return (IV_FAIL);
840 }
841
842 if((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P) &&
843 (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE) &&
844 (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV) &&
845 (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
846 {
847 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
848 ps_op->s_ive_op.u4_error_code |= IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
849 return (IV_FAIL);
850 }
851
852 break;
853 }
854 case ISVCE_CMD_CTL_GETVERSION:
855 {
856 isvce_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
857 isvce_ctl_getversioninfo_op_t *ps_op = pv_api_op;
858
859 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_getversioninfo_ip_t))
860 {
861 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
862 ps_op->s_ive_op.u4_error_code |=
863 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
864 return IV_FAIL;
865 }
866
867 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_getversioninfo_op_t))
868 {
869 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
870 ps_op->s_ive_op.u4_error_code |=
871 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
872 return IV_FAIL;
873 }
874
875 if(ps_ip->s_ive_ip.pu1_version == NULL)
876 {
877 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
878 ps_op->s_ive_op.u4_error_code |= IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL;
879 return IV_FAIL;
880 }
881
882 break;
883 }
884 case ISVCE_CMD_CTL_FLUSH:
885 {
886 isvce_ctl_flush_ip_t *ps_ip = pv_api_ip;
887 isvce_ctl_flush_op_t *ps_op = pv_api_op;
888
889 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_flush_ip_t))
890 {
891 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
892 ps_op->s_ive_op.u4_error_code |=
893 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
894 return IV_FAIL;
895 }
896
897 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_flush_op_t))
898 {
899 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
900 ps_op->s_ive_op.u4_error_code |=
901 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
902 return IV_FAIL;
903 }
904
905 break;
906 }
907 case ISVCE_CMD_CTL_RESET:
908 {
909 isvce_ctl_reset_ip_t *ps_ip = pv_api_ip;
910 isvce_ctl_reset_op_t *ps_op = pv_api_op;
911
912 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_reset_ip_t))
913 {
914 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
915 ps_op->s_ive_op.u4_error_code |=
916 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
917 return IV_FAIL;
918 }
919
920 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_reset_op_t))
921 {
922 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
923 ps_op->s_ive_op.u4_error_code |=
924 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
925 return IV_FAIL;
926 }
927
928 break;
929 }
930 case ISVCE_CMD_CTL_SET_NUM_CORES:
931 {
932 isvce_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
933 isvce_ctl_set_num_cores_op_t *ps_op = pv_api_op;
934
935 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_num_cores_ip_t))
936 {
937 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
938 ps_op->s_ive_op.u4_error_code |=
939 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
940 return IV_FAIL;
941 }
942
943 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_num_cores_op_t))
944 {
945 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
946 ps_op->s_ive_op.u4_error_code |=
947 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
948 return IV_FAIL;
949 }
950
951 if((ps_ip->s_ive_ip.u4_num_cores < 1) ||
952 (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES))
953 {
954 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
955 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_NUM_CORES;
956 return IV_FAIL;
957 }
958
959 break;
960 }
961 case ISVCE_CMD_CTL_SET_DIMENSIONS:
962 {
963 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
964
965 isvce_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
966 isvce_ctl_set_dimensions_op_t *ps_op = pv_api_op;
967
968 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_dimensions_ip_t))
969 {
970 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
971 ps_op->s_ive_op.u4_error_code |=
972 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
973 return IV_FAIL;
974 }
975
976 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_dimensions_op_t))
977 {
978 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
979 ps_op->s_ive_op.u4_error_code |=
980 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
981 return IV_FAIL;
982 }
983
984 if(ps_ip->s_ive_ip.u4_wd < MIN_WD)
985 {
986 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
987 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
988 return (IV_FAIL);
989 }
990
991 if(ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd)
992 {
993 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
994 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
995 return (IV_FAIL);
996 }
997
998 if(ps_ip->s_ive_ip.u4_ht < MIN_HT)
999 {
1000 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1001 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
1002 return (IV_FAIL);
1003 }
1004
1005 if(ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht)
1006 {
1007 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1008 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
1009 return (IV_FAIL);
1010 }
1011
1012 if(ps_ip->s_ive_ip.u4_wd & 1)
1013 {
1014 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1015 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
1016 return (IV_FAIL);
1017 }
1018
1019 if(ps_ip->s_ive_ip.u4_ht & 1)
1020 {
1021 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1022 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
1023 return (IV_FAIL);
1024 }
1025
1026 break;
1027 }
1028 case ISVCE_CMD_CTL_SET_FRAMERATE:
1029 {
1030 isvce_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
1031 isvce_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
1032
1033 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_frame_rate_ip_t))
1034 {
1035 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1036 ps_op->s_ive_op.u4_error_code |=
1037 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1038 return IV_FAIL;
1039 }
1040
1041 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_frame_rate_op_t))
1042 {
1043 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1044 ps_op->s_ive_op.u4_error_code |=
1045 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1046 return IV_FAIL;
1047 }
1048
1049 if(((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE) ||
1050 ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE))
1051 {
1052 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1053 ps_op->s_ive_op.u4_error_code |= IH264E_FRAME_RATE_NOT_SUPPORTED;
1054 return (IV_FAIL);
1055 }
1056
1057 if((ps_ip->s_ive_ip.u4_src_frame_rate == 0) ||
1058 (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0))
1059 {
1060 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1061 ps_op->s_ive_op.u4_error_code |= IH264E_FRAME_RATE_NOT_SUPPORTED;
1062 return (IV_FAIL);
1063 }
1064
1065 if(ps_ip->s_ive_ip.u4_tgt_frame_rate > ps_ip->s_ive_ip.u4_src_frame_rate)
1066 {
1067 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1068 ps_op->s_ive_op.u4_error_code |=
1069 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE;
1070 return (IV_FAIL);
1071 }
1072
1073 break;
1074 }
1075 case ISVCE_CMD_CTL_SET_BITRATE:
1076 {
1077 isvce_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
1078 isvce_ctl_set_bitrate_op_t *ps_op = pv_api_op;
1079
1080 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1081
1082 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_bitrate_ip_t))
1083 {
1084 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1085 ps_op->s_ive_op.u4_error_code |=
1086 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1087 return IV_FAIL;
1088 }
1089
1090 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_bitrate_op_t))
1091 {
1092 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1093 ps_op->s_ive_op.u4_error_code |=
1094 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1095 return IV_FAIL;
1096 }
1097
1098 for(i = 0; i < ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers; i++)
1099 {
1100 if((ps_ip->pu4_target_bitrate[i] > DEFAULT_MAX_BITRATE) ||
1101 (ps_ip->pu4_target_bitrate[i] == 0))
1102 {
1103 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1104 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
1105 return (IV_FAIL);
1106 }
1107 }
1108
1109 break;
1110 }
1111 case ISVCE_CMD_CTL_SET_FRAMETYPE:
1112 {
1113 isvce_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
1114 isvce_ctl_set_frame_type_op_t *ps_op = pv_api_op;
1115
1116 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_frame_type_ip_t))
1117 {
1118 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1119 ps_op->s_ive_op.u4_error_code |=
1120 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1121 return IV_FAIL;
1122 }
1123
1124 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_frame_type_op_t))
1125 {
1126 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1127 ps_op->s_ive_op.u4_error_code |=
1128 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1129 return IV_FAIL;
1130 }
1131
1132 if((ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME) &&
1133 (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME) &&
1134 (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME))
1135 {
1136 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1137 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_FORCE_FRAME_INPUT;
1138 return IV_FAIL;
1139 }
1140
1141 break;
1142 }
1143 case ISVCE_CMD_CTL_SET_ME_PARAMS:
1144 {
1145 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1146
1147 isvce_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
1148 isvce_ctl_set_me_params_op_t *ps_op = pv_api_op;
1149
1150 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_me_params_ip_t))
1151 {
1152 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1153 ps_op->s_ive_op.u4_error_code |=
1154 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1155 return IV_FAIL;
1156 }
1157
1158 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_me_params_op_t))
1159 {
1160 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1161 ps_op->s_ive_op.u4_error_code |=
1162 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1163 return IV_FAIL;
1164 }
1165
1166 if(ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH)
1167 {
1168 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1169 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ME_SPEED_PRESET;
1170 return IV_FAIL;
1171 }
1172
1173 if((ps_ip->s_ive_ip.u4_enable_hpel != 0) &&
1174 (ps_ip->s_ive_ip.u4_enable_hpel != 1))
1175 {
1176 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1177 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_HALFPEL_OPTION;
1178 return IV_FAIL;
1179 }
1180
1181 if((ps_ip->s_ive_ip.u4_enable_qpel != 0) &&
1182 (ps_ip->s_ive_ip.u4_enable_qpel != 1))
1183 {
1184 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1185 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_QPEL_OPTION;
1186 return IV_FAIL;
1187 }
1188
1189 if((ps_ip->s_ive_ip.u4_enable_fast_sad != 0))
1190 {
1191 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1192 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_FAST_SAD_OPTION;
1193 return IV_FAIL;
1194 }
1195
1196 if(ps_ip->s_ive_ip.u4_enable_alt_ref > 0)
1197 {
1198 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1199 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ALT_REF_OPTION;
1200 return IV_FAIL;
1201 }
1202
1203 if(ps_ip->s_ive_ip.u4_srch_rng_x > ps_codec->s_cfg.u4_max_srch_rng_x)
1204 {
1205 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1206 ps_op->s_ive_op.u4_error_code |=
1207 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
1208 return (IV_FAIL);
1209 }
1210
1211 if(ps_ip->s_ive_ip.u4_srch_rng_y > ps_codec->s_cfg.u4_max_srch_rng_y)
1212 {
1213 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1214 ps_op->s_ive_op.u4_error_code |= IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
1215 return (IV_FAIL);
1216 }
1217
1218 break;
1219 }
1220 case ISVCE_CMD_CTL_SET_IPE_PARAMS:
1221 {
1222 isvce_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
1223 isvce_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
1224
1225 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_ipe_params_ip_t))
1226 {
1227 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1228 ps_op->s_ive_op.u4_error_code |=
1229 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1230 return IV_FAIL;
1231 }
1232
1233 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_ipe_params_op_t))
1234 {
1235 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1236 ps_op->s_ive_op.u4_error_code |=
1237 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1238 return IV_FAIL;
1239 }
1240
1241 if((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0) &&
1242 (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1))
1243 {
1244 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1245 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INTRA4x4_OPTION;
1246 return IV_FAIL;
1247 }
1248
1249 if((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG) &&
1250 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST) &&
1251 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL) &&
1252 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST) &&
1253 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED) &&
1254 (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST))
1255 {
1256 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1257 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ENC_SPEED_PRESET;
1258 return IV_FAIL;
1259 }
1260
1261 break;
1262 }
1263 case ISVCE_CMD_CTL_SET_GOP_PARAMS:
1264 {
1265 isvce_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
1266 isvce_ctl_set_gop_params_op_t *ps_op = pv_api_op;
1267
1268 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_gop_params_ip_t))
1269 {
1270 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1271 ps_op->s_ive_op.u4_error_code |=
1272 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1273 return IV_FAIL;
1274 }
1275
1276 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_gop_params_op_t))
1277 {
1278 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1279 ps_op->s_ive_op.u4_error_code |=
1280 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1281 return IV_FAIL;
1282 }
1283
1284 if((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) ||
1285 (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1286 {
1287 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1288 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INTRA_FRAME_INTERVAL;
1289 return IV_FAIL;
1290 }
1291
1292 if((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) ||
1293 (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1294 {
1295 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1296 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_IDR_FRAME_INTERVAL;
1297 return IV_FAIL;
1298 }
1299
1300 break;
1301 }
1302 case ISVCE_CMD_CTL_SET_DEBLOCK_PARAMS:
1303 {
1304 isvce_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
1305 isvce_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
1306
1307 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_deblock_params_ip_t))
1308 {
1309 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1310 ps_op->s_ive_op.u4_error_code |=
1311 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1312 return IV_FAIL;
1313 }
1314
1315 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_deblock_params_op_t))
1316 {
1317 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1318 ps_op->s_ive_op.u4_error_code |=
1319 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1320 return IV_FAIL;
1321 }
1322
1323 if((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0) &&
1324 (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2) &&
1325 (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3) &&
1326 (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4))
1327 {
1328 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1329 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_DEBLOCKING_TYPE_INPUT;
1330 return IV_FAIL;
1331 }
1332
1333 break;
1334 }
1335 case ISVCE_CMD_CTL_SET_QP:
1336 {
1337 isvce_ctl_set_qp_ip_t *ps_ip = pv_api_ip;
1338 isvce_ctl_set_qp_op_t *ps_op = pv_api_op;
1339
1340 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1341
1342 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_qp_ip_t))
1343 {
1344 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1345 ps_op->s_ive_op.u4_error_code |=
1346 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1347 return IV_FAIL;
1348 }
1349
1350 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_qp_op_t))
1351 {
1352 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1353 ps_op->s_ive_op.u4_error_code |=
1354 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1355 return IV_FAIL;
1356 }
1357
1358 for(i = 0; i < ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers; i++)
1359 {
1360 if((ps_ip->pu4_i_qp_max[i] > MAX_H264_QP) ||
1361 (ps_ip->pu4_p_qp_max[i] > MAX_H264_QP) ||
1362 (ps_ip->pu4_b_qp_max[i] > MAX_H264_QP))
1363 {
1364 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1365 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_MAX_FRAME_QP;
1366 return IV_FAIL;
1367 }
1368
1369 /* We donot support QP < 4 */
1370 if((((WORD32) ps_ip->pu4_i_qp_min[i]) < MIN_H264_QP) ||
1371 ((WORD32) ps_ip->pu4_p_qp_min[i] < MIN_H264_QP) ||
1372 (((WORD32) ps_ip->pu4_b_qp_min[i]) < MIN_H264_QP) ||
1373 (ps_ip->pu4_i_qp_min[i] > ps_ip->pu4_i_qp_max[i]) ||
1374 (ps_ip->pu4_p_qp_min[i] > ps_ip->pu4_p_qp_max[i]) ||
1375 (ps_ip->pu4_b_qp_min[i] > ps_ip->pu4_b_qp_max[i]))
1376 {
1377 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1378 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_MIN_FRAME_QP;
1379 return IV_FAIL;
1380 }
1381
1382 if((ps_ip->pu4_i_qp[i] > ps_ip->pu4_i_qp_max[i]) ||
1383 (ps_ip->pu4_p_qp[i] > ps_ip->pu4_p_qp_max[i]) ||
1384 (ps_ip->pu4_b_qp[i] > ps_ip->pu4_b_qp_max[i]))
1385 {
1386 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1387 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1388 return IV_FAIL;
1389 }
1390
1391 if((ps_ip->pu4_i_qp[i] < ps_ip->pu4_i_qp_min[i]) ||
1392 (ps_ip->pu4_p_qp[i] < ps_ip->pu4_p_qp_min[i]) ||
1393 (ps_ip->pu4_b_qp[i] < ps_ip->pu4_b_qp_min[i]))
1394 {
1395 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1396 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1397 return IV_FAIL;
1398 }
1399 }
1400
1401 break;
1402 }
1403 case ISVCE_CMD_CTL_SET_VUI_PARAMS:
1404 {
1405 isvce_vui_ip_t *ps_ip = pv_api_ip;
1406 isvce_vui_op_t *ps_op = pv_api_op;
1407
1408 if(ps_ip->u4_size != sizeof(isvce_vui_ip_t))
1409 {
1410 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1411 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1412 return IV_FAIL;
1413 }
1414
1415 if(ps_op->u4_size != sizeof(isvce_vui_op_t))
1416 {
1417 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1418 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1419 return IV_FAIL;
1420 }
1421
1422 break;
1423 }
1424 case ISVCE_CMD_CTL_SET_SEI_MDCV_PARAMS:
1425 {
1426 isvce_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
1427 isvce_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
1428
1429 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_mdcv_params_ip_t))
1430 {
1431 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1432 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1433 return IV_FAIL;
1434 }
1435
1436 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_mdcv_params_op_t))
1437 {
1438 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1439 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1440 return IV_FAIL;
1441 }
1442
1443 if((ps_ip->u1_sei_mdcv_params_present_flag != 0) &&
1444 (ps_ip->u1_sei_mdcv_params_present_flag) != 1)
1445 {
1446 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1447 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1448 return IV_FAIL;
1449 }
1450
1451 if(1 == ps_ip->u1_sei_mdcv_params_present_flag)
1452 {
1453 /* Check values for u2_display_primaries_x and
1454 * u2_display_primaries_y */
1455 for(i = 0; i < 3; i++)
1456 {
1457 if((ps_ip->au2_display_primaries_x[i] >
1458 DISPLAY_PRIMARIES_X_UPPER_LIMIT) ||
1459 (ps_ip->au2_display_primaries_x[i] <
1460 DISPLAY_PRIMARIES_X_LOWER_LIMIT) ||
1461 ((ps_ip->au2_display_primaries_x[i] %
1462 DISPLAY_PRIMARIES_X_DIVISION_FACTOR) != 0))
1463 {
1464 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1465 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1466 return IV_FAIL;
1467 }
1468
1469 if((ps_ip->au2_display_primaries_y[i] >
1470 DISPLAY_PRIMARIES_Y_UPPER_LIMIT) ||
1471 (ps_ip->au2_display_primaries_y[i] <
1472 DISPLAY_PRIMARIES_Y_LOWER_LIMIT) ||
1473 ((ps_ip->au2_display_primaries_y[i] %
1474 DISPLAY_PRIMARIES_Y_DIVISION_FACTOR) != 0))
1475 {
1476 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1477 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1478 return IV_FAIL;
1479 }
1480 }
1481
1482 if((ps_ip->u2_white_point_x > WHITE_POINT_X_UPPER_LIMIT) ||
1483 (ps_ip->u2_white_point_x < WHITE_POINT_X_LOWER_LIMIT) ||
1484 ((ps_ip->u2_white_point_x % WHITE_POINT_X_DIVISION_FACTOR) != 0))
1485 {
1486 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1487 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1488 return IV_FAIL;
1489 }
1490
1491 if((ps_ip->u2_white_point_y > WHITE_POINT_Y_UPPER_LIMIT) ||
1492 (ps_ip->u2_white_point_y < WHITE_POINT_Y_LOWER_LIMIT) ||
1493 ((ps_ip->u2_white_point_y % WHITE_POINT_Y_DIVISION_FACTOR) != 0))
1494 {
1495 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1496 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1497 return IV_FAIL;
1498 }
1499
1500 if((ps_ip->u4_max_display_mastering_luminance >
1501 MAX_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) ||
1502 (ps_ip->u4_max_display_mastering_luminance <
1503 MAX_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT) ||
1504 ((ps_ip->u4_max_display_mastering_luminance %
1505 MAX_DISPLAY_MASTERING_LUMINANCE_DIVISION_FACTOR) != 0))
1506 {
1507 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1508 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1509 return IV_FAIL;
1510 }
1511
1512 if((ps_ip->u4_min_display_mastering_luminance >
1513 MIN_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) ||
1514 (ps_ip->u4_min_display_mastering_luminance <
1515 MIN_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT))
1516 {
1517 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1518 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1519 return IV_FAIL;
1520 }
1521
1522 if(ps_ip->u4_max_display_mastering_luminance <=
1523 ps_ip->u4_min_display_mastering_luminance)
1524 {
1525 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1526 ps_op->u4_error_code |= IH264E_INVALID_SEI_MDCV_PARAMS;
1527 return IV_FAIL;
1528 }
1529 }
1530
1531 break;
1532 }
1533 case ISVCE_CMD_CTL_SET_SEI_CLL_PARAMS:
1534 {
1535 isvce_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
1536 isvce_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
1537
1538 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_cll_params_ip_t))
1539 {
1540 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1541 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1542 return IV_FAIL;
1543 }
1544
1545 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_cll_params_op_t))
1546 {
1547 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1548 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1549 return IV_FAIL;
1550 }
1551
1552 if((ps_ip->u1_sei_cll_params_present_flag != 0) &&
1553 (ps_ip->u1_sei_cll_params_present_flag != 1))
1554 {
1555 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1556 ps_op->u4_error_code |= IH264E_INVALID_SEI_CLL_PARAMS;
1557 return IV_FAIL;
1558 }
1559
1560 break;
1561 }
1562 case ISVCE_CMD_CTL_SET_SEI_AVE_PARAMS:
1563 {
1564 isvce_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
1565 isvce_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
1566
1567 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_ave_params_ip_t))
1568 {
1569 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1570 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1571 return IV_FAIL;
1572 }
1573
1574 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_ave_params_op_t))
1575 {
1576 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1577 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1578 return IV_FAIL;
1579 }
1580
1581 if((ps_ip->u1_sei_ave_params_present_flag != 0) &&
1582 (ps_ip->u1_sei_ave_params_present_flag != 1))
1583 {
1584 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1585 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1586 return IV_FAIL;
1587 }
1588
1589 if(1 == ps_ip->u1_sei_ave_params_present_flag)
1590 {
1591 if((0 == ps_ip->u4_ambient_illuminance))
1592 {
1593 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1594 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1595 return IV_FAIL;
1596 }
1597
1598 if(ps_ip->u2_ambient_light_x > AMBIENT_LIGHT_X_UPPER_LIMIT)
1599 {
1600 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1601 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1602 return IV_FAIL;
1603 }
1604
1605 if(ps_ip->u2_ambient_light_y > AMBIENT_LIGHT_Y_UPPER_LIMIT)
1606 {
1607 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1608 ps_op->u4_error_code |= IH264E_INVALID_SEI_AVE_PARAMS;
1609 return IV_FAIL;
1610 }
1611 }
1612
1613 break;
1614 }
1615 case ISVCE_CMD_CTL_SET_SEI_CCV_PARAMS:
1616 {
1617 isvce_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
1618 isvce_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
1619
1620 if(ps_ip->u4_size != sizeof(isvce_ctl_set_sei_ccv_params_ip_t))
1621 {
1622 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1623 ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1624 return IV_FAIL;
1625 }
1626
1627 if(ps_op->u4_size != sizeof(isvce_ctl_set_sei_ccv_params_op_t))
1628 {
1629 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1630 ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1631 return IV_FAIL;
1632 }
1633
1634 if((ps_ip->u1_sei_ccv_params_present_flag != 0) &&
1635 (ps_ip->u1_sei_ccv_params_present_flag != 1))
1636 {
1637 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1638 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1639 return IV_FAIL;
1640 }
1641
1642 if(1 == ps_ip->u1_sei_ccv_params_present_flag)
1643 {
1644 if((ps_ip->u1_ccv_cancel_flag != 0) && (ps_ip->u1_ccv_cancel_flag != 1))
1645 {
1646 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1647 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1648 return IV_FAIL;
1649 }
1650
1651 if(0 == ps_ip->u1_ccv_cancel_flag)
1652 {
1653 if((ps_ip->u1_ccv_persistence_flag != 0) &&
1654 (ps_ip->u1_ccv_persistence_flag != 1))
1655 {
1656 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1657 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1658 return IV_FAIL;
1659 }
1660 if((ps_ip->u1_ccv_primaries_present_flag != 0) &&
1661 (ps_ip->u1_ccv_primaries_present_flag != 1))
1662 {
1663 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1664 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1665 return IV_FAIL;
1666 }
1667 if((ps_ip->u1_ccv_min_luminance_value_present_flag != 0) &&
1668 (ps_ip->u1_ccv_min_luminance_value_present_flag != 1))
1669 {
1670 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1671 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1672 return IV_FAIL;
1673 }
1674 if((ps_ip->u1_ccv_max_luminance_value_present_flag != 0) &&
1675 (ps_ip->u1_ccv_max_luminance_value_present_flag != 1))
1676 {
1677 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1678 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1679 return IV_FAIL;
1680 }
1681 if((ps_ip->u1_ccv_avg_luminance_value_present_flag != 0) &&
1682 (ps_ip->u1_ccv_avg_luminance_value_present_flag != 1))
1683 {
1684 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1685 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1686 return IV_FAIL;
1687 }
1688 if((ps_ip->u1_ccv_primaries_present_flag == 0) &&
1689 (ps_ip->u1_ccv_min_luminance_value_present_flag == 0) &&
1690 (ps_ip->u1_ccv_max_luminance_value_present_flag == 0) &&
1691 (ps_ip->u1_ccv_avg_luminance_value_present_flag == 0))
1692 {
1693 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1694 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1695 return IV_FAIL;
1696 }
1697
1698 if((ps_ip->u1_ccv_reserved_zero_2bits != 0))
1699 {
1700 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1701 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1702 return IV_FAIL;
1703 }
1704
1705 if(1 == ps_ip->u1_ccv_primaries_present_flag)
1706 {
1707 for(i = 0; i < 3; i++)
1708 {
1709 if((ps_ip->ai4_ccv_primaries_x[i] >
1710 CCV_PRIMARIES_X_UPPER_LIMIT) ||
1711 (ps_ip->ai4_ccv_primaries_x[i] <
1712 CCV_PRIMARIES_X_LOWER_LIMIT))
1713 {
1714 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1715 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1716 return IV_FAIL;
1717 }
1718
1719 if((ps_ip->ai4_ccv_primaries_y[i] >
1720 CCV_PRIMARIES_Y_UPPER_LIMIT) ||
1721 (ps_ip->ai4_ccv_primaries_y[i] <
1722 CCV_PRIMARIES_Y_LOWER_LIMIT))
1723 {
1724 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1725 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1726 return IV_FAIL;
1727 }
1728 }
1729 }
1730
1731 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
1732 (1 == ps_ip->u1_ccv_avg_luminance_value_present_flag))
1733 {
1734 if((ps_ip->u4_ccv_avg_luminance_value <
1735 ps_ip->u4_ccv_min_luminance_value))
1736 {
1737 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1738 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1739 return IV_FAIL;
1740 }
1741 }
1742
1743 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
1744 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
1745 {
1746 if((ps_ip->u4_ccv_max_luminance_value <
1747 ps_ip->u4_ccv_min_luminance_value))
1748 {
1749 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1750 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1751 return IV_FAIL;
1752 }
1753 }
1754 if((1 == ps_ip->u1_ccv_avg_luminance_value_present_flag) &&
1755 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
1756 {
1757 if((ps_ip->u4_ccv_max_luminance_value <
1758 ps_ip->u4_ccv_avg_luminance_value))
1759 {
1760 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1761 ps_op->u4_error_code |= IH264E_INVALID_SEI_CCV_PARAMS;
1762 return IV_FAIL;
1763 }
1764 }
1765 }
1766 }
1767
1768 break;
1769 }
1770 case ISVCE_CMD_CTL_SET_ENC_MODE:
1771 {
1772 isvce_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
1773 isvce_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
1774
1775 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_enc_mode_ip_t))
1776 {
1777 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1778 ps_op->s_ive_op.u4_error_code |=
1779 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1780 return IV_FAIL;
1781 }
1782
1783 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_enc_mode_op_t))
1784 {
1785 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1786 ps_op->s_ive_op.u4_error_code |=
1787 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1788 return IV_FAIL;
1789 }
1790
1791 if((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER) &&
1792 (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE))
1793 {
1794 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1795 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ENC_OPERATION_MODE;
1796 return IV_FAIL;
1797 }
1798
1799 break;
1800 }
1801 case ISVCE_CMD_CTL_SET_VBV_PARAMS:
1802 {
1803 isvce_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
1804 isvce_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
1805
1806 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_handle->pv_codec_handle);
1807
1808 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_vbv_params_ip_t))
1809 {
1810 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1811 ps_op->s_ive_op.u4_error_code |=
1812 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1813 return IV_FAIL;
1814 }
1815
1816 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_vbv_params_op_t))
1817 {
1818 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1819 ps_op->s_ive_op.u4_error_code |=
1820 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1821 return IV_FAIL;
1822 }
1823
1824 for(i = 0; i < ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers; i++)
1825 {
1826 if((ps_ip->pu4_vbv_buffer_delay[i] < DEFAULT_MIN_BUFFER_DELAY) ||
1827 (ps_ip->pu4_vbv_buffer_delay[i] > DEFAULT_MAX_BUFFER_DELAY))
1828 {
1829 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1830 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_BUFFER_DELAY;
1831 return IV_FAIL;
1832 }
1833 }
1834
1835 break;
1836 }
1837 case ISVCE_CMD_CTL_SET_AIR_PARAMS:
1838 {
1839 isvce_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
1840 isvce_ctl_set_air_params_op_t *ps_op = pv_api_op;
1841
1842 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_air_params_ip_t))
1843 {
1844 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1845 ps_op->s_ive_op.u4_error_code |=
1846 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1847 return IV_FAIL;
1848 }
1849
1850 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_air_params_op_t))
1851 {
1852 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1853 ps_op->s_ive_op.u4_error_code |=
1854 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1855 return IV_FAIL;
1856 }
1857
1858 if((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE) &&
1859 (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC) &&
1860 (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM))
1861 {
1862 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1863 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_AIR_MODE;
1864 return IV_FAIL;
1865 }
1866
1867 if(ps_ip->s_ive_ip.u4_air_refresh_period == 0)
1868 {
1869 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1870 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_AIR_REFRESH_PERIOD;
1871 return IV_FAIL;
1872 }
1873
1874 break;
1875 }
1876 case ISVCE_CMD_CTL_SET_PROFILE_PARAMS:
1877 {
1878 isvce_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
1879 isvce_ctl_set_profile_params_op_t *ps_op = pv_api_op;
1880
1881 if(ps_ip->s_ive_ip.u4_size != sizeof(isvce_ctl_set_profile_params_ip_t))
1882 {
1883 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1884 ps_op->s_ive_op.u4_error_code |=
1885 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1886 return IV_FAIL;
1887 }
1888
1889 if(ps_op->s_ive_op.u4_size != sizeof(isvce_ctl_set_profile_params_op_t))
1890 {
1891 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1892 ps_op->s_ive_op.u4_error_code |=
1893 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1894 return IV_FAIL;
1895 }
1896
1897 if(ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE &&
1898 ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN)
1899 {
1900 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1901 ps_op->s_ive_op.u4_error_code |= IH264E_PROFILE_NOT_SUPPORTED;
1902 return IV_FAIL;
1903 }
1904
1905 if(ps_ip->s_ive_ip.u4_entropy_coding_mode > 1)
1906 {
1907 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1908 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_ENTROPY_CODING_MODE;
1909 return IV_FAIL;
1910 }
1911
1912 break;
1913 }
1914 default:
1915 {
1916 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1917 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD;
1918 return IV_FAIL;
1919 }
1920 }
1921
1922 break;
1923 }
1924 default:
1925 {
1926 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1927 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
1928 return IV_FAIL;
1929 }
1930 }
1931
1932 return IV_SUCCESS;
1933 }
1934
1935 /**
1936 *******************************************************************************
1937 *
1938 * @brief
1939 * Sets default encoder config parameters
1940 *
1941 * @par Description:
1942 * Sets default dynamic parameters. Will be called in isvce_init() to ensure
1943 * that even if set_params is not called, codec continues to work
1944 *
1945 * @param[in] ps_cfg
1946 * Pointer to encoder config params
1947 *
1948 * @returns error status
1949 *
1950 * @remarks none
1951 *
1952 *******************************************************************************
1953 */
isvce_set_default_params(isvce_cfg_params_t * ps_cfg)1954 static WORD32 isvce_set_default_params(isvce_cfg_params_t *ps_cfg)
1955 {
1956 WORD32 ret = IV_SUCCESS;
1957 WORD32 i;
1958
1959 ps_cfg->u4_max_wd = MAX_WD;
1960 ps_cfg->u4_max_ht = MAX_HT;
1961 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
1962 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
1963 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
1964 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV;
1965 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE;
1966 ps_cfg->e_recon_color_fmt = IV_YUV_420P;
1967 ps_cfg->u4_enc_speed_preset = IVE_FASTEST;
1968 ps_cfg->e_rc_mode = DEFAULT_RC;
1969 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE;
1970 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES;
1971 ps_cfg->e_content_type = IV_PROGRESSIVE;
1972 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X;
1973 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y;
1974 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE;
1975 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM;
1976 ps_cfg->e_arch = isvce_default_arch();
1977 ps_cfg->e_soc = SOC_GENERIC;
1978 ps_cfg->u4_disp_wd = MAX_WD;
1979 ps_cfg->u4_disp_ht = MAX_HT;
1980 ps_cfg->u4_wd = MAX_WD;
1981 ps_cfg->u4_ht = MAX_HT;
1982 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE;
1983 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE;
1984 ps_cfg->e_frame_type = IV_NA_FRAME;
1985 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT;
1986 ps_cfg->e_air_mode = DEFAULT_AIR_MODE;
1987 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD;
1988 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES;
1989 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET;
1990 ps_cfg->u4_enable_hpel = DEFAULT_HPEL;
1991 ps_cfg->u4_enable_qpel = DEFAULT_QPEL;
1992 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4;
1993 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8;
1994 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16;
1995 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD;
1996 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD;
1997 ps_cfg->i4_min_sad = (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD)
1998 ? DEFAULT_MIN_SAD_ENABLE
1999 : DEFAULT_MIN_SAD_DISABLE;
2000 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X;
2001 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y;
2002 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL;
2003 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL;
2004 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL;
2005 ps_cfg->e_profile = DEFAULT_PROFILE;
2006 ps_cfg->u4_timestamp_low = 0;
2007 ps_cfg->u4_timestamp_high = 0;
2008 ps_cfg->u4_is_valid = 1;
2009 ps_cfg->e_cmd = ISVCE_CMD_CT_NA;
2010 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
2011 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
2012 ps_cfg->u4_entropy_coding_mode = CAVLC;
2013 ps_cfg->u4_weighted_prediction = 0;
2014 ps_cfg->u4_pic_info_type = 0;
2015 ps_cfg->u4_isvce_mb_info_type = 0;
2016 ps_cfg->s_vui.u1_video_signal_type_present_flag = 1;
2017 ps_cfg->s_vui.u1_colour_description_present_flag = 1;
2018
2019 ps_cfg->b_nalu_info_export_enable = false;
2020
2021 for(i = 0; i < MAX_NUM_SPATIAL_LAYERS; i++)
2022 {
2023 ps_cfg->au4_i_qp_max[i] = MAX_H264_QP;
2024 ps_cfg->au4_i_qp_min[i] = MIN_H264_QP;
2025 ps_cfg->au4_i_qp[i] = DEFAULT_I_QP;
2026 ps_cfg->au4_p_qp_max[i] = MAX_H264_QP;
2027 ps_cfg->au4_p_qp_min[i] = MIN_H264_QP;
2028 ps_cfg->au4_p_qp[i] = DEFAULT_P_QP;
2029 ps_cfg->au4_b_qp_max[i] = MAX_H264_QP;
2030 ps_cfg->au4_b_qp_min[i] = MIN_H264_QP;
2031 ps_cfg->au4_b_qp[i] = DEFAULT_B_QP;
2032 }
2033
2034 ps_cfg->s_svc_params.d_spatial_res_ratio = 2.0;
2035 ps_cfg->s_svc_params.u1_num_spatial_layers = 1;
2036 ps_cfg->s_svc_params.u1_num_temporal_layers = 1;
2037
2038 return ret;
2039 }
2040
2041 /**
2042 *******************************************************************************
2043 *
2044 * @brief
2045 * Initialize encoder context. This will be called by init_mem_rec and during
2046 * codec reset
2047 *
2048 * @par Description:
2049 * Initializes the context
2050 *
2051 * @param[in] ps_codec
2052 * Codec context pointer
2053 *
2054 * @returns error status
2055 *
2056 * @remarks none
2057 *
2058 *******************************************************************************
2059 */
isvce_init(isvce_codec_t * ps_codec)2060 static WORD32 isvce_init(isvce_codec_t *ps_codec)
2061 {
2062 /* enc config param set */
2063 isvce_cfg_params_t *ps_cfg = &(ps_codec->s_cfg);
2064
2065 UWORD32 i;
2066
2067 /* coded pic count */
2068 ps_codec->i4_poc = 0;
2069
2070 /* Number of API calls to encode are made */
2071 ps_codec->i4_encode_api_call_cnt = -1;
2072
2073 /* Indicates no header has been generated yet */
2074 ps_codec->u4_header_generated = 0;
2075
2076 /* Number of pictures encoded */
2077 ps_codec->i4_pic_cnt = -1;
2078
2079 /* Number of threads created */
2080 ps_codec->i4_proc_thread_cnt = 0;
2081
2082 /* ctl mutex init */
2083 ithread_mutex_init(ps_codec->pv_ctl_mutex);
2084
2085 /* Set encoder chroma format */
2086 ps_codec->e_codec_color_format =
2087 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ? IV_YUV_420SP_VU : IV_YUV_420SP_UV;
2088
2089 /* Number of continuous frames where deblocking was disabled */
2090 ps_codec->u4_disable_deblock_level_cnt = 0;
2091
2092 /* frame num */
2093 ps_codec->i4_frame_num = 0;
2094
2095 /* set the current frame type to I frame, since we are going to start
2096 * encoding*/
2097 ps_codec->force_curr_frame_type = IV_NA_FRAME;
2098
2099 /* idr_pic_id */
2100 ps_codec->i4_idr_pic_id = -1;
2101
2102 /* Flush mode */
2103 ps_codec->i4_flush_mode = 0;
2104
2105 /* Encode header mode */
2106 ps_codec->i4_header_mode = 0;
2107
2108 /* Encode generate header */
2109 ps_codec->i4_gen_header = 0;
2110
2111 /* To signal successful completion of init */
2112 ps_codec->i4_init_done = 1;
2113
2114 /* To signal that at least one picture was decoded */
2115 ps_codec->i4_first_pic_done = 0;
2116
2117 /* Reset Codec */
2118 ps_codec->i4_reset_flag = 0;
2119
2120 /* Current error code */
2121 ps_codec->i4_error_code = IH264E_SUCCESS;
2122
2123 /* threshold residue */
2124 ps_codec->u4_thres_resi = 1;
2125
2126 /* inter gating enable */
2127 ps_codec->u4_inter_gate = 0;
2128
2129 /* entropy mutex init */
2130 ithread_mutex_init(ps_codec->pv_entropy_mutex);
2131
2132 /* Process thread created status */
2133 memset(ps_codec->ai4_process_thread_created, 0, sizeof(ps_codec->ai4_process_thread_created));
2134
2135 /* Number of MBs processed together */
2136 ps_codec->i4_proc_nmb = 8;
2137
2138 /* Previous POC msb */
2139 ps_codec->i4_prev_poc_msb = 0;
2140
2141 /* Previous POC lsb */
2142 ps_codec->i4_prev_poc_lsb = -1;
2143
2144 /* max Previous POC lsb */
2145 ps_codec->i4_max_prev_poc_lsb = -1;
2146
2147 /* sps, pps status */
2148 {
2149 sps_t *ps_sps = ps_codec->ps_sps_base;
2150 pps_t *ps_pps = ps_codec->ps_pps_base;
2151
2152 for(i = 0; i < MAX_SPS_CNT; i++)
2153 {
2154 ps_sps->i1_sps_valid = 0;
2155 ps_sps++;
2156 }
2157
2158 for(i = 0; i < MAX_PPS_CNT; i++)
2159 {
2160 ps_pps->i1_pps_valid = 0;
2161 ps_pps++;
2162 }
2163 }
2164
2165 {
2166 WORD32 max_mb_rows;
2167 UWORD32 u4_ht, u4_wd;
2168
2169 isvce_get_svc_compliant_dimensions(ps_cfg->s_svc_params.u1_num_spatial_layers,
2170 ps_cfg->s_svc_params.d_spatial_res_ratio, ps_cfg->u4_wd,
2171 ps_cfg->u4_ht, &u4_wd, &u4_ht);
2172
2173 /* frame dimensions */
2174 u4_ht = ALIGN16(u4_ht);
2175 max_mb_rows = u4_ht / MB_SIZE;
2176
2177 {
2178 WORD32 clz;
2179
2180 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
2181
2182 /* Use next power of two number of entries*/
2183 clz = CLZ(num_jobs);
2184 num_jobs = 1 << (32 - clz);
2185
2186 /* init process jobq */
2187 ps_codec->pv_proc_jobq =
2188 ih264_list_init(ps_codec->pv_proc_jobq_buf, ps_codec->i4_proc_jobq_buf_size,
2189 num_jobs, sizeof(job_t), 10);
2190 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
2191 ih264_list_reset(ps_codec->pv_proc_jobq);
2192
2193 /* init entropy jobq */
2194 ps_codec->pv_entropy_jobq =
2195 ih264_list_init(ps_codec->pv_entropy_jobq_buf, ps_codec->i4_entropy_jobq_buf_size,
2196 num_jobs, sizeof(job_t), 10);
2197 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL);
2198 ih264_list_reset(ps_codec->pv_entropy_jobq);
2199 }
2200 }
2201
2202 /* Update the jobq context to all the threads */
2203 for(i = 0; i < MAX_PROCESS_CTXT; i++)
2204 {
2205 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
2206 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq;
2207
2208 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */
2209 ps_codec->as_process[i].i4_id = i % MAX_PROCESS_THREADS;
2210 ps_codec->as_process[i].ps_codec = ps_codec;
2211
2212 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq;
2213 ps_codec->as_process[i].s_entropy.pv_entropy_jobq = ps_codec->pv_entropy_jobq;
2214 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1;
2215 }
2216
2217 /* Initialize MV Bank buffer manager */
2218 ps_codec->pv_svc_au_data_store_mgr =
2219 ih264_buf_mgr_init(ps_codec->pv_svc_au_data_store_mgr_base);
2220
2221 /* Initialize Picture buffer manager for reference buffers*/
2222 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_ref_buf_mgr_base);
2223
2224 /* Initialize Picture buffer manager for input buffers*/
2225 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_inp_buf_mgr_base);
2226
2227 /* Initialize buffer manager for output buffers*/
2228 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_out_buf_mgr_base);
2229
2230 /* buffer cnt in buffer manager */
2231 ps_codec->i4_inp_buf_cnt = 0;
2232 ps_codec->i4_out_buf_cnt = 0;
2233 ps_codec->i4_ref_buf_cnt = 0;
2234
2235 ps_codec->ps_pic_buf = ps_codec->ps_pic_buf_base;
2236 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(svc_au_buf_t));
2237
2238 for(i = 0; i < BUF_MGR_MAX_CNT; i++)
2239 {
2240 isvce_svc_au_buf_init(&((svc_au_buf_t *) ps_codec->ps_pic_buf)[i], &ps_cfg->s_svc_params);
2241 }
2242
2243 /* Initialize dpb manager */
2244 ih264_dpb_mgr_init((dpb_mgr_t *) ps_codec->pv_dpb_mgr);
2245
2246 memset(ps_codec->as_ref_set, 0, sizeof(ps_codec->as_ref_set));
2247 for(i = 0; i < (sizeof(ps_codec->as_ref_set) / sizeof(ps_codec->as_ref_set[0])); i++)
2248 {
2249 ps_codec->as_ref_set[i].i4_pic_cnt = -1;
2250 }
2251
2252 /* fn ptr init */
2253 isvce_init_function_ptr(ps_codec);
2254
2255 /* reset status flags */
2256 for(i = 0; i < MAX_CTXT_SETS; i++)
2257 {
2258 ps_codec->ae_entropy_thread_exit_state[i] = INACTIVE;
2259 ps_codec->ai4_pic_cnt[i] = -1;
2260
2261 ps_codec->s_rate_control.pre_encode_skip[i] = 0;
2262 ps_codec->s_rate_control.post_encode_skip[i] = 0;
2263 }
2264
2265 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
2266 {
2267 ps_codec->s_rate_control.ai4_num_intra_in_prev_frame[i] = 0;
2268 ps_codec->s_rate_control.ai4_avg_activity[i] = 0;
2269 }
2270
2271 ps_codec->i4_max_num_reference_frames =
2272 MIN((gas_ih264_lvl_tbl[ih264e_get_lvl_idx(ps_codec->s_cfg.u4_max_level)].u4_max_dpb_size /
2273 (ps_codec->s_cfg.i4_wd_mbs * ps_codec->s_cfg.i4_ht_mbs)),
2274 16);
2275
2276 return IV_SUCCESS;
2277 }
2278
2279 /**
2280 *******************************************************************************
2281 *
2282 * @brief
2283 * Gets number of memory records required by the codec
2284 *
2285 * @par Description:
2286 * Gets codec memory requirements
2287 *
2288 * @param[in] pv_api_ip
2289 * Pointer to input argument structure
2290 *
2291 * @param[out] pv_api_op
2292 * Pointer to output argument structure
2293 *
2294 * @returns status
2295 *
2296 * @remarks
2297 *
2298 *******************************************************************************
2299 */
isvce_get_num_rec(void * pv_api_ip,void * pv_api_op)2300 static WORD32 isvce_get_num_rec(void *pv_api_ip, void *pv_api_op)
2301 {
2302 /* api call I/O structures */
2303 isvce_num_mem_rec_op_t *ps_op = pv_api_op;
2304
2305 UNUSED(pv_api_ip);
2306
2307 ps_op->s_ive_op.u4_num_mem_rec = ISVCE_MEM_REC_CNT;
2308
2309 return IV_SUCCESS;
2310 }
2311
2312 /**
2313 *******************************************************************************
2314 *
2315 * @brief
2316 * Fills memory records of the codec
2317 *
2318 * @par Description:
2319 * Fills codec memory requirements
2320 *
2321 * @param[in] pv_api_ip
2322 * Pointer to input argument structure
2323 *
2324 * @param[out] pv_api_op
2325 * Pointer to output argument structure
2326 *
2327 * @returns error status
2328 *
2329 * @remarks none
2330 *
2331 *******************************************************************************
2332 */
isvce_fill_num_mem_rec(void * pv_api_ip,void * pv_api_op)2333 static WORD32 isvce_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
2334 {
2335 isvce_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
2336 isvce_fill_mem_rec_op_t *ps_op = pv_api_op;
2337
2338 WORD32 level;
2339 WORD32 num_reorder_frames;
2340 WORD32 num_ref_frames;
2341
2342 WORD32 no_of_mem_rec;
2343 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
2344
2345 WORD32 max_wd_luma, max_ht_luma;
2346 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
2347 UWORD32 u4_wd, u4_ht;
2348
2349 WORD32 i;
2350
2351 IV_STATUS_T status = IV_SUCCESS;
2352
2353 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt;
2354 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt;
2355
2356 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
2357 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
2358
2359 isvce_get_svc_compliant_dimensions(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
2360 ps_ip->s_svc_inp_params.d_spatial_res_ratio, ps_ip->u4_wd,
2361 ps_ip->u4_ht, &u4_wd, &u4_ht);
2362
2363 /* frame dimensions */
2364 max_ht_luma = ALIGN16(u4_ht);
2365 max_wd_luma = ALIGN16(u4_wd);
2366 max_mb_rows = max_ht_luma / MB_SIZE;
2367 max_mb_cols = max_wd_luma / MB_SIZE;
2368 max_mb_cnt = max_mb_rows * max_mb_cols;
2369
2370 /* profile / level info */
2371 level = ih264e_get_min_level(max_ht_luma, max_wd_luma);
2372
2373 /* Validate params */
2374 ps_op->s_ive_op.u4_error_code |= isvce_svc_au_props_validate(
2375 &ps_ip->s_svc_inp_params, ps_ip->u4_wd, ps_ip->u4_ht, u4_wd, u4_ht);
2376
2377 if(ps_op->s_ive_op.u4_error_code != IV_SUCCESS)
2378 {
2379 return IV_FAIL;
2380 }
2381
2382 if((level < MIN_LEVEL) || (level > MAX_LEVEL))
2383 {
2384 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
2385 level = MAX_LEVEL;
2386 }
2387
2388 if(num_ref_frames > MAX_REF_CNT)
2389 {
2390 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
2391 num_ref_frames = MAX_REF_CNT;
2392 }
2393
2394 if(num_reorder_frames > MAX_REF_CNT)
2395 {
2396 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
2397 num_reorder_frames = MAX_REF_CNT;
2398 }
2399
2400 /* Set all memory records as persistent and alignment as 128 by default */
2401 ps_mem_rec = ps_mem_rec_base;
2402 for(i = 0; i < no_of_mem_rec; i++)
2403 {
2404 ps_mem_rec->u4_mem_alignment = 128;
2405 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2406 ps_mem_rec++;
2407 }
2408
2409 /************************************************************************
2410 * Request memory for h264 encoder handle *
2411 ***********************************************************************/
2412 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_IV_OBJ];
2413 {
2414 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
2415 }
2416 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size);
2417
2418 /************************************************************************
2419 * Request memory for h264 encoder context *
2420 ***********************************************************************/
2421 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CODEC];
2422 {
2423 ps_mem_rec->u4_mem_size = sizeof(isvce_codec_t);
2424 }
2425 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CODEC, ps_mem_rec->u4_mem_size);
2426
2427 /************************************************************************
2428 * Request memory for CABAC context *
2429 ***********************************************************************/
2430 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC];
2431 {
2432 ps_mem_rec->u4_mem_size = sizeof(isvce_cabac_ctxt_t);
2433 }
2434 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CABAC, ps_mem_rec->u4_mem_size);
2435
2436 /************************************************************************
2437 * Request memory for CABAC MB info *
2438 ***********************************************************************/
2439 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC_MB_INFO];
2440 {
2441 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1) * sizeof(isvce_mb_info_ctxt_t);
2442 }
2443 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size);
2444
2445 /************************************************************************
2446 * Request memory for entropy context *
2447 * In multi core encoding, each row is assumed to be launched on a *
2448 * thread. The rows below can only start after its neighbors are coded *
2449 * The status of an mb coded/uncoded is signaled via entropy map. *
2450 * 1. One word32 to store skip run cnt *
2451 * 2. mb entropy map (mb status entropy coded/uncoded). The size*
2452 * of the entropy map is max mb cols. Further allocate one *
2453 * more additional row to evade checking for row -1. *
2454 * 3. size of bit stream buffer to store bit stream ctxt. *
2455 * 4. Entropy coding is dependent on nnz coefficient count for *
2456 * the neighbor blocks. It is sufficient to maintain one row *
2457 * worth of nnz as entropy for lower row waits on entropy map*
2458 ************************************************************************/
2459 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY];
2460 {
2461 /* total size of the mem record */
2462 WORD32 total_size = 0;
2463
2464 /* size of skip mb run */
2465 total_size += sizeof(WORD32);
2466 total_size = ALIGN8(total_size);
2467
2468 /* size in bytes to store entropy status of an entire frame */
2469 total_size += (max_mb_cols * max_mb_rows);
2470 /* add an additional 1 row of bytes to evade the special case of row 0 */
2471 total_size += max_mb_cols;
2472 total_size = ALIGN128(total_size);
2473
2474 /* size of bit stream buffer */
2475 total_size += sizeof(bitstrm_t);
2476 total_size = ALIGN128(total_size);
2477
2478 #if ENABLE_RE_ENC_AS_SKIP
2479 total_size += sizeof(bitstrm_t);
2480 total_size = ALIGN128(total_size);
2481 #endif
2482
2483 /* top nnz luma */
2484 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2485 total_size = ALIGN128(total_size);
2486
2487 /* top nnz cbcr */
2488 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2489 total_size = ALIGN128(total_size);
2490
2491 /* ps_mb_qp_ctxt */
2492 total_size += ALIGN128(sizeof(mb_qp_ctxt_t));
2493
2494 /* total size per each proc ctxt */
2495 total_size *= MAX_CTXT_SETS;
2496
2497 ps_mem_rec->u4_mem_size = total_size;
2498 }
2499 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size);
2500
2501 /************************************************************************
2502 * The residue coefficients that needs to be entropy coded are packed *
2503 * at a buffer space by the proc threads. The entropy thread shall *
2504 * read from the buffer space, unpack them and encode the same. The *
2505 * buffer space required to pack a row of mbs are as follows. *
2506 * Assuming transform_8x8_flag is disabled, *
2507 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed *
2508 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed *
2509 * by 8 ac 4x4 chroma sub blocks. *
2510 * For the sake of simplicity we assume that all sub blocks are of *
2511 * type 4x4. The packing of each 4x4 is depicted by the structure *
2512 * tu_sblk_coeff_data_t *
2513 ************************************************************************/
2514 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_COEFF_DATA];
2515 {
2516 /* temp var */
2517 WORD32 size = 0;
2518
2519 /* size of coeff data of 1 mb */
2520 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
2521
2522 /* size of coeff data of 1 row of mb's */
2523 size *= max_mb_cols;
2524
2525 /* align to avoid any false sharing across threads */
2526 size = ALIGN64(size);
2527
2528 /* size for one full frame */
2529 size *= max_mb_rows;
2530
2531 /* size of each proc buffer set (ping, pong) */
2532 size *= MAX_CTXT_SETS;
2533
2534 ps_mem_rec->u4_mem_size = size;
2535 }
2536 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size);
2537
2538 /************************************************************************
2539 * while encoding an mb, the mb header data is signaled to the entropy*
2540 * thread by writing to a buffer space. the size of header data per mb *
2541 * is assumed to be 40 bytes *
2542 * TODO: revisit this inference *
2543 ************************************************************************/
2544 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_HEADER_DATA];
2545 {
2546 /* temp var */
2547 WORD32 size;
2548
2549 /* size per MB */
2550 size = sizeof(isvce_mb_hdr_t);
2551
2552 /* size for 1 row of mbs */
2553 size = size * max_mb_cols;
2554
2555 /* align to avoid any false sharing across threads */
2556 size = ALIGN64(size);
2557
2558 /* size for one full frame */
2559 size *= max_mb_rows;
2560
2561 /* size of each proc buffer set (ping, pong) */
2562 size *= MAX_CTXT_SETS;
2563
2564 ps_mem_rec->u4_mem_size = size;
2565 }
2566 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size);
2567
2568 /************************************************************************
2569 * While encoding inter slices, to compute the cost of encoding an mb *
2570 * with the mv's at hand, we employ the expression cost = sad + lambda *
2571 * x mv_bits. Here mv_bits is the total number of bits taken to represe*
2572 * nt the mv in the stream. The mv bits for all the possible mv are *
2573 * stored in the look up table. The mem record for this look up table *
2574 * is given below. *
2575 ************************************************************************/
2576 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBITS];
2577 {
2578 /* max srch range x */
2579 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
2580
2581 /* max srch range y */
2582 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
2583
2584 /* max srch range */
2585 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
2586
2587 /* due to subpel */
2588 u4_max_srch_range <<= 2;
2589
2590 /* due to mv on either direction */
2591 u4_max_srch_range = (u4_max_srch_range << 1);
2592
2593 /* due to pred mv + zero */
2594 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
2595
2596 u4_max_srch_range = ALIGN128(u4_max_srch_range);
2597
2598 ps_mem_rec->u4_mem_size = u4_max_srch_range;
2599 }
2600 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MVBITS, ps_mem_rec->u4_mem_size);
2601
2602 /************************************************************************
2603 * Request memory for SPS *
2604 ***********************************************************************/
2605 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SPS];
2606 {
2607 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
2608 }
2609 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SPS, ps_mem_rec->u4_mem_size);
2610
2611 /************************************************************************
2612 * Request memory for PPS *
2613 ***********************************************************************/
2614 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PPS];
2615 {
2616 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
2617 }
2618 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PPS, ps_mem_rec->u4_mem_size);
2619
2620 /************************************************************************
2621 * Request memory for SVC NALU Extension *
2622 ************************************************************************/
2623 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_NALU_EXT];
2624 {
2625 /* 2 implies allocation for NAL_PREFIX and NAL_CODED_SLICE_EXTENSION */
2626 ps_mem_rec->u4_mem_size =
2627 2 * MAX_CTXT_SETS * SVC_MAX_SLICE_HDR_CNT * sizeof(svc_nalu_ext_t);
2628 }
2629 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SVC_NALU_EXT, ps_mem_rec->u4_mem_size);
2630
2631 /************************************************************************
2632 * Request memory for subset SPS *
2633 ************************************************************************/
2634 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SUBSET_SPS];
2635 {
2636 ps_mem_rec->u4_mem_size =
2637 MAX_SPS_CNT * ps_ip->s_svc_inp_params.u1_num_spatial_layers * sizeof(subset_sps_t);
2638 }
2639 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SUBSET_SPS, ps_mem_rec->u4_mem_size);
2640
2641 /************************************************************************
2642 * Request memory for Slice Header *
2643 ***********************************************************************/
2644 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_HDR];
2645 {
2646 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * SVC_MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
2647 }
2648 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size);
2649
2650 /************************************************************************
2651 * Request memory for SVC Slice Header *
2652 ***********************************************************************/
2653 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_SLICE_HDR];
2654 {
2655 ps_mem_rec->u4_mem_size =
2656 MAX_CTXT_SETS * SVC_MAX_SLICE_HDR_CNT * sizeof(svc_slice_header_t);
2657 }
2658 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SVC_SLICE_HDR, ps_mem_rec->u4_mem_size);
2659
2660 /************************************************************************
2661 * Request memory for Adaptive Intra Refresh *
2662 ***********************************************************************/
2663 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_AIR_MAP];
2664 {
2665 /* total size of the mem record */
2666 WORD32 total_size = 0;
2667
2668 /* intra coded map */
2669 total_size += max_mb_cnt;
2670 total_size *= MAX_CTXT_SETS;
2671
2672 /* mb refresh map */
2673 total_size += sizeof(UWORD16) * max_mb_cnt;
2674
2675 /* alignment */
2676 total_size = ALIGN128(total_size);
2677
2678 ps_mem_rec->u4_mem_size = total_size;
2679 }
2680 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size);
2681
2682 /************************************************************************
2683 * In multi slice encoding, this memory record helps tracking the start*
2684 * of slice with reference to mb. *
2685 * MEM RECORD for holding *
2686 * 1. mb slice map *
2687 ************************************************************************/
2688 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_MAP];
2689 {
2690 /* total size of the mem record */
2691 WORD32 total_size = 0;
2692
2693 /* size in bytes to slice index of all mbs of a frame */
2694 total_size = ALIGN64(max_mb_cnt);
2695
2696 /* isvce_update_proc_ctxt can overread by 1 at the end */
2697 total_size += 1;
2698
2699 /* total size per each proc ctxt */
2700 total_size *= MAX_CTXT_SETS;
2701 ps_mem_rec->u4_mem_size = total_size;
2702 }
2703 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size);
2704
2705 /************************************************************************
2706 * Request memory to hold thread handles for each processing thread *
2707 ************************************************************************/
2708 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_THREAD_HANDLE];
2709 {
2710 WORD32 handle_size = ithread_get_handle_size();
2711
2712 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size;
2713 }
2714 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size);
2715
2716 /************************************************************************
2717 * Request memory to hold mutex for control calls *
2718 ************************************************************************/
2719 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CTL_MUTEX];
2720 {
2721 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
2722 }
2723 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size);
2724
2725 /************************************************************************
2726 * Request memory to hold mutex for entropy calls *
2727 ************************************************************************/
2728 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_MUTEX];
2729 {
2730 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
2731 }
2732 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size);
2733
2734 /************************************************************************
2735 * Request memory to hold process jobs *
2736 ***********************************************************************/
2737 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_JOBQ];
2738 {
2739 /* One process job per row of MBs */
2740 /* Allocate for two pictures, so that wrap around can be handled easily */
2741 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
2742
2743 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
2744
2745 ps_mem_rec->u4_mem_size = job_queue_size;
2746 }
2747 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size);
2748
2749 /************************************************************************
2750 * Request memory to hold entropy jobs *
2751 ***********************************************************************/
2752 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_JOBQ];
2753 {
2754 /* One process job per row of MBs */
2755 /* Allocate for two pictures, so that wrap around can be handled easily */
2756 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
2757
2758 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
2759
2760 ps_mem_rec->u4_mem_size = job_queue_size;
2761 }
2762 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size);
2763
2764 /************************************************************************
2765 * In multi core encoding, each row is assumed to be launched on a *
2766 * thread. The rows below can only start after its neighbors are coded *
2767 * The status of an mb coded/uncoded is signaled via proc map. *
2768 * MEM RECORD for holding *
2769 * 1. mb proc map (mb status core coded/uncoded) *
2770 ************************************************************************/
2771 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_MAP];
2772 {
2773 /* total size of the mem record */
2774 WORD32 total_size = 0;
2775
2776 /* size in bytes to mb core coding status of an entire frame */
2777 total_size = max_mb_cnt;
2778
2779 /* add an additional 1 row of bytes to evade the special case of row 0 */
2780 total_size += max_mb_cols;
2781
2782 /* total size per each proc ctxt */
2783 total_size *= MAX_CTXT_SETS;
2784 ps_mem_rec->u4_mem_size = total_size;
2785 }
2786 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size);
2787
2788 /************************************************************************
2789 * mem record for holding a particular MB is deblocked or not *
2790 * 1. mb deblk map (mb status deblocked/not deblocked) *
2791 ************************************************************************/
2792 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DBLK_MAP];
2793 {
2794 /* total size of the mem record */
2795 WORD32 total_size = 0;
2796
2797 /* size in bytes to mb core coding status of an entire frame */
2798 total_size = max_mb_cnt;
2799
2800 /* add an additional 1 row of bytes to evade the special case of row 0 */
2801 total_size += max_mb_cols;
2802
2803 total_size = ALIGN64(total_size);
2804
2805 /* total size per each proc ctxt */
2806 total_size *= MAX_CTXT_SETS;
2807 ps_mem_rec->u4_mem_size = total_size;
2808 }
2809 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size);
2810
2811 /************************************************************************
2812 * mem record for holding a particular MB's me is done or not *
2813 * 1. mb me map *
2814 ************************************************************************/
2815 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ME_MAP];
2816 {
2817 /* total size of the mem record */
2818 WORD32 total_size = 0;
2819
2820 /* size in bytes to mb core coding status of an entire frame */
2821 total_size = max_mb_cnt;
2822
2823 /* add an additional 1 row of bytes to evade the special case of row 0 */
2824 total_size += max_mb_cols;
2825
2826 /* total size per each proc ctxt */
2827 total_size *= MAX_CTXT_SETS;
2828
2829 ps_mem_rec->u4_mem_size = total_size;
2830 }
2831 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size);
2832
2833 /************************************************************************
2834 * size for holding dpb manager context *
2835 ************************************************************************/
2836 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DPB_MGR];
2837 {
2838 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
2839 }
2840 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size);
2841
2842 /************************************************************************
2843 * luma or chroma core coding involves mb estimation, error computation*
2844 * between the estimated singnal and the actual signal, transform the *
2845 * error, quantize the error, then inverse transform and inverse quant *
2846 * ize the residue and add the result back to estimated signal. *
2847 * To perform all these, a set of temporary buffers are needed. *
2848 * MEM RECORD for holding scratch buffers *
2849 * 1. prediction buffer used during mb mode analysis *
2850 * 2 temp. reference buffer when intra 4x4 with rdopt on is *
2851 * enabled *
2852 * - when intra 4x4 is enabled, rdopt is on, to store the *
2853 * reconstructed values and use them later this temp. buffer *
2854 * is used. *
2855 * 3. prediction buffer used during intra mode analysis *
2856 * 4. prediction buffer used during intra 16x16 plane mode *
2857 * analysis
2858 * 5. prediction buffer used during intra chroma mode analysis *
2859 * 6. prediction buffer used during intra chroma 16x16 plane *
2860 * mode analysis
2861 * 7. forward transform output buffer *
2862 * - to store the error between estimated and the actual inp *
2863 * ut and to store the fwd transformed quantized output *
2864 * 8. forward transform output buffer *
2865 * - when intra 4x4 is enabled, rdopt is on, to store the *
2866 * fwd transform values and use them later this temp. buffer *
2867 * is used. *
2868 * 9. temporary buffer for inverse transform *
2869 * - temporary buffer used in inverse transform and inverse *
2870 * quantization *
2871 * A. Buffers for holding half_x , half_y and half_xy planes *
2872 ************************************************************************/
2873 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_SCRATCH];
2874 {
2875 WORD32 total_size = 0;
2876 WORD32 i4_tmp_size;
2877
2878 /* size to hold prediction buffer */
2879 total_size += sizeof(UWORD8) * 16 * 16;
2880 total_size = ALIGN64(total_size);
2881
2882 /* size to hold recon for intra 4x4 buffer */
2883 total_size += sizeof(UWORD8) * 16 * 16;
2884 total_size = ALIGN64(total_size);
2885
2886 /* prediction buffer intra 16x16 */
2887 total_size += sizeof(UWORD8) * 16 * 16;
2888 total_size = ALIGN64(total_size);
2889
2890 /* prediction buffer intra 16x16 plane*/
2891 total_size += sizeof(UWORD8) * 16 * 16;
2892 total_size = ALIGN64(total_size);
2893
2894 /* prediction buffer intra chroma*/
2895 total_size += sizeof(UWORD8) * 16 * 8;
2896 total_size = ALIGN64(total_size);
2897
2898 /* prediction buffer intra chroma plane*/
2899 total_size += sizeof(UWORD8) * 16 * 8;
2900 total_size = ALIGN64(total_size);
2901
2902 /* size to hold fwd transform output */
2903 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
2904 total_size = ALIGN64(total_size);
2905
2906 /* size to hold fwd transform output */
2907 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
2908 total_size = ALIGN64(total_size);
2909
2910 /* size to hold temporary data during inverse transform */
2911 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
2912 total_size = ALIGN64(total_size);
2913
2914 /* Buffers for holding half_x , half_y and half_xy planes */
2915 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
2916 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT);
2917
2918 /* Allocate for each process thread */
2919 total_size *= MAX_PROCESS_CTXT;
2920
2921 ps_mem_rec->u4_mem_size = total_size;
2922 }
2923 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size);
2924
2925 /************************************************************************
2926 * When transform_8x8_flag is disabled, the size of a sub block is *
2927 * 4x4 and when the transform_8x8_flag is enabled the size of the sub *
2928 * block is 8x8. The threshold matrix and the forward scaling list *
2929 * is of the size of the sub block. *
2930 * MEM RECORD for holding *
2931 * 1. quantization parameters for plane y, cb, cr *
2932 * - threshold matrix for quantization *
2933 * - forward weight matrix *
2934 * - satqd threshold matrix *
2935 ************************************************************************/
2936 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_QUANT_PARAM];
2937 {
2938 /* total size of the mem record */
2939 WORD32 total_size = 0;
2940
2941 /* quantization parameter list for planes y,cb and cr */
2942 total_size += ALIGN64(sizeof(quant_params_t)) * 3;
2943
2944 /* size of threshold matrix for quantization
2945 * (assuming the transform_8x8_flag is disabled).
2946 * for all 3 planes */
2947 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
2948
2949 /* size of forward weight matrix for quantization
2950 * (assuming the transform_8x8_flag is disabled).
2951 * for all 3 planes */
2952 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
2953
2954 /* Size for SATDQ threshold matrix for palnes y, cb and cr */
2955 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3;
2956
2957 total_size = ALIGN128(total_size);
2958
2959 /* total size per each proc thread */
2960 total_size *= MAX_PROCESS_CTXT;
2961
2962 ps_mem_rec->u4_mem_size = total_size;
2963 }
2964 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size);
2965
2966 /************************************************************************
2967 * While computing blocking strength for the current mb, the csbp, mb *
2968 * type for the neighboring mbs are necessary. memtab for storing top *
2969 * row mbtype and csbp is evaluated here. *
2970 * *
2971 * when encoding intra 4x4 or intra 8x8 the submb types are estimated *
2972 * and sent. The estimation is dependent on neighbor mbs. For this *
2973 * store the top row sub mb types for intra mbs *
2974 * *
2975 * During motion vector prediction, the curr mb mv is predicted from *
2976 * neigbors left, top, top right and sometimes top left depending on *
2977 * the availability. The top and top right content is accessed from *
2978 * the memtab specified below. *
2979 ************************************************************************/
2980 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_TOP_ROW_SYN_INFO];
2981 {
2982 UWORD32 total_size = isvce_get_svc_nbr_info_buf_size(
2983 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
2984 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
2985
2986 total_size = ALIGN128(total_size);
2987 ps_mem_rec->u4_mem_size = total_size;
2988 }
2989 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size);
2990
2991 /************************************************************************
2992 * When transform_8x8_flag is disabled, the mb is partitioned into *
2993 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 *
2994 * vertical inner edge, 1 horizontal top edge and 1 horizontal *
2995 * inner edge per mb. Further, When transform_8x8_flag is enabled, *
2996 * the mb is partitioned in to 16 sub blocks. This corresponds to *
2997 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top *
2998 * edge and 3 horizontal inner edges per mb. *
2999 * MEM RECORD for holding *
3000 * 1. vertical edge blocking strength *
3001 * 2. horizontal edge blocking strength *
3002 * 3. mb qp *
3003 * all are frame level *
3004 ************************************************************************/
3005 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BS_QP];
3006 {
3007 /* total size of the mem record */
3008 WORD32 total_size = 0;
3009
3010 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of
3011 * every mb*/
3012 WORD32 vert_bs_size, horz_bs_size, qp_size;
3013
3014 /* vertical edge bs = total number of vertical edges * number of bytes per
3015 * each edge */
3016 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3017 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
3018 * bs */
3019 vert_bs_size = 2 * ALIGN64(max_mb_cnt * 4 * 4);
3020
3021 /* horizontal edge bs = total number of horizontal edges * number of bytes
3022 * per each edge */
3023 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3024 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
3025 * bs */
3026 horz_bs_size = 2 * ALIGN64(max_mb_cnt * 4 * 4);
3027
3028 /* qp of each mb requires 1 byte */
3029 qp_size = ALIGN64(max_mb_cnt);
3030
3031 /* total size */
3032 total_size = vert_bs_size + horz_bs_size + qp_size;
3033
3034 /* total size per each proc ctxt */
3035 total_size *= MAX_CTXT_SETS;
3036
3037 ps_mem_rec->u4_mem_size = total_size;
3038 }
3039 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_BS_QP, ps_mem_rec->u4_mem_size);
3040
3041 /************************************************************************
3042 * size for holding input pic buf *
3043 ************************************************************************/
3044 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_INP_PIC];
3045 {
3046 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3047 }
3048 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size);
3049
3050 /************************************************************************
3051 * size for holding putput pic buf *
3052 ************************************************************************/
3053 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_OUT];
3054 {
3055 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3056 }
3057 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_OUT, ps_mem_rec->u4_mem_size);
3058
3059 /************************************************************************
3060 * Size for color space conversion *
3061 ************************************************************************/
3062 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CSC];
3063 {
3064 /* We need a total a memory for a single frame of 420 sp, ie
3065 * (wd * ht) for luma and (wd * ht / 2) for chroma*/
3066 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * ((3 * max_ht_luma * max_wd_luma) >> 1);
3067 /* Allocate an extra row, since inverse transform functions for
3068 * chroma access(only read, not used) few extra bytes due to
3069 * interleaved input
3070 */
3071 ps_mem_rec->u4_mem_size += max_wd_luma;
3072 }
3073 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_CSC, ps_mem_rec->u4_mem_size);
3074
3075 /************************************************************************
3076 * Size for holding pic_buf_t for each reference picture *
3077 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3078 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3079 * max_dpb_size will be based on max_wd and max_ht *
3080 * For higher max_wd and max_ht this number will be smaller than *
3081 * MAX_DPB_SIZE But during actual initialization number of buffers *
3082 * allocated can be more. *
3083 * *
3084 * Also to handle display depth application can allocate more than *
3085 * what codec asks for in case of non-shared mode *
3086 * Since this is only a structure allocation and not actual buffer *
3087 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3088 ************************************************************************/
3089 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_REF_PIC];
3090 {
3091 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3092 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(svc_au_buf_t);
3093
3094 /************************************************************************
3095 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3096 * is set to maximum number of luma samples allowed at the given level. *
3097 * This is done to ensure that any stream with width and height lesser *
3098 * than max_wd and max_ht is supported. Number of buffers required can *
3099 * be greater for lower width and heights at a given level and this *
3100 * increased number of buffers might require more memory than what *
3101 * max_wd and max_ht buffer would have required. Number of buffers is *
3102 * doubled in order to return one frame at a time instead of sending *
3103 * multiple outputs during dpb full case. Also note one extra buffer is *
3104 * allocted to store current picture. *
3105 * *
3106 * Half-pel planes for each reference buffer are allocated along with *
3107 * the reference buffer. So each reference buffer is 4 times the *
3108 * required size. This way buffer management for the half-pel planes is *
3109 * easier and while using the half-pel planes in MC, an offset can be *
3110 * used from a single pointer *
3111 ***********************************************************************/
3112 ps_mem_rec->u4_mem_size +=
3113 HPEL_PLANES_CNT * isvce_get_total_svc_au_buf_size(&ps_ip->s_svc_inp_params,
3114 u4_wd * u4_ht, level, PAD_WD, PAD_HT,
3115 num_ref_frames, num_reorder_frames);
3116 }
3117 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size);
3118
3119 /************************************************************************
3120 * Size for holding svc_au_data_t for each MV Bank. *
3121 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3122 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3123 * max_dpb_size will be based on max_wd and max_ht *
3124 * For higher max_wd and max_ht this number will be smaller than *
3125 * MAX_DPB_SIZE But during actual initialization number of buffers *
3126 * allocated can be more. *
3127 * *
3128 * One extra MV Bank is needed to hold current pics MV bank. *
3129 * Since this is only a structure allocation and not actual buffer *
3130 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3131 ************************************************************************/
3132 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBANK];
3133 {
3134 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3135
3136 /************************************************************************
3137 * Allocate for pu_map, isvce_enc_pu_t and pic_pu_idx for each MV bank *
3138 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3139 * is set to maximum number of luma samples allowed at the given level. *
3140 * This is done to ensure that any stream with width and height lesser *
3141 * than max_wd and max_ht is supported. Number of buffers required can *
3142 * be greater for lower width and heights at a given level and this *
3143 * increased number of buffers might require more memory than what *
3144 * max_wd and max_ht buffer would have required Also note one extra *
3145 * buffer is allocated to store current pictures MV bank. *
3146 ***********************************************************************/
3147
3148 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(svc_au_data_t);
3149
3150 ps_mem_rec->u4_mem_size +=
3151 (num_ref_frames + num_reorder_frames + ps_ip->s_svc_inp_params.u1_num_temporal_layers +
3152 MAX_CTXT_SETS) *
3153 isvce_get_total_svc_au_data_size(u4_wd * u4_ht,
3154 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3155 ps_ip->s_svc_inp_params.d_spatial_res_ratio);
3156 }
3157 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MVBANK, ps_mem_rec->u4_mem_size);
3158
3159 /************************************************************************
3160 * Request memory to hold mem recs to be returned during retrieve call *
3161 ************************************************************************/
3162 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BACKUP];
3163 {
3164 ps_mem_rec->u4_mem_size = ISVCE_MEM_REC_CNT * sizeof(iv_mem_rec_t);
3165 }
3166 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_BACKUP, ps_mem_rec->u4_mem_size);
3167
3168 /************************************************************************
3169 * size for memory required by NMB info structs and buffer for storing *
3170 * half pel plane *
3171 ************************************************************************/
3172 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_INFO_NMB];
3173 {
3174 /* Additional 4 bytes to allow use of '_mm_loadl_epi64' */
3175 ps_mem_rec->u4_mem_size =
3176 MAX_PROCESS_CTXT * max_mb_cols *
3177 (sizeof(isvce_mb_info_nmb_t) + (MB_SIZE * MB_SIZE + 4) * sizeof(UWORD8));
3178 }
3179 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size);
3180
3181 /* Buffers for storing SVC Spatial data */
3182 {
3183 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_SPAT_INP];
3184
3185 ps_mem_rec->u4_mem_size =
3186 isvce_get_svc_inp_buf_size(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3187 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3188
3189 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_SPAT_INP, ps_mem_rec->u4_mem_size);
3190 }
3191
3192 /* Buffer for storing Downscaler data */
3193 {
3194 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_DOWN_SCALER];
3195
3196 ps_mem_rec->u4_mem_size = isvce_get_downscaler_data_size(
3197 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3198 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3199
3200 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_DOWN_SCALER, ps_mem_rec->u4_mem_size);
3201 }
3202
3203 {
3204 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_DATA];
3205
3206 ps_mem_rec->u4_mem_size =
3207 isvce_get_svc_ilp_buf_size(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3208 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3209
3210 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_ILP_DATA, ps_mem_rec->u4_mem_size);
3211 }
3212
3213 {
3214 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_MV_CTXT];
3215
3216 ps_mem_rec->u4_mem_size =
3217 isvce_get_ilp_mv_ctxt_size(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3218 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3219
3220 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_ILP_MV_CTXT, ps_mem_rec->u4_mem_size);
3221 }
3222
3223 {
3224 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_RES_PRED_CTXT];
3225
3226 ps_mem_rec->u4_mem_size = isvce_get_svc_res_pred_ctxt_size(
3227 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3228 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3229
3230 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_RES_PRED_CTXT,
3231 ps_mem_rec->u4_mem_size);
3232 }
3233
3234 {
3235 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_INTRA_PRED_CTXT];
3236
3237 ps_mem_rec->u4_mem_size = isvce_get_svc_intra_pred_ctxt_size(
3238 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3239 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3240
3241 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_INTRA_PRED_CTXT,
3242 ps_mem_rec->u4_mem_size);
3243 }
3244
3245 {
3246 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_RC_UTILS_CTXT];
3247
3248 ps_mem_rec->u4_mem_size = isvce_get_rc_utils_data_size();
3249
3250 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_RC_UTILS_CTXT,
3251 ps_mem_rec->u4_mem_size);
3252 }
3253
3254 {
3255 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_SVC_SUB_PIC_RC_CTXT];
3256
3257 ps_mem_rec->u4_mem_size = isvce_get_sub_pic_rc_ctxt_size(
3258 ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3259 ps_ip->s_svc_inp_params.d_spatial_res_ratio, u4_wd, u4_ht);
3260
3261 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_SVC_SUB_PIC_RC_CTXT,
3262 ps_mem_rec->u4_mem_size);
3263 }
3264
3265 #if ENABLE_MODE_STAT_VISUALISER
3266 {
3267 ps_mem_rec = &ps_mem_rec_base[MEM_MODE_STAT_VISUALISER_BUF];
3268
3269 ps_mem_rec->u4_mem_size = isvce_get_msv_ctxt_size(u4_wd, u4_ht);
3270
3271 DEBUG("\nMemory record Id %d = %d \n", MEM_MODE_STAT_VISUALISER_BUF,
3272 ps_mem_rec->u4_mem_size);
3273 }
3274 #endif
3275
3276 /************************************************************************
3277 * RC mem records *
3278 ************************************************************************/
3279 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_RC];
3280 {
3281 isvce_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB);
3282 }
3283 DEBUG("\nMemory record Id %d = %d \n", ISVCE_MEM_REC_RC, ps_mem_rec->u4_mem_size);
3284
3285 /* Each memtab size is aligned to next multiple of 128 bytes */
3286 /* This is to ensure all the memtabs start at different cache lines */
3287 ps_mem_rec = ps_mem_rec_base;
3288 for(i = 0; i < ISVCE_MEM_REC_CNT; i++)
3289 {
3290 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
3291 ps_mem_rec++;
3292 }
3293
3294 ps_op->s_ive_op.u4_num_mem_rec = ISVCE_MEM_REC_CNT;
3295
3296 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec);
3297
3298 return (status);
3299 }
3300
3301 /**
3302 *******************************************************************************
3303 *
3304 * @brief
3305 * Initializes from mem records passed to the codec
3306 *
3307 * @par Description:
3308 * Initializes pointers based on mem records passed
3309 *
3310 * @param[in] ps_codec_obj
3311 * Pointer to codec object at API level
3312 *
3313 * @param[in] pv_api_ip
3314 * Pointer to input argument structure
3315 *
3316 * @param[out] pv_api_op
3317 * Pointer to output argument structure
3318 *
3319 * @returns error status
3320 *
3321 * @remarks none
3322 *
3323 *******************************************************************************
3324 */
isvce_init_mem_rec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)3325 static WORD32 isvce_init_mem_rec(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
3326 {
3327 /* api call I/O structures */
3328 isvce_init_ip_t *ps_ip = pv_api_ip;
3329 isvce_init_op_t *ps_op = pv_api_op;
3330
3331 /* mem records */
3332 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
3333
3334 /* codec variables */
3335 isvce_codec_t *ps_codec;
3336 isvce_cabac_ctxt_t *ps_cabac;
3337 isvce_mb_info_ctxt_t *ps_mb_map_ctxt_inc;
3338
3339 isvce_cfg_params_t *ps_cfg;
3340
3341 /* frame dimensions */
3342 WORD32 max_wd_luma, max_ht_luma;
3343 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
3344
3345 WORD32 i, j;
3346 WORD32 status = IV_SUCCESS;
3347
3348 if(MAX_CTXT_SETS != 1)
3349 {
3350 return IV_FAIL;
3351 }
3352
3353 /* mem records */
3354 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
3355
3356 /* memset all allocated memory, except the first one. First buffer (i.e. i == MEM_REC_IV_OBJ)
3357 is initialized by application before calling this init function */
3358 for(i = ISVCE_MEM_REC_CODEC; i < ISVCE_MEM_REC_CNT; i++)
3359 {
3360 ps_mem_rec = &ps_mem_rec_base[i];
3361 memset(ps_mem_rec->pv_base, 0, ps_mem_rec->u4_mem_size);
3362 }
3363
3364 /* Init mem records */
3365 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CODEC];
3366 {
3367 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
3368 ps_codec = (isvce_codec_t *) (ps_codec_obj->pv_codec_handle);
3369 }
3370 /* Init mem records_cabac ctxt */
3371 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC];
3372 {
3373 ps_cabac = (isvce_cabac_ctxt_t *) (ps_mem_rec->pv_base);
3374 }
3375
3376 /* Init mem records mb info array for CABAC */
3377 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CABAC_MB_INFO];
3378 {
3379 ps_mb_map_ctxt_inc = (isvce_mb_info_ctxt_t *) (ps_mem_rec->pv_base);
3380 }
3381
3382 /* Note this memset can not be done in init() call, since init will called
3383 during reset as well. And calling this during reset will mean all pointers
3384 need to reinitialized */
3385 memset(ps_codec, 0, sizeof(isvce_codec_t));
3386 memset(ps_cabac, 0, sizeof(isvce_cabac_ctxt_t));
3387
3388 /* Set default Config Params */
3389 ps_cfg = &ps_codec->s_cfg;
3390 isvce_set_default_params(ps_cfg);
3391
3392 /* get new input dimensions that satisfy the SVC and libavc constraints
3393 constraint 1) All layers of SVC should have dimensions that are a multiple of
3394 16 constraint 2) Dimension of Li layer = dimension of Li-1 layer * scaling
3395 factor*/
3396
3397 isvce_get_svc_compliant_dimensions(ps_ip->s_svc_inp_params.u1_num_spatial_layers,
3398 ps_ip->s_svc_inp_params.d_spatial_res_ratio, ps_ip->u4_wd,
3399 ps_ip->u4_ht, &ps_cfg->u4_wd, &ps_cfg->u4_ht);
3400
3401 /* Update config params as per input */
3402 ps_cfg->u4_max_wd = ps_cfg->u4_disp_wd = ALIGN16(ps_cfg->u4_wd);
3403 ps_cfg->u4_max_ht = ps_cfg->u4_disp_ht = ALIGN16(ps_cfg->u4_ht);
3404 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
3405 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
3406 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
3407 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
3408 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level;
3409 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt;
3410 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt;
3411 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate;
3412 for(i = 0; i < ps_ip->s_svc_inp_params.u1_num_spatial_layers; i++)
3413 {
3414 ps_cfg->au4_max_bitrate[i] = ps_ip->pu4_max_bitrate[i];
3415 }
3416 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes;
3417 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type;
3418 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3419 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3420 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode;
3421 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param;
3422 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch;
3423 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc;
3424 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon;
3425 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode;
3426 ps_cfg->u4_disable_vui = ps_ip->b_use_default_vui;
3427
3428 ps_cfg->s_svc_params.u1_num_temporal_layers = ps_ip->s_svc_inp_params.u1_num_temporal_layers;
3429
3430 ps_cfg->s_svc_params.u1_num_spatial_layers = ps_ip->s_svc_inp_params.u1_num_spatial_layers;
3431
3432 ps_cfg->s_svc_params.d_spatial_res_ratio = ps_ip->s_svc_inp_params.d_spatial_res_ratio;
3433
3434 ps_cfg->b_nalu_info_export_enable = ps_ip->b_nalu_info_export_enable;
3435
3436 /* frame dimensions */
3437 max_ht_luma = ALIGN16(ps_cfg->u4_ht);
3438 max_wd_luma = ALIGN16(ps_cfg->u4_wd);
3439 max_mb_rows = max_ht_luma / MB_SIZE;
3440 max_mb_cols = max_wd_luma / MB_SIZE;
3441 max_mb_cnt = max_mb_rows * max_mb_cols;
3442
3443 /* Validate params */
3444 ps_op->s_ive_op.u4_error_code |= isvce_svc_inp_params_validate(ps_ip, ps_cfg);
3445
3446 if(ps_op->s_ive_op.u4_error_code != IV_SUCCESS)
3447 {
3448 return IV_FAIL;
3449 }
3450
3451 #if defined(X86)
3452 if((ps_cfg->e_arch != ARCH_X86_GENERIC) && (ps_cfg->e_arch != ARCH_X86_SSSE3) &&
3453 (ps_cfg->e_arch != ARCH_X86_SSE42))
3454 {
3455 ps_cfg->e_arch = ARCH_X86_SSE42;
3456 }
3457 #else
3458 if((ps_cfg->e_arch == ARCH_X86_GENERIC) || (ps_cfg->e_arch == ARCH_X86_SSSE3) ||
3459 (ps_cfg->e_arch == ARCH_X86_SSE42))
3460 {
3461 #if defined(DISABLE_NEON)
3462 ps_cfg->e_arch = ARCH_ARM_NONEON;
3463 #elif defined(ARMV8)
3464 ps_cfg->e_arch = ARCH_ARM_V8_NEON;
3465 #else
3466 ps_cfg->e_arch = ARCH_ARM_A7;
3467 #endif
3468 }
3469 #endif
3470
3471 if((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL) || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL))
3472 {
3473 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
3474 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
3475 }
3476
3477 if(ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT)
3478 {
3479 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
3480 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
3481 }
3482
3483 if(ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT)
3484 {
3485 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
3486 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
3487 }
3488
3489 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BACKUP];
3490 {
3491 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base;
3492
3493 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
3494 ISVCE_MEM_REC_CNT * sizeof(iv_mem_rec_t));
3495 }
3496
3497 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY];
3498 {
3499 /* temp var */
3500 WORD32 size = 0;
3501
3502 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3503 {
3504 /* base ptr */
3505 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3506
3507 /* reset size */
3508 size = 0;
3509
3510 /* skip mb run */
3511 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run = (WORD32 *) (pu1_buf + size);
3512 size += sizeof(WORD32);
3513 size = ALIGN8(size);
3514
3515 /* entropy map */
3516 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
3517 (UWORD8 *) (pu1_buf + size + max_mb_cols);
3518 /* size in bytes to store entropy status of an entire frame */
3519 size += (max_mb_cols * max_mb_rows);
3520 /* add an additional 1 row of bytes to evade the special case of row 0
3521 */
3522 size += max_mb_cols;
3523 size = ALIGN128(size);
3524
3525 /* bit stream ptr */
3526 ps_codec->as_process[i].s_entropy.ps_bitstrm = (bitstrm_t *) (pu1_buf + size);
3527 size += sizeof(ps_codec->as_process[i].s_entropy.ps_bitstrm[0]);
3528 size = ALIGN128(size);
3529
3530 #if ENABLE_RE_ENC_AS_SKIP
3531 ps_codec->as_process[i].s_entropy.ps_bitstrm_after_slice_hdr =
3532 (bitstrm_t *) (pu1_buf + size);
3533 size += sizeof(ps_codec->as_process[i].s_entropy.ps_bitstrm_after_slice_hdr[0]);
3534 size = ALIGN128(size);
3535 #endif
3536
3537 /* nnz luma */
3538 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma = (UWORD8(*)[4])(pu1_buf + size);
3539 size += (max_mb_cols * 4 * sizeof(UWORD8));
3540 size = ALIGN128(size);
3541
3542 /* nnz chroma */
3543 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr = (UWORD8(*)[4])(pu1_buf + size);
3544 size += (max_mb_cols * 4 * sizeof(UWORD8));
3545 size = ALIGN128(size);
3546
3547 /* ps_mb_qp_ctxt */
3548 ps_codec->as_process[i].s_entropy.ps_mb_qp_ctxt = (mb_qp_ctxt_t *) (pu1_buf + size);
3549 size += ALIGN128(sizeof(ps_codec->as_process[i].s_entropy.ps_mb_qp_ctxt[0]));
3550
3551 /* cabac Context */
3552 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
3553 }
3554 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base = ps_mb_map_ctxt_inc;
3555 }
3556
3557 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_COEFF_DATA];
3558 {
3559 /* temp var */
3560 WORD32 size = 0, size_of_row;
3561 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3562
3563 /* size of coeff data of 1 mb */
3564 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
3565
3566 /* size of coeff data of 1 row of mb's */
3567 size *= max_mb_cols;
3568
3569 /* align to avoid false sharing */
3570 size = ALIGN64(size);
3571 size_of_row = size;
3572
3573 /* size for one full frame */
3574 size *= max_mb_rows;
3575
3576 ps_codec->u4_size_coeff_data = size_of_row;
3577
3578 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3579 {
3580 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf;
3581 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf;
3582 }
3583 }
3584
3585 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_HEADER_DATA];
3586 {
3587 /* temp var */
3588 WORD32 size, size_of_row;
3589 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3590
3591 /* size of header data of 1 mb */
3592 size = sizeof(isvce_mb_hdr_t);
3593
3594 /* size for 1 row of mbs */
3595 size = size * max_mb_cols;
3596
3597 /* align to avoid any false sharing across threads */
3598 size = ALIGN64(size);
3599 size_of_row = size;
3600
3601 /* size for one full frame */
3602 size *= max_mb_rows;
3603
3604 ps_codec->u4_size_header_data = size_of_row;
3605
3606 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3607 {
3608 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf;
3609 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data = pu1_buf;
3610 }
3611 }
3612
3613 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBITS];
3614 {
3615 /* max srch range x */
3616 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3617
3618 /* max srch range y */
3619 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3620
3621 /* max srch range */
3622 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3623
3624 /* temp var */
3625 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3626
3627 /* due to subpel */
3628 u4_max_srch_range <<= 2;
3629
3630 // /* due to mv on either direction */
3631 // u4_max_srch_range = (u4_max_srch_range << 1);
3632
3633 /* due to pred mv + zero */
3634 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3635
3636 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3637 {
3638 /* me ctxt */
3639 isvce_me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt);
3640
3641 /* init at zero mv */
3642 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range;
3643 }
3644 }
3645
3646 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SPS];
3647 {
3648 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base;
3649 }
3650
3651 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PPS];
3652 {
3653 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base;
3654 }
3655
3656 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_NALU_EXT];
3657 {
3658 ps_codec->ps_svc_nalu_ext_base = ps_mem_rec->pv_base;
3659
3660 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3661 {
3662 ps_codec->as_process[i].ps_svc_nalu_ext_base = ps_mem_rec->pv_base;
3663 }
3664 }
3665
3666 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SUBSET_SPS];
3667 {
3668 ps_codec->ps_subset_sps_base = ps_mem_rec->pv_base;
3669 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3670 {
3671 ps_codec->as_process[i].ps_subset_sps_base = ps_mem_rec->pv_base;
3672 }
3673 }
3674 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_HDR];
3675 {
3676 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base;
3677
3678 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3679 {
3680 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base;
3681 }
3682 }
3683
3684 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SVC_SLICE_HDR];
3685 {
3686 ps_codec->ps_svc_slice_hdr_base = ps_mem_rec->pv_base;
3687
3688 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3689 {
3690 ps_codec->as_process[i].ps_svc_slice_hdr_base = ps_mem_rec->pv_base;
3691 }
3692 }
3693
3694 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_AIR_MAP];
3695 {
3696 /* temp var */
3697 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3698
3699 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3700 {
3701 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf;
3702 }
3703
3704 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * MAX_CTXT_SETS);
3705 }
3706
3707 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_SLICE_MAP];
3708 {
3709 /* pointer to storage space */
3710 UWORD8 *pu1_buf_ping;
3711
3712 /* init pointer */
3713 pu1_buf_ping = ps_mem_rec->pv_base;
3714
3715 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3716 {
3717 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping;
3718 }
3719 }
3720
3721 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_THREAD_HANDLE];
3722 {
3723 WORD32 handle_size = ithread_get_handle_size();
3724
3725 for(i = 0; i < MAX_PROCESS_THREADS; i++)
3726 {
3727 ps_codec->apv_proc_thread_handle[i] =
3728 (UWORD8 *) ps_mem_rec->pv_base + (i * handle_size);
3729 }
3730 }
3731
3732 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CTL_MUTEX];
3733 {
3734 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base;
3735 }
3736
3737 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_MUTEX];
3738 {
3739 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base;
3740 }
3741
3742 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_JOBQ];
3743 {
3744 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
3745 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
3746 }
3747
3748 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ENTROPY_JOBQ];
3749 {
3750 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base;
3751 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size;
3752 }
3753
3754 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_MAP];
3755 {
3756 /* pointer to storage space */
3757 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3758
3759 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3760 {
3761 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols;
3762 }
3763 }
3764
3765 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DBLK_MAP];
3766 {
3767 /* pointer to storage space */
3768 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3769
3770 /* total size of the mem record */
3771 WORD32 total_size = 0;
3772
3773 /* size in bytes to mb core coding status of an entire frame */
3774 total_size = max_mb_cnt;
3775
3776 /* add an additional 1 row of bytes to evade the special case of row 0 */
3777 total_size += max_mb_cols;
3778
3779 /*Align the memory offsets*/
3780 total_size = ALIGN64(total_size);
3781
3782 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3783 {
3784 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols;
3785 }
3786 }
3787
3788 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_ME_MAP];
3789 {
3790 /* pointer to storage space */
3791 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
3792
3793 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3794 {
3795 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols;
3796 }
3797 }
3798
3799 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_DPB_MGR];
3800 {
3801 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
3802 }
3803
3804 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_PROC_SCRATCH];
3805 {
3806 /* pointer to storage space */
3807 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
3808
3809 /* size of pred buffer, fwd transform output, temp buffer for inv tra */
3810 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp;
3811
3812 /* temp var */
3813 WORD32 size = 0;
3814
3815 /* size to hold intra/inter prediction buffer */
3816 size_pred_luma = sizeof(UWORD8) * 16 * 16;
3817 size_pred_chroma = sizeof(UWORD8) * 8 * 16;
3818
3819 /* size to hold fwd transform output */
3820 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF;
3821
3822 /* size to hold temporary data during inverse transform */
3823 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
3824
3825 /* size to hold half pel plane buffers */
3826 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
3827
3828 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3829 {
3830 /* prediction buffer */
3831 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size);
3832 ps_codec->as_process[i].i4_pred_strd = 16;
3833 size += size_pred_luma;
3834 size = ALIGN64(size);
3835
3836 /* prediction buffer */
3837 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf + size);
3838 size += size_pred_luma;
3839 size = ALIGN64(size);
3840
3841 /* prediction buffer intra 16x16 */
3842 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf + size);
3843 size += size_pred_luma;
3844 size = ALIGN64(size);
3845
3846 /* prediction buffer intra 16x16 plane*/
3847 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane = (void *) (pu1_buf + size);
3848 size += size_pred_luma;
3849 size = ALIGN64(size);
3850
3851 /* prediction buffer intra chroma*/
3852 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf + size);
3853 size += size_pred_chroma;
3854 size = ALIGN64(size);
3855
3856 /* prediction buffer intra chroma plane*/
3857 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane = (void *) (pu1_buf + size);
3858 size += size_pred_chroma;
3859 size = ALIGN64(size);
3860
3861 /* Fwd transform output */
3862 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size);
3863 ps_codec->as_process[i].i4_res_strd = 16;
3864 size += size_fwd;
3865 size = ALIGN64(size);
3866
3867 /* Fwd transform output */
3868 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf + size);
3869 size += size_fwd;
3870 size = ALIGN64(size);
3871
3872 /* scratch buffer used during inverse transform */
3873 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size);
3874 size += size_inv;
3875 size = ALIGN64(size);
3876
3877 for(j = 0; j < SUBPEL_BUFF_CNT; j++)
3878 {
3879 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size);
3880 size += ALIGN64(size_hp);
3881 }
3882 }
3883 }
3884
3885 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_QUANT_PARAM];
3886 {
3887 /* pointer to storage space */
3888 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
3889
3890 /* size of qp, threshold matrix, fwd scaling list for one plane */
3891 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat, size_satqd_weight_mat;
3892
3893 /* temp var */
3894 WORD32 total_size = 0;
3895
3896 /* size of quantization parameter list of 1 plane */
3897 size_quant_param = ALIGN64(sizeof(quant_params_t));
3898
3899 /* size of threshold matrix for quantization
3900 * (assuming the transform_8x8_flag is disabled).
3901 * for 1 plane */
3902 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
3903
3904 /* size of forward weight matrix for quantization
3905 * (assuming the transform_8x8_flag is disabled).
3906 * for 1 plane */
3907 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
3908
3909 /* size of SATQD matrix*/
3910 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9);
3911
3912 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3913 {
3914 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params;
3915
3916 /* quantization param structure */
3917 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size);
3918 total_size = total_size + size_quant_param;
3919 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size);
3920 total_size = total_size + size_quant_param;
3921 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size);
3922 total_size = total_size + size_quant_param;
3923
3924 /* threshold matrix for quantization */
3925 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size);
3926 total_size = total_size + size_thres_mat;
3927 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size);
3928 total_size = total_size + size_thres_mat;
3929 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size);
3930 total_size = total_size + size_thres_mat;
3931
3932 /* fwd weight matrix */
3933 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
3934 total_size = total_size + size_fwd_weight_mat;
3935 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
3936 total_size = total_size + size_fwd_weight_mat;
3937 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
3938 total_size = total_size + size_fwd_weight_mat;
3939
3940 /* threshold matrix for SATQD */
3941 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
3942 total_size = total_size + size_satqd_weight_mat;
3943 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
3944 total_size = total_size + size_satqd_weight_mat;
3945 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
3946 total_size = total_size + size_satqd_weight_mat;
3947
3948 total_size = ALIGN128(total_size);
3949 }
3950 }
3951
3952 isvce_svc_nbr_info_buf_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_REC_TOP_ROW_SYN_INFO]);
3953
3954 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_BS_QP];
3955 {
3956 UWORD8 *pu1_buf_ping;
3957
3958 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of
3959 * every mb*/
3960 WORD32 vert_bs_size, horz_bs_size, qp_size;
3961
3962 /* vertical edge bs = total number of vertical edges * number of bytes per
3963 * each edge */
3964 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3965 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
3966 * bs */
3967 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3968
3969 /* horizontal edge bs = total number of horizontal edges * number of bytes
3970 * per each edge */
3971 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3972 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing
3973 * bs */
3974 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3975
3976 /* qp of each mb requires 1 byte */
3977 qp_size = ALIGN64(max_mb_cnt);
3978
3979 for(i = 0; i < MAX_PROCESS_CTXT; i++)
3980 {
3981 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base;
3982
3983 /* vertical edge bs storage space */
3984 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
3985 (UWORD32 *) pu1_buf_ping;
3986 pu1_buf_ping += vert_bs_size;
3987
3988 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_intra_base_vert_bs =
3989 (UWORD32 *) pu1_buf_ping;
3990 pu1_buf_ping += vert_bs_size;
3991
3992 /* horizontal edge bs storage space */
3993 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
3994 (UWORD32 *) pu1_buf_ping;
3995 pu1_buf_ping += horz_bs_size;
3996
3997 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_intra_base_horz_bs =
3998 (UWORD32 *) pu1_buf_ping;
3999 pu1_buf_ping += horz_bs_size;
4000
4001 /* qp */
4002 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp = (UWORD8 *) pu1_buf_ping;
4003 pu1_buf_ping += qp_size;
4004 }
4005 }
4006
4007 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_INP_PIC];
4008 {
4009 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base;
4010 }
4011
4012 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_OUT];
4013 {
4014 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base;
4015 }
4016
4017 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_CSC];
4018 {
4019 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base;
4020 ps_codec->pu1_uv_csc_buf_base =
4021 (UWORD8 *) ps_mem_rec->pv_base + (max_ht_luma * max_wd_luma);
4022 }
4023
4024 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_REF_PIC];
4025 {
4026 /* size of buf mgr struct */
4027 WORD32 size = ih264_buf_mgr_size();
4028
4029 /* temp var */
4030 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4031
4032 /* pic buffer mgr */
4033 ps_codec->pv_ref_buf_mgr_base = pu1_buf;
4034
4035 /* picture bank */
4036 ps_codec->ps_pic_buf_base = (svc_au_buf_t *) (pu1_buf + size);
4037 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size;
4038 }
4039
4040 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MVBANK];
4041 {
4042 /* size of buf mgr struct */
4043 WORD32 size = ih264_buf_mgr_size();
4044
4045 /* temp var */
4046 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4047
4048 /* mv buffer mgr */
4049 ps_codec->pv_svc_au_data_store_mgr_base = pu1_buf;
4050
4051 /* mv bank */
4052 ps_codec->ps_svc_au_data_base = (svc_au_data_t *) (pu1_buf + size);
4053 ps_codec->i4_svc_au_data_size = ps_mem_rec->u4_mem_size - size;
4054 }
4055
4056 ps_mem_rec = &ps_mem_rec_base[ISVCE_MEM_REC_MB_INFO_NMB];
4057 {
4058 /* temp var */
4059 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4060
4061 /* size of nmb ctxt */
4062 WORD32 size = max_mb_cols * sizeof(isvce_mb_info_nmb_t);
4063
4064 WORD32 nmb_cntr, subpel_buf_size;
4065
4066 /* init nmb info structure pointer in all proc ctxts */
4067 for(i = 0; i < MAX_PROCESS_CTXT; i++)
4068 {
4069 ps_codec->as_process[i].ps_nmb_info = (isvce_mb_info_nmb_t *) (pu1_buf);
4070
4071 pu1_buf += size;
4072 }
4073
4074 /* Additional 4 bytes to allow use of '_mm_loadl_epi64' */
4075 subpel_buf_size = (MB_SIZE * MB_SIZE + 4) * sizeof(UWORD8);
4076
4077 /* adjusting pointers for nmb halfpel buffer */
4078 for(i = 0; i < MAX_PROCESS_CTXT; i++)
4079 {
4080 isvce_mb_info_nmb_t *ps_mb_info_nmb = &ps_codec->as_process[i].ps_nmb_info[0];
4081
4082 for(nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++)
4083 {
4084 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf;
4085
4086 pu1_buf = pu1_buf + subpel_buf_size;
4087
4088 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE;
4089 }
4090 }
4091 }
4092
4093 isvce_svc_inp_buf_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_SPAT_INP]);
4094
4095 isvce_initialize_downscaler(&ps_codec->s_scaler, &ps_mem_rec_base[ISVCE_MEM_DOWN_SCALER],
4096 ps_codec->s_cfg.s_svc_params.d_spatial_res_ratio,
4097 ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers,
4098 ps_codec->s_cfg.u4_wd, ps_codec->s_cfg.u4_ht,
4099 ps_codec->s_cfg.e_arch);
4100
4101 isvce_svc_ilp_buf_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_DATA]);
4102
4103 isvce_ilp_mv_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_ILP_MV_CTXT]);
4104
4105 isvce_svc_res_pred_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_RES_PRED_CTXT]);
4106
4107 isvce_intra_pred_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_INTRA_PRED_CTXT]);
4108
4109 isvce_rc_utils_init(&ps_codec->s_rate_control.s_rc_utils,
4110 &ps_mem_rec_base[ISVCE_MEM_SVC_RC_UTILS_CTXT], ps_codec->s_cfg.e_arch);
4111
4112 #if ENABLE_MODE_STAT_VISUALISER
4113 isvce_msv_ctxt_init(ps_codec, &ps_mem_rec_base[MEM_MODE_STAT_VISUALISER_BUF]);
4114 #endif
4115
4116 isvce_get_rate_control_mem_tab(&ps_codec->s_rate_control, &ps_mem_rec_base[ISVCE_MEM_REC_RC],
4117 USE_BASE);
4118
4119 isvce_sub_pic_rc_ctxt_init(ps_codec, &ps_mem_rec_base[ISVCE_MEM_SVC_SUB_PIC_RC_CTXT]);
4120
4121 status = isvce_init(ps_codec);
4122
4123 return status;
4124 }
4125
4126 /**
4127 *******************************************************************************
4128 *
4129 * @brief
4130 * Retrieves mem records passed to the codec
4131 *
4132 * @par Description:
4133 * Retrieves mem recs passed during init
4134 *
4135 * @param[in] ps_codec_obj
4136 * Pointer to codec object at API level
4137 *
4138 * @param[in] pv_api_ip
4139 * Pointer to input argument structure
4140 *
4141 * @param[out] pv_api_op
4142 * Pointer to output argument structure
4143 *
4144 * @returns error status
4145 *
4146 * @remarks none
4147 *
4148 *******************************************************************************
4149 */
isvce_retrieve_memrec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4150 static WORD32 isvce_retrieve_memrec(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
4151 {
4152 isvce_codec_t *ps_codec = (isvce_codec_t *) ps_codec_obj->pv_codec_handle;
4153
4154 /* ctrl call I/O structures */
4155 isvce_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
4156 isvce_retrieve_mem_rec_op_t *ps_op = pv_api_op;
4157
4158 if(ps_codec->i4_init_done != 1)
4159 {
4160 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
4161 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
4162 return IV_FAIL;
4163 }
4164
4165 /* join threads upon at end of sequence */
4166 isvce_join_threads(ps_codec);
4167
4168 /* collect list of memory records used by the encoder library */
4169 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup,
4170 ISVCE_MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
4171 ps_op->s_ive_op.u4_num_mem_rec_filled = ISVCE_MEM_REC_CNT;
4172
4173 /* clean up mutex memory */
4174 ih264_list_free(ps_codec->pv_entropy_jobq);
4175 ih264_list_free(ps_codec->pv_proc_jobq);
4176 ithread_mutex_destroy(ps_codec->pv_ctl_mutex);
4177 ithread_mutex_destroy(ps_codec->pv_entropy_mutex);
4178
4179 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_svc_au_data_store_mgr);
4180 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_ref_buf_mgr);
4181 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_inp_buf_mgr);
4182 ih264_buf_mgr_free((buf_mgr_t *) ps_codec->pv_out_buf_mgr);
4183
4184 #if ENABLE_MODE_STAT_VISUALISER
4185 isvce_msv_ctxt_delete(ps_codec->ps_mode_stat_visualiser);
4186 #endif
4187
4188 isvce_sub_pic_rc_ctxt_delete(ps_codec->as_process->ps_sub_pic_rc_ctxt);
4189
4190 return IV_SUCCESS;
4191 }
4192
4193 /**
4194 *******************************************************************************
4195 *
4196 * @brief
4197 * Sets the encoder in flush mode.
4198 *
4199 * @par Description:
4200 * Sets the encoder in flush mode
4201 *
4202 * @param[in] ps_codec_obj
4203 * Pointer to codec object at API level
4204 *
4205 * @param[in] pv_api_ip
4206 * Pointer to input argument structure
4207 *
4208 * @param[out] pv_api_op
4209 * Pointer to output argument structure
4210 *
4211 * @returns error status
4212 *
4213 * @remarks This call has no real effect on encoder
4214 *
4215 *******************************************************************************
4216 */
isvce_set_flush_mode(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4217 static WORD32 isvce_set_flush_mode(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
4218 {
4219 /* codec ctxt */
4220 isvce_codec_t *ps_codec = (isvce_codec_t *) ps_codec_obj->pv_codec_handle;
4221
4222 /* ctrl call I/O structures */
4223 isvce_ctl_flush_op_t *ps_ctl_op = pv_api_op;
4224
4225 UNUSED(pv_api_ip);
4226
4227 ps_ctl_op->s_ive_op.u4_error_code = 0;
4228
4229 /* signal flush frame control call */
4230 ps_codec->i4_flush_mode = 1;
4231
4232 return IV_SUCCESS;
4233 }
4234
4235 /**
4236 *******************************************************************************
4237 *
4238 * @brief
4239 * Gets encoder buffer requirements
4240 *
4241 * @par Description:
4242 * Gets the encoder buffer requirements. Basing on max width and max height
4243 * configuration settings, this routine, computes the sizes of necessary input,
4244 * output buffers returns this info to callee.
4245 *
4246 * @param[in] ps_codec_obj
4247 * Pointer to codec object at API level
4248 *
4249 * @param[in] pv_api_ip
4250 * Pointer to input argument structure
4251 *
4252 * @param[out] pv_api_op
4253 * Pointer to output argument structure
4254 *
4255 * @returns error status
4256 *
4257 * @remarks none
4258 *
4259 *******************************************************************************
4260 */
isvce_get_buf_info(void * pv_codec_handle,void * pv_api_ip,void * pv_api_op)4261 static WORD32 isvce_get_buf_info(void *pv_codec_handle, void *pv_api_ip, void *pv_api_op)
4262 {
4263 WORD32 i;
4264 UWORD32 wd, ht;
4265
4266 isvce_codec_t *ps_codec = (isvce_codec_t *) pv_codec_handle;
4267 isvce_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
4268 isvce_ctl_getbufinfo_op_t *ps_op = pv_api_op;
4269
4270 isvce_get_svc_compliant_dimensions(ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers,
4271 ps_codec->s_cfg.s_svc_params.d_spatial_res_ratio,
4272 ALIGN16(ps_ip->s_ive_ip.u4_max_wd),
4273 ALIGN16(ps_ip->s_ive_ip.u4_max_ht), &wd, &ht);
4274
4275 ps_op->s_ive_op.u4_error_code = 0;
4276
4277 /* Number of components in input buffers required for codec &
4278 * Minimum sizes of each component in input buffer required */
4279 if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P)
4280 {
4281 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP;
4282
4283 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4284 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1);
4285 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1);
4286 }
4287 else if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE)
4288 {
4289 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP;
4290
4291 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4292 ps_op->s_ive_op.au4_min_in_buf_size[1] = ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4293 }
4294 else if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565)
4295 {
4296 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP;
4297
4298 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4299 ps_op->s_ive_op.au4_min_in_buf_size[1] = ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4300 }
4301 else if(ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888)
4302 {
4303 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP;
4304
4305 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4;
4306 ps_op->s_ive_op.au4_min_in_buf_size[1] = ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4307 }
4308 else if((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV) ||
4309 (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU))
4310 {
4311 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP;
4312
4313 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4314 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1);
4315 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4316 }
4317
4318 /* Number of components in output buffers required for codec &
4319 * Minimum sizes of each component in output buffer required */
4320 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP;
4321
4322 for(i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++)
4323 {
4324 ps_op->s_ive_op.au4_min_out_buf_size[i] =
4325 isvce_get_min_outbuf_size(wd, ht, ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers);
4326 }
4327
4328 ps_op->u4_rec_comp_cnt = MIN_RAW_BUFS_420_COMP;
4329 ps_op->au4_min_rec_buf_size[0] = wd * ht;
4330 ps_op->au4_min_rec_buf_size[1] = (wd >> 1) * (ht >> 1);
4331 ps_op->au4_min_rec_buf_size[2] = (wd >> 1) * (ht >> 1);
4332
4333 if(ps_codec->s_cfg.b_nalu_info_export_enable)
4334 {
4335 ps_op->u4_min_nalu_info_buf_size =
4336 isvce_get_nalu_info_buf_size(ps_codec->s_cfg.s_svc_params.u1_num_spatial_layers);
4337 }
4338 else
4339 {
4340 ps_op->u4_min_nalu_info_buf_size = 0;
4341 }
4342
4343 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS;
4344 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS;
4345 ps_op->u4_min_rec_bufs = MIN_OUT_BUFS;
4346 ps_op->u4_min_nalu_info_bufs = MIN_OUT_BUFS;
4347
4348 return IV_SUCCESS;
4349 }
4350
4351 /**
4352 *******************************************************************************
4353 *
4354 * @brief
4355 * Sets the picture dimensions
4356 *
4357 * @par Description:
4358 * Sets width, height, display width, display height and strides
4359 *
4360 * @param[in] pv_api_ip
4361 * Pointer to input argument structure
4362 *
4363 * @param[out] pv_api_op
4364 * Pointer to output argument structure
4365 *
4366 * @param[out] ps_cfg
4367 * Pointer to config structure to be updated
4368 *
4369 * @returns error status
4370 *
4371 * @remarks none
4372 *
4373 *******************************************************************************
4374 */
isvce_set_dimensions(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4375 static IV_STATUS_T isvce_set_dimensions(void *pv_api_ip, void *pv_api_op,
4376 isvce_cfg_params_t *ps_cfg)
4377 {
4378 isvce_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
4379 isvce_ctl_set_dimensions_op_t *ps_op = pv_api_op;
4380
4381 ps_op->s_ive_op.u4_error_code = 0;
4382
4383 isvce_get_svc_compliant_dimensions(
4384 ps_cfg->s_svc_params.u1_num_spatial_layers, ps_cfg->s_svc_params.d_spatial_res_ratio,
4385 ps_ip->s_ive_ip.u4_wd, ps_ip->s_ive_ip.u4_ht, &ps_cfg->u4_wd, &ps_cfg->u4_ht);
4386
4387 ASSERT(0 == (ps_cfg->u4_wd % MB_SIZE));
4388 ASSERT(0 == (ps_cfg->u4_ht % MB_SIZE));
4389
4390 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd / MB_SIZE;
4391 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht / MB_SIZE;
4392 ps_cfg->u4_disp_wd = ps_cfg->u4_wd;
4393 ps_cfg->u4_disp_ht = ps_cfg->u4_ht;
4394
4395 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4396 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4397
4398 return IV_SUCCESS;
4399 }
4400
4401 /**
4402 *******************************************************************************
4403 *
4404 * @brief
4405 * Provide dimensions used for encoding
4406 *
4407 * @param[in] pv_api_ip
4408 * Pointer to input argument structure
4409 *
4410 * @param[out] pv_api_op
4411 * Pointer to output argument structure
4412 *
4413 * @param[out] ps_cfg
4414 * Pointer to config structure
4415 *
4416 * @returns error status
4417 *
4418 * @remarks none
4419 *
4420 *******************************************************************************
4421 */
isvce_get_enc_frame_dimensions(isvce_ctl_get_enc_dimensions_ip_t * ps_ip,isvce_ctl_get_enc_dimensions_op_t * ps_op,isvce_cfg_params_t * ps_cfg)4422 static IV_STATUS_T isvce_get_enc_frame_dimensions(isvce_ctl_get_enc_dimensions_ip_t *ps_ip,
4423 isvce_ctl_get_enc_dimensions_op_t *ps_op,
4424 isvce_cfg_params_t *ps_cfg)
4425 {
4426 ps_op->u4_error_code = IVE_ERR_NONE;
4427
4428 isvce_get_svc_compliant_dimensions(ps_cfg->s_svc_params.u1_num_spatial_layers,
4429 ps_cfg->s_svc_params.d_spatial_res_ratio,
4430 ps_ip->u4_inp_frame_wd, ps_ip->u4_inp_frame_ht,
4431 &ps_op->u4_enc_frame_wd, &ps_op->u4_enc_frame_ht);
4432
4433 ASSERT(ps_cfg->u4_wd == ps_op->u4_enc_frame_wd);
4434 ASSERT(ps_cfg->u4_ht == ps_op->u4_enc_frame_ht);
4435
4436 return IV_SUCCESS;
4437 }
4438
4439 /**
4440 *******************************************************************************
4441 *
4442 * @brief
4443 * Sets source and target frame rates
4444 *
4445 * @par Description:
4446 * Sets source and target frame rates
4447 *
4448 * @param[in] pv_api_ip
4449 * Pointer to input argument structure
4450 *
4451 * @param[out] pv_api_op
4452 * Pointer to output argument structure
4453 *
4454 * @param[out] ps_cfg
4455 * Pointer to config structure to be updated
4456 *
4457 * @returns error status
4458 *
4459 * @remarks none
4460 *
4461 *******************************************************************************
4462 */
isvce_set_frame_rate(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4463 static IV_STATUS_T isvce_set_frame_rate(void *pv_api_ip, void *pv_api_op,
4464 isvce_cfg_params_t *ps_cfg)
4465 {
4466 /* ctrl call I/O structures */
4467 isvce_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
4468 isvce_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
4469
4470 ps_op->s_ive_op.u4_error_code = 0;
4471
4472 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate;
4473 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate;
4474
4475 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4476 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4477
4478 return IV_SUCCESS;
4479 }
4480
4481 /**
4482 *******************************************************************************
4483 *
4484 * @brief
4485 * Sets target bit rate
4486 *
4487 * @par Description:
4488 * Sets target bit rate
4489 *
4490 * @param[in] pv_api_ip
4491 * Pointer to input argument structure
4492 *
4493 * @param[out] pv_api_op
4494 * Pointer to output argument structure
4495 *
4496 * @param[out] ps_cfg
4497 * Pointer to config structure to be updated
4498 *
4499 * @returns error status
4500 *
4501 * @remarks none
4502 *
4503 *******************************************************************************
4504 */
isvce_set_bit_rate(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4505 static IV_STATUS_T isvce_set_bit_rate(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4506 {
4507 /* ctrl call I/O structures */
4508 isvce_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
4509 isvce_ctl_set_bitrate_op_t *ps_op = pv_api_op;
4510 WORD8 i;
4511
4512 ps_op->s_ive_op.u4_error_code = 0;
4513
4514 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
4515 {
4516 ps_cfg->au4_target_bitrate[i] = ps_ip->pu4_target_bitrate[i];
4517 }
4518
4519 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4520 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4521
4522 return IV_SUCCESS;
4523 }
4524
4525 /**
4526 *******************************************************************************
4527 *
4528 * @brief
4529 * Sets frame type
4530 *
4531 * @par Description:
4532 * Sets frame type
4533 *
4534 * @param[in] pv_api_ip
4535 * Pointer to input argument structure
4536 *
4537 * @param[out] pv_api_op
4538 * Pointer to output argument structure
4539 *
4540 * @param[out] ps_cfg
4541 * Pointer to config structure to be updated
4542 *
4543 * @returns error status
4544 *
4545 * @remarks not a sticky tag
4546 *
4547 *******************************************************************************
4548 */
isvce_set_frame_type(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4549 static IV_STATUS_T isvce_set_frame_type(void *pv_api_ip, void *pv_api_op,
4550 isvce_cfg_params_t *ps_cfg)
4551 {
4552 /* ctrl call I/O structures */
4553 isvce_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
4554 isvce_ctl_set_frame_type_op_t *ps_op = pv_api_op;
4555
4556 ps_op->s_ive_op.u4_error_code = 0;
4557
4558 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type;
4559
4560 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4561 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4562
4563 return IV_SUCCESS;
4564 }
4565
4566 /**
4567 *******************************************************************************
4568 *
4569 * @brief
4570 * Sets quantization params
4571 *
4572 * @par Description:
4573 * Sets the max, min and default qp for I frame, P frame and B frame
4574 *
4575 * @param[in] pv_api_ip
4576 * Pointer to input argument structure
4577 *
4578 * @param[out] pv_api_op
4579 * Pointer to output argument structure
4580 *
4581 * @param[out] ps_cfg
4582 * Pointer to config structure to be updated
4583 *
4584 * @returns error status
4585 *
4586 * @remarks none
4587 *
4588 *******************************************************************************
4589 */
isvce_set_qp(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4590 static IV_STATUS_T isvce_set_qp(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4591 {
4592 /* ctrl call I/O structures */
4593 isvce_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip;
4594 isvce_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op;
4595 WORD8 i;
4596
4597 ps_set_qp_op->s_ive_op.u4_error_code = 0;
4598
4599 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
4600 {
4601 ps_cfg->au4_i_qp_max[i] =
4602 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_max[i]);
4603 ps_cfg->au4_i_qp_min[i] =
4604 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_min[i]);
4605 ps_cfg->au4_i_qp[i] = CLIP3(ps_set_qp_ip->pu4_i_qp_min[i], ps_set_qp_ip->pu4_i_qp_max[i],
4606 ps_set_qp_ip->pu4_i_qp[i]);
4607 ps_cfg->au4_i_qp_max[i] =
4608 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_max[i]);
4609 ps_cfg->au4_i_qp_min[i] =
4610 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_min[i]);
4611 ps_cfg->au4_i_qp[i] = CLIP3(ps_set_qp_ip->pu4_i_qp_min[i], ps_set_qp_ip->pu4_i_qp_max[i],
4612 ps_set_qp_ip->pu4_i_qp[i]);
4613 ps_cfg->au4_i_qp_max[i] =
4614 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_max[i]);
4615 ps_cfg->au4_i_qp_min[i] =
4616 CLIP3(MIN_H264_QP, MAX_H264_QP, (WORD32) ps_set_qp_ip->pu4_i_qp_min[i]);
4617 ps_cfg->au4_i_qp[i] = CLIP3(ps_set_qp_ip->pu4_i_qp_min[i], ps_set_qp_ip->pu4_i_qp_max[i],
4618 ps_set_qp_ip->pu4_i_qp[i]);
4619 }
4620
4621 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high;
4622 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low;
4623
4624 return IV_SUCCESS;
4625 }
4626
4627 /**
4628 *******************************************************************************
4629 *
4630 * @brief
4631 * Sets encoding mode
4632 *
4633 * @par Description:
4634 * Sets encoding mode
4635 *
4636 * @param[in] pv_api_ip
4637 * Pointer to input argument structure
4638 *
4639 * @param[out] pv_api_op
4640 * Pointer to output argument structure
4641 *
4642 * @param[out] ps_cfg
4643 * Pointer to config structure to be updated
4644 *
4645 * @returns error status
4646 *
4647 * @remarks none
4648 *
4649 *******************************************************************************
4650 */
isvce_set_enc_mode(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4651 static IV_STATUS_T isvce_set_enc_mode(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4652 {
4653 /* ctrl call I/O structures */
4654 isvce_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
4655 isvce_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
4656
4657 ps_op->s_ive_op.u4_error_code = 0;
4658
4659 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode;
4660
4661 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4662 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4663
4664 return IV_SUCCESS;
4665 }
4666
4667 /**
4668 *******************************************************************************
4669 *
4670 * @brief
4671 * Sets vbv parameters
4672 *
4673 * @par Description:
4674 * Sets vbv parameters
4675 *
4676 * @param[in] pv_api_ip
4677 * Pointer to input argument structure
4678 *
4679 * @param[out] pv_api_op
4680 * Pointer to output argument structure
4681 *
4682 * @param[out] ps_cfg
4683 * Pointer to config structure to be updated
4684 *
4685 * @returns error status
4686 *
4687 * @remarks none
4688 *
4689 *******************************************************************************
4690 */
isvce_set_vbv_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4691 static IV_STATUS_T isvce_set_vbv_params(void *pv_api_ip, void *pv_api_op,
4692 isvce_cfg_params_t *ps_cfg)
4693 {
4694 /* ctrl call I/O structures */
4695 isvce_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
4696 isvce_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
4697 WORD8 i;
4698
4699 ps_op->s_ive_op.u4_error_code = 0;
4700
4701 for(i = 0; i < ps_cfg->s_svc_params.u1_num_spatial_layers; i++)
4702 {
4703 ps_cfg->au4_vbv_buffer_delay[i] = ps_ip->pu4_vbv_buffer_delay[i];
4704 }
4705
4706 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4707 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4708
4709 return IV_SUCCESS;
4710 }
4711
4712 /**
4713 *******************************************************************************
4714 *
4715 * @brief
4716 * Sets AIR parameters
4717 *
4718 * @par Description:
4719 * Sets AIR parameters
4720 *
4721 * @param[in] pv_api_ip
4722 * Pointer to input argument structure
4723 *
4724 * @param[out] pv_api_op
4725 * Pointer to output argument structure
4726 *
4727 * @param[out] ps_cfg
4728 * Pointer to config structure to be updated
4729 *
4730 * @returns error status
4731 *
4732 * @remarks none
4733 *
4734 *******************************************************************************
4735 */
isvc_set_air_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4736 static IV_STATUS_T isvc_set_air_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4737 {
4738 /* ctrl call I/O structures */
4739 isvce_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
4740 isvce_ctl_set_air_params_op_t *ps_op = pv_api_op;
4741
4742 ps_op->s_ive_op.u4_error_code = 0;
4743
4744 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode;
4745 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period;
4746
4747 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4748 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4749
4750 return IV_SUCCESS;
4751 }
4752
4753 /**
4754 *******************************************************************************
4755 *
4756 * @brief
4757 * Sets motion estimation parameters
4758 *
4759 * @par Description:
4760 * Sets motion estimation parameters
4761 *
4762 * @param[in] pv_api_ip
4763 * Pointer to input argument structure
4764 *
4765 * @param[out] pv_api_op
4766 * Pointer to output argument structure
4767 *
4768 * @param[out] ps_cfg
4769 * Pointer to config structure to be updated
4770 *
4771 * @returns error status
4772 *
4773 * @remarks none
4774 *
4775 *******************************************************************************
4776 */
isvc_set_me_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4777 static IV_STATUS_T isvc_set_me_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4778 {
4779 /* ctrl call I/O structures */
4780 isvce_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
4781 isvce_ctl_set_me_params_op_t *ps_op = pv_api_op;
4782
4783 ps_op->s_ive_op.u4_error_code = 0;
4784
4785 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel;
4786 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel;
4787 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad;
4788 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref;
4789 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x;
4790 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y;
4791 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset;
4792
4793 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4794 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4795
4796 return IV_SUCCESS;
4797 }
4798
4799 /**
4800 *******************************************************************************
4801 *
4802 * @brief
4803 * Sets Intra/Inter Prediction estimation parameters
4804 *
4805 * @par Description:
4806 * Sets Intra/Inter Prediction estimation parameters
4807 *
4808 * @param[in] pv_api_ip
4809 * Pointer to input argument structure
4810 *
4811 * @param[out] pv_api_op
4812 * Pointer to output argument structure
4813 *
4814 * @param[out] ps_cfg
4815 * Pointer to config structure to be updated
4816 *
4817 * @returns error status
4818 *
4819 * @remarks none
4820 *
4821 *******************************************************************************
4822 */
isvc_set_ipe_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4823 static IV_STATUS_T isvc_set_ipe_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4824 {
4825 /* ctrl call I/O structures */
4826 isvce_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
4827 isvce_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
4828
4829 ps_op->s_ive_op.u4_error_code = 0;
4830
4831 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4;
4832 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset;
4833
4834 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4835 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4836
4837 return IV_SUCCESS;
4838 }
4839
4840 /**
4841 *******************************************************************************
4842 *
4843 * @brief
4844 * Sets GOP parameters
4845 *
4846 * @par Description:
4847 * Sets GOP parameters
4848 *
4849 * @param[in] pv_api_ip
4850 * Pointer to input argument structure
4851 *
4852 * @param[out] pv_api_op
4853 * Pointer to output argument structure
4854 *
4855 * @param[out] ps_cfg
4856 * Pointer to config structure to be updated
4857 *
4858 * @returns error status
4859 *
4860 * @remarks none
4861 *
4862 *******************************************************************************
4863 */
isvc_set_gop_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4864 static IV_STATUS_T isvc_set_gop_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4865 {
4866 /* ctrl call I/O structures */
4867 isvce_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
4868 isvce_ctl_set_gop_params_op_t *ps_op = pv_api_op;
4869
4870 ps_op->s_ive_op.u4_error_code = 0;
4871
4872 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval;
4873 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval;
4874
4875 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4876 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4877
4878 return IV_SUCCESS;
4879 }
4880
4881 /**
4882 *******************************************************************************
4883 *
4884 * @brief
4885 * Sets profile parameters
4886 *
4887 * @par Description:
4888 * Sets profile parameters
4889 *
4890 * @param[in] pv_api_ip
4891 * Pointer to input argument structure
4892 *
4893 * @param[out] pv_api_op
4894 * Pointer to output argument structure
4895 *
4896 * @param[out] ps_cfg
4897 * Pointer to config structure to be updated
4898 *
4899 * @returns error status
4900 *
4901 * @remarks none
4902 *
4903 *******************************************************************************
4904 */
isvc_set_profile_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4905 static IV_STATUS_T isvc_set_profile_params(void *pv_api_ip, void *pv_api_op,
4906 isvce_cfg_params_t *ps_cfg)
4907 {
4908 /* ctrl call I/O structures */
4909 isvce_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
4910 isvce_ctl_set_profile_params_op_t *ps_op = pv_api_op;
4911
4912 ps_op->s_ive_op.u4_error_code = 0;
4913
4914 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile;
4915
4916 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode;
4917
4918 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4919 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4920
4921 return IV_SUCCESS;
4922 }
4923
4924 /**
4925 *******************************************************************************
4926 *
4927 * @brief
4928 * Sets disable deblock level
4929 *
4930 * @par Description:
4931 * Sets disable deblock level. Level 0 means no disabling and level 4 means
4932 * disable completely. 1, 2, 3 are intermediate levels that control amount
4933 * of deblocking done.
4934 *
4935 * @param[in] ps_codec_obj
4936 * Pointer to codec object at API level
4937 *
4938 * @param[in] pv_api_ip
4939 * Pointer to input argument structure
4940 *
4941 * @param[out] pv_api_op
4942 * Pointer to output argument structure
4943 *
4944 * @returns error status
4945 *
4946 * @remarks none
4947 *
4948 *******************************************************************************
4949 */
isvc_set_deblock_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4950 static WORD32 isvc_set_deblock_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4951 {
4952 /* ctrl call I/O structures */
4953 isvce_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
4954 isvce_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
4955
4956 ps_op->s_ive_op.u4_error_code = 0;
4957
4958 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level;
4959
4960 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4961 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4962
4963 return IV_SUCCESS;
4964 }
4965 /**
4966 *******************************************************************************
4967 *
4968 * @brief
4969 * Sets vui params
4970 *
4971 * @par Description:
4972 * Video usability information
4973 *
4974 * @param[in] pv_api_ip
4975 * Pointer to input argument structure
4976 *
4977 * @param[out] pv_api_op
4978 * Pointer to output argument structure
4979 *
4980 * @param[out] ps_cfg
4981 * Pointer to config structure to be updated
4982 *
4983 * @returns error status
4984 *
4985 * @remarks none
4986 *
4987 *******************************************************************************
4988 */
isvce_set_vui_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)4989 static WORD32 isvce_set_vui_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
4990 {
4991 /* ctrl call I/O structures */
4992 isvce_vui_ip_t *ps_ip = pv_api_ip;
4993 isvce_vui_op_t *ps_op = pv_api_op;
4994 vui_t *ps_vui = &ps_cfg->s_vui;
4995
4996 ps_op->u4_error_code = 0;
4997
4998 ps_vui->u1_aspect_ratio_info_present_flag = ps_ip->u1_aspect_ratio_info_present_flag;
4999 ps_vui->u1_aspect_ratio_idc = ps_ip->u1_aspect_ratio_idc;
5000 ps_vui->u2_sar_width = ps_ip->u2_sar_width;
5001 ps_vui->u2_sar_height = ps_ip->u2_sar_height;
5002 ps_vui->u1_overscan_info_present_flag = ps_ip->u1_overscan_info_present_flag;
5003 ps_vui->u1_overscan_appropriate_flag = ps_ip->u1_overscan_appropriate_flag;
5004 ps_vui->u1_video_signal_type_present_flag = ps_ip->u1_video_signal_type_present_flag;
5005 ps_vui->u1_video_format = ps_ip->u1_video_format;
5006 ps_vui->u1_video_full_range_flag = ps_ip->u1_video_full_range_flag;
5007 ps_vui->u1_colour_description_present_flag = ps_ip->u1_colour_description_present_flag;
5008 ps_vui->u1_colour_primaries = ps_ip->u1_colour_primaries;
5009 ps_vui->u1_transfer_characteristics = ps_ip->u1_transfer_characteristics;
5010 ps_vui->u1_matrix_coefficients = ps_ip->u1_matrix_coefficients;
5011 ps_vui->u1_chroma_loc_info_present_flag = ps_ip->u1_chroma_loc_info_present_flag;
5012 ps_vui->u1_chroma_sample_loc_type_top_field = ps_ip->u1_chroma_sample_loc_type_top_field;
5013 ps_vui->u1_chroma_sample_loc_type_bottom_field = ps_ip->u1_chroma_sample_loc_type_bottom_field;
5014 ps_vui->u1_vui_timing_info_present_flag = ps_ip->u1_vui_timing_info_present_flag;
5015 ps_vui->u4_vui_num_units_in_tick = ps_ip->u4_vui_num_units_in_tick;
5016 ps_vui->u4_vui_time_scale = ps_ip->u4_vui_time_scale;
5017 ps_vui->u1_fixed_frame_rate_flag = ps_ip->u1_fixed_frame_rate_flag;
5018 ps_vui->u1_nal_hrd_parameters_present_flag = ps_ip->u1_nal_hrd_parameters_present_flag;
5019 ps_vui->u1_vcl_hrd_parameters_present_flag = ps_ip->u1_vcl_hrd_parameters_present_flag;
5020 ps_vui->u1_low_delay_hrd_flag = ps_ip->u1_low_delay_hrd_flag;
5021 ps_vui->u1_pic_struct_present_flag = ps_ip->u1_pic_struct_present_flag;
5022 ps_vui->u1_bitstream_restriction_flag = ps_ip->u1_bitstream_restriction_flag;
5023 ps_vui->u1_motion_vectors_over_pic_boundaries_flag =
5024 ps_ip->u1_motion_vectors_over_pic_boundaries_flag;
5025 ps_vui->u1_max_bytes_per_pic_denom = ps_ip->u1_max_bytes_per_pic_denom;
5026 ps_vui->u1_max_bits_per_mb_denom = ps_ip->u1_max_bits_per_mb_denom;
5027 ps_vui->u1_log2_max_mv_length_horizontal = ps_ip->u1_log2_max_mv_length_horizontal;
5028 ps_vui->u1_log2_max_mv_length_vertical = ps_ip->u1_log2_max_mv_length_vertical;
5029 ps_vui->u1_num_reorder_frames = ps_ip->u1_num_reorder_frames;
5030 ps_vui->u1_max_dec_frame_buffering = ps_ip->u1_max_dec_frame_buffering;
5031
5032 return IV_SUCCESS;
5033 }
5034
5035 /**
5036 *******************************************************************************
5037 *
5038 * @brief
5039 * Sets Mastering display color volume sei params
5040 *
5041 * @par Description:
5042 * Supplemental enhancement information
5043 *
5044 * @param[in] pv_api_ip
5045 * Pointer to input argument structure
5046 *
5047 * @param[out] pv_api_op
5048 * Pointer to output argument structure
5049 *
5050 * @param[out] ps_cfg
5051 * Pointer to config structure to be updated
5052 *
5053 * @return error status
5054 *
5055 * @remarks none
5056 *
5057 *******************************************************************************
5058 */
isvce_set_sei_mdcv_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5059 static WORD32 isvce_set_sei_mdcv_params(void *pv_api_ip, void *pv_api_op,
5060 isvce_cfg_params_t *ps_cfg)
5061 {
5062 WORD32 i4_count;
5063 /* ctrl call I/O structures */
5064 isvce_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
5065 isvce_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
5066 sei_params_t *ps_sei = &ps_cfg->s_sei;
5067
5068 ps_op->u4_error_code = 0;
5069
5070 ps_sei->u1_sei_mdcv_params_present_flag = ps_ip->u1_sei_mdcv_params_present_flag;
5071 for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
5072 {
5073 ps_sei->s_sei_mdcv_params.au2_display_primaries_x[i4_count] =
5074 ps_ip->au2_display_primaries_x[i4_count];
5075 ps_sei->s_sei_mdcv_params.au2_display_primaries_y[i4_count] =
5076 ps_ip->au2_display_primaries_y[i4_count];
5077 }
5078
5079 ps_sei->s_sei_mdcv_params.u2_white_point_x = ps_ip->u2_white_point_x;
5080 ps_sei->s_sei_mdcv_params.u2_white_point_y = ps_ip->u2_white_point_y;
5081 ps_sei->s_sei_mdcv_params.u4_max_display_mastering_luminance =
5082 ps_ip->u4_max_display_mastering_luminance;
5083 ps_sei->s_sei_mdcv_params.u4_min_display_mastering_luminance =
5084 ps_ip->u4_min_display_mastering_luminance;
5085
5086 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5087 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5088
5089 return IV_SUCCESS;
5090 }
5091
5092 /**
5093 *******************************************************************************
5094 *
5095 * @brief
5096 * Sets content light level sei params
5097 *
5098 * @par Description:
5099 * Supplemental enhancement information
5100 *
5101 * @param[in] pv_api_ip
5102 * Pointer to input argument structure
5103 *
5104 * @param[out] pv_api_op
5105 * Pointer to output argument structure
5106 *
5107 * @param[out] ps_cfg
5108 * Pointer to config structure to be updated
5109 *
5110 * @return error status
5111 *
5112 * @remarks none
5113 *
5114 *******************************************************************************
5115 */
isvce_set_sei_cll_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5116 static WORD32 isvce_set_sei_cll_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5117 {
5118 /* ctrl call I/O structures */
5119 isvce_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
5120 isvce_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
5121 sei_params_t *ps_sei = &ps_cfg->s_sei;
5122
5123 ps_op->u4_error_code = 0;
5124
5125 ps_sei->u1_sei_cll_params_present_flag = ps_ip->u1_sei_cll_params_present_flag;
5126
5127 ps_sei->s_sei_cll_params.u2_max_content_light_level = ps_ip->u2_max_content_light_level;
5128 ps_sei->s_sei_cll_params.u2_max_pic_average_light_level = ps_ip->u2_max_pic_average_light_level;
5129
5130 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5131 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5132
5133 return IV_SUCCESS;
5134 }
5135
5136 /**
5137 *******************************************************************************
5138 *
5139 * @brief
5140 * Sets ambient viewing environment sei params
5141 *
5142 * @par Description:
5143 * Supplemental enhancement information
5144 *
5145 * @param[in] pv_api_ip
5146 * Pointer to input argument structure
5147 *
5148 * @param[out] pv_api_op
5149 * Pointer to output argument structure
5150 *
5151 * @param[out] ps_cfg
5152 * Pointer to config structure to be updated
5153 *
5154 * @return error status
5155 *
5156 * @remarks none
5157 *
5158 *******************************************************************************
5159 */
isvce_set_sei_ave_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5160 static WORD32 isvce_set_sei_ave_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5161 {
5162 /* ctrl call I/O structures */
5163 isvce_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
5164 isvce_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
5165 sei_params_t *ps_sei = &ps_cfg->s_sei;
5166
5167 ps_op->u4_error_code = 0;
5168
5169 ps_sei->u1_sei_ave_params_present_flag = ps_ip->u1_sei_ave_params_present_flag;
5170
5171 ps_sei->s_sei_ave_params.u4_ambient_illuminance = ps_ip->u4_ambient_illuminance;
5172 ps_sei->s_sei_ave_params.u2_ambient_light_x = ps_ip->u2_ambient_light_x;
5173 ps_sei->s_sei_ave_params.u2_ambient_light_y = ps_ip->u2_ambient_light_y;
5174
5175 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5176 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5177
5178 return IV_SUCCESS;
5179 }
5180
5181 /**
5182 *******************************************************************************
5183 *
5184 * @brief
5185 * Sets content color volume sei params
5186 *
5187 * @par Description:
5188 * Supplemental enhancement information
5189 *
5190 * @param[in] pv_api_ip
5191 * Pointer to input argument structure
5192 *
5193 * @param[out] pv_api_op
5194 * Pointer to output argument structure
5195 *
5196 * @param[out] ps_cfg
5197 * Pointer to config structure to be updated
5198 *
5199 * @return error status
5200 *
5201 * @remarks none
5202 *
5203 *******************************************************************************
5204 */
isvce_set_sei_ccv_params(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5205 static WORD32 isvce_set_sei_ccv_params(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5206 {
5207 WORD32 i4_count;
5208 /* ctrl call I/O structures */
5209 isvce_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
5210 isvce_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
5211 sei_params_t *ps_sei = &ps_cfg->s_sei;
5212
5213 ps_op->u4_error_code = 0;
5214
5215 ps_sei->u1_sei_ccv_params_present_flag = ps_ip->u1_sei_ccv_params_present_flag;
5216
5217 ps_sei->s_sei_ccv_params.u1_ccv_cancel_flag = ps_ip->u1_ccv_cancel_flag;
5218 ps_sei->s_sei_ccv_params.u1_ccv_persistence_flag = ps_ip->u1_ccv_persistence_flag;
5219 ps_sei->s_sei_ccv_params.u1_ccv_primaries_present_flag = ps_ip->u1_ccv_primaries_present_flag;
5220 ps_sei->s_sei_ccv_params.u1_ccv_min_luminance_value_present_flag =
5221 ps_ip->u1_ccv_min_luminance_value_present_flag;
5222 ps_sei->s_sei_ccv_params.u1_ccv_max_luminance_value_present_flag =
5223 ps_ip->u1_ccv_max_luminance_value_present_flag;
5224 ps_sei->s_sei_ccv_params.u1_ccv_avg_luminance_value_present_flag =
5225 ps_ip->u1_ccv_avg_luminance_value_present_flag;
5226 ps_sei->s_sei_ccv_params.u1_ccv_reserved_zero_2bits = ps_ip->u1_ccv_reserved_zero_2bits;
5227
5228 for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
5229 {
5230 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_x[i4_count] =
5231 ps_ip->ai4_ccv_primaries_x[i4_count];
5232 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_y[i4_count] =
5233 ps_ip->ai4_ccv_primaries_y[i4_count];
5234 }
5235
5236 ps_sei->s_sei_ccv_params.u4_ccv_min_luminance_value = ps_ip->u4_ccv_min_luminance_value;
5237 ps_sei->s_sei_ccv_params.u4_ccv_max_luminance_value = ps_ip->u4_ccv_max_luminance_value;
5238 ps_sei->s_sei_ccv_params.u4_ccv_avg_luminance_value = ps_ip->u4_ccv_avg_luminance_value;
5239
5240 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5241 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5242
5243 return IV_SUCCESS;
5244 }
5245
5246 /**
5247 *******************************************************************************
5248 *
5249 * @brief
5250 * Sets number of cores
5251 *
5252 * @par Description:
5253 * Sets number of cores
5254 *
5255 * @param[in] ps_codec_obj
5256 * Pointer to codec object at API level
5257 *
5258 * @param[in] pv_api_ip
5259 * Pointer to input argument structure
5260 *
5261 * @param[out] pv_api_op
5262 * Pointer to output argument structure
5263 *
5264 * @returns error status
5265 *
5266 * @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS
5267 *
5268 *******************************************************************************
5269 */
isvce_set_num_cores(void * pv_api_ip,void * pv_api_op,isvce_cfg_params_t * ps_cfg)5270 static WORD32 isvce_set_num_cores(void *pv_api_ip, void *pv_api_op, isvce_cfg_params_t *ps_cfg)
5271 {
5272 /* ctrl call I/O structures */
5273 isvce_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
5274 isvce_ctl_set_num_cores_op_t *ps_op = pv_api_op;
5275
5276 ps_op->s_ive_op.u4_error_code = 0;
5277
5278 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS);
5279
5280 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5281 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5282
5283 return IV_SUCCESS;
5284 }
5285
5286 /**
5287 *******************************************************************************
5288 *
5289 * @brief
5290 * Resets encoder state
5291 *
5292 * @par Description:
5293 * Resets encoder state by calling isvce_init()
5294 *
5295 * @param[in] ps_codec_obj
5296 * Pointer to codec object at API level
5297 *
5298 * @param[in] pv_api_ip
5299 * Pointer to input argument structure
5300 *
5301 * @param[out] pv_api_op
5302 * Pointer to output argument structure
5303 *
5304 * @returns error status
5305 *
5306 * @remarks none
5307 *
5308 *******************************************************************************
5309 */
isvce_reset(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5310 static WORD32 isvce_reset(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op)
5311 {
5312 /* codec ctxt */
5313 isvce_codec_t *ps_codec = (isvce_codec_t *) (ps_codec_obj->pv_codec_handle);
5314
5315 /* ctrl call I/O structures */
5316 isvce_ctl_reset_op_t *ps_op = pv_api_op;
5317
5318 UNUSED(pv_api_ip);
5319
5320 ps_op->s_ive_op.u4_error_code = 0;
5321
5322 if(ps_codec != NULL)
5323 {
5324 isvce_init(ps_codec);
5325 }
5326 else
5327 {
5328 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE;
5329 }
5330
5331 return IV_SUCCESS;
5332 }
5333
isvce_ctl_set_error_code(void * pv_api_op,ISVCE_CONTROL_API_COMMAND_TYPE_T e_sub_cmd)5334 static void isvce_ctl_set_error_code(void *pv_api_op, ISVCE_CONTROL_API_COMMAND_TYPE_T e_sub_cmd)
5335 {
5336 switch(e_sub_cmd)
5337 {
5338 case ISVCE_CMD_CTL_SET_DIMENSIONS:
5339 {
5340 ((isvce_ctl_set_dimensions_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5341 1 << IVE_FATALERROR;
5342 ((isvce_ctl_set_dimensions_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5343 IH264E_INIT_NOT_DONE;
5344
5345 break;
5346 }
5347 case ISVCE_CMD_CTL_SET_FRAMERATE:
5348 {
5349 ((isvce_ctl_set_frame_rate_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5350 1 << IVE_FATALERROR;
5351 ((isvce_ctl_set_frame_rate_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5352 IH264E_INIT_NOT_DONE;
5353
5354 break;
5355 }
5356 case ISVCE_CMD_CTL_SET_BITRATE:
5357 {
5358 ((isvce_ctl_set_bitrate_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1
5359 << IVE_FATALERROR;
5360 ((isvce_ctl_set_bitrate_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5361 IH264E_INIT_NOT_DONE;
5362
5363 break;
5364 }
5365 case ISVCE_CMD_CTL_SET_FRAMETYPE:
5366 {
5367 ((isvce_ctl_set_frame_type_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5368 1 << IVE_FATALERROR;
5369 ((isvce_ctl_set_frame_type_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5370 IH264E_INIT_NOT_DONE;
5371
5372 break;
5373 }
5374 case ISVCE_CMD_CTL_SET_QP:
5375 {
5376 ((isvce_ctl_set_qp_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5377 ((isvce_ctl_set_qp_op_t *) pv_api_op)->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5378
5379 break;
5380 }
5381 case ISVCE_CMD_CTL_SET_ENC_MODE:
5382 {
5383 ((isvce_ctl_set_enc_mode_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5384 1 << IVE_FATALERROR;
5385 ((isvce_ctl_set_enc_mode_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5386 IH264E_INIT_NOT_DONE;
5387
5388 break;
5389 }
5390 case ISVCE_CMD_CTL_SET_VBV_PARAMS:
5391 {
5392 ((isvce_ctl_set_vbv_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5393 1 << IVE_FATALERROR;
5394 ((isvce_ctl_set_vbv_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5395 IH264E_INIT_NOT_DONE;
5396
5397 break;
5398 }
5399 case ISVCE_CMD_CTL_SET_AIR_PARAMS:
5400 {
5401 ((isvce_ctl_set_air_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5402 1 << IVE_FATALERROR;
5403 ((isvce_ctl_set_air_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5404 IH264E_INIT_NOT_DONE;
5405
5406 break;
5407 }
5408 case ISVCE_CMD_CTL_SET_ME_PARAMS:
5409 {
5410 ((isvce_ctl_set_me_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5411 1 << IVE_FATALERROR;
5412 ((isvce_ctl_set_me_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5413 IH264E_INIT_NOT_DONE;
5414
5415 break;
5416 }
5417 case ISVCE_CMD_CTL_SET_IPE_PARAMS:
5418 {
5419 ((isvce_ctl_set_ipe_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5420 1 << IVE_FATALERROR;
5421 ((isvce_ctl_set_ipe_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5422 IH264E_INIT_NOT_DONE;
5423
5424 break;
5425 }
5426 case ISVCE_CMD_CTL_SET_GOP_PARAMS:
5427 {
5428 ((isvce_ctl_set_gop_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5429 1 << IVE_FATALERROR;
5430 ((isvce_ctl_set_gop_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5431 IH264E_INIT_NOT_DONE;
5432
5433 break;
5434 }
5435 case ISVCE_CMD_CTL_SET_PROFILE_PARAMS:
5436 {
5437 ((isvce_ctl_set_profile_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5438 1 << IVE_FATALERROR;
5439 ((isvce_ctl_set_profile_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5440 IH264E_INIT_NOT_DONE;
5441
5442 break;
5443 }
5444 case ISVCE_CMD_CTL_SET_DEBLOCK_PARAMS:
5445 {
5446 ((isvce_ctl_set_deblock_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5447 1 << IVE_FATALERROR;
5448 ((isvce_ctl_set_deblock_params_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5449 IH264E_INIT_NOT_DONE;
5450
5451 break;
5452 }
5453 case ISVCE_CMD_CTL_SET_VUI_PARAMS:
5454 {
5455 ((isvce_vui_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5456 ((isvce_vui_op_t *) pv_api_op)->u4_error_code |= IH264E_INIT_NOT_DONE;
5457
5458 break;
5459 }
5460 case ISVCE_CMD_CTL_SET_SEI_MDCV_PARAMS:
5461 {
5462 ((isvce_ctl_set_sei_mdcv_params_op_t *) pv_api_op)->u4_error_code |= 1
5463 << IVE_FATALERROR;
5464 ((isvce_ctl_set_sei_mdcv_params_op_t *) pv_api_op)->u4_error_code |=
5465 IH264E_INIT_NOT_DONE;
5466
5467 break;
5468 }
5469 case ISVCE_CMD_CTL_SET_SEI_CLL_PARAMS:
5470 {
5471 ((isvce_ctl_set_sei_cll_params_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5472 ((isvce_ctl_set_sei_cll_params_op_t *) pv_api_op)->u4_error_code |=
5473 IH264E_INIT_NOT_DONE;
5474
5475 break;
5476 }
5477 case ISVCE_CMD_CTL_SET_SEI_AVE_PARAMS:
5478 {
5479 ((isvce_ctl_set_sei_ave_params_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5480 ((isvce_ctl_set_sei_ave_params_op_t *) pv_api_op)->u4_error_code |=
5481 IH264E_INIT_NOT_DONE;
5482
5483 break;
5484 }
5485 case ISVCE_CMD_CTL_SET_SEI_CCV_PARAMS:
5486 {
5487 ((isvce_ctl_set_sei_ccv_params_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5488 ((isvce_ctl_set_sei_ccv_params_op_t *) pv_api_op)->u4_error_code |=
5489 IH264E_INIT_NOT_DONE;
5490
5491 break;
5492 }
5493 case ISVCE_CMD_CTL_RESET:
5494 {
5495 ((isvce_ctl_reset_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5496 ((isvce_ctl_reset_op_t *) pv_api_op)->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5497
5498 break;
5499 }
5500 case ISVCE_CMD_CTL_SETDEFAULT:
5501 {
5502 ((isvce_ctl_setdefault_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1
5503 << IVE_FATALERROR;
5504 ((isvce_ctl_setdefault_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5505 IH264E_INIT_NOT_DONE;
5506
5507 break;
5508 }
5509 case ISVCE_CMD_CTL_FLUSH:
5510 {
5511 ((isvce_ctl_flush_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5512 ((isvce_ctl_flush_op_t *) pv_api_op)->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5513
5514 break;
5515 }
5516 case ISVCE_CMD_CTL_GETBUFINFO:
5517 {
5518 ((isvce_ctl_getbufinfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |= 1
5519 << IVE_FATALERROR;
5520 ((isvce_ctl_getbufinfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5521 IH264E_INIT_NOT_DONE;
5522
5523 break;
5524 }
5525 case ISVCE_CMD_CTL_GETVERSION:
5526 {
5527 ((isvce_ctl_getversioninfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5528 1 << IVE_FATALERROR;
5529 ((isvce_ctl_getversioninfo_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5530 IH264E_INIT_NOT_DONE;
5531
5532 break;
5533 }
5534 case ISVCE_CMD_CTL_SET_NUM_CORES:
5535 {
5536 ((isvce_ctl_set_num_cores_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5537 1 << IVE_FATALERROR;
5538 ((isvce_ctl_set_num_cores_op_t *) pv_api_op)->s_ive_op.u4_error_code |=
5539 IH264E_INIT_NOT_DONE;
5540
5541 break;
5542 }
5543 case ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS:
5544 {
5545 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |= 1 << IVE_FATALERROR;
5546 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5547 IH264E_INIT_NOT_DONE;
5548
5549 break;
5550 }
5551 default:
5552 {
5553 ASSERT(0);
5554 }
5555 }
5556 }
5557
5558 /**
5559 *******************************************************************************
5560 *
5561 * @brief
5562 * Codec control call
5563 *
5564 * @par Description:
5565 * Codec control call which in turn calls appropriate calls based on
5566 *sub-command
5567 *
5568 * @param[in] ps_codec_obj
5569 * Pointer to codec object at API level
5570 *
5571 * @param[in] pv_api_ip
5572 * Pointer to input argument structure
5573 *
5574 * @param[out] pv_api_op
5575 * Pointer to output argument structure
5576 *
5577 * @returns error status
5578 *
5579 * @remarks none
5580 *
5581 *******************************************************************************
5582 */
isvce_ctl(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op,ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd)5583 static WORD32 isvce_ctl(iv_obj_t *ps_codec_obj, void *pv_api_ip, void *pv_api_op,
5584 ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd)
5585 {
5586 WORD32 i;
5587
5588 isvce_codec_t *ps_codec = (isvce_codec_t *) ps_codec_obj->pv_codec_handle;
5589 isvce_cfg_params_t *ps_cfg = NULL;
5590
5591 IV_STATUS_T ret = IV_SUCCESS;
5592
5593 /* control call is for configuring encoding params, this is not to be called
5594 * before a successful init call */
5595 if(ps_codec->i4_init_done != 1)
5596 {
5597 isvce_ctl_set_error_code(pv_api_op, e_ctl_cmd);
5598
5599 return IV_FAIL;
5600 }
5601
5602 /* make it thread safe */
5603 ithread_mutex_lock(ps_codec->pv_ctl_mutex);
5604
5605 /* find a free config param set to hold current parameters */
5606 if(e_ctl_cmd != ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS)
5607 {
5608 for(i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
5609 {
5610 if(0 == ps_codec->as_cfg[i].u4_is_valid)
5611 {
5612 ps_cfg = &ps_codec->as_cfg[i];
5613 break;
5614 }
5615 }
5616
5617 /* If all are invalid, then start overwriting from the head config params */
5618 if(NULL == ps_cfg)
5619 {
5620 ps_cfg = &ps_codec->as_cfg[0];
5621 }
5622
5623 ps_cfg->u4_is_valid = 1;
5624
5625 ps_cfg->s_svc_params = ps_codec->s_cfg.s_svc_params;
5626 ps_cfg->e_cmd = e_ctl_cmd;
5627 }
5628
5629 switch(e_ctl_cmd)
5630 {
5631 case ISVCE_CMD_CTL_SET_DIMENSIONS:
5632 ret = isvce_set_dimensions(pv_api_ip, pv_api_op, ps_cfg);
5633 break;
5634
5635 case ISVCE_CMD_CTL_SET_FRAMERATE:
5636 ret = isvce_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg);
5637 break;
5638
5639 case ISVCE_CMD_CTL_SET_BITRATE:
5640 ret = isvce_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg);
5641 break;
5642
5643 case ISVCE_CMD_CTL_SET_FRAMETYPE:
5644 ret = isvce_set_frame_type(pv_api_ip, pv_api_op, ps_cfg);
5645 break;
5646
5647 case ISVCE_CMD_CTL_SET_QP:
5648 ret = isvce_set_qp(pv_api_ip, pv_api_op, ps_cfg);
5649 break;
5650
5651 case ISVCE_CMD_CTL_SET_ENC_MODE:
5652 ret = isvce_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg);
5653 break;
5654
5655 case ISVCE_CMD_CTL_SET_VBV_PARAMS:
5656 ret = isvce_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg);
5657 break;
5658
5659 case ISVCE_CMD_CTL_SET_AIR_PARAMS:
5660 ret = isvc_set_air_params(pv_api_ip, pv_api_op, ps_cfg);
5661 break;
5662
5663 case ISVCE_CMD_CTL_SET_ME_PARAMS:
5664 ret = isvc_set_me_params(pv_api_ip, pv_api_op, ps_cfg);
5665 break;
5666
5667 case ISVCE_CMD_CTL_SET_IPE_PARAMS:
5668 ret = isvc_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg);
5669 break;
5670
5671 case ISVCE_CMD_CTL_SET_GOP_PARAMS:
5672 ret = isvc_set_gop_params(pv_api_ip, pv_api_op, ps_cfg);
5673 break;
5674
5675 case ISVCE_CMD_CTL_SET_PROFILE_PARAMS:
5676 ret = isvc_set_profile_params(pv_api_ip, pv_api_op, ps_cfg);
5677 break;
5678
5679 case ISVCE_CMD_CTL_SET_DEBLOCK_PARAMS:
5680 ret = isvc_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg);
5681 break;
5682
5683 case ISVCE_CMD_CTL_SET_VUI_PARAMS:
5684 ret = isvce_set_vui_params(pv_api_ip, pv_api_op, ps_cfg);
5685 break;
5686
5687 case ISVCE_CMD_CTL_SET_SEI_MDCV_PARAMS:
5688 ret = isvce_set_sei_mdcv_params(pv_api_ip, pv_api_op, ps_cfg);
5689 break;
5690
5691 case ISVCE_CMD_CTL_SET_SEI_CLL_PARAMS:
5692 ret = isvce_set_sei_cll_params(pv_api_ip, pv_api_op, ps_cfg);
5693 break;
5694
5695 case ISVCE_CMD_CTL_SET_SEI_AVE_PARAMS:
5696 ret = isvce_set_sei_ave_params(pv_api_ip, pv_api_op, ps_cfg);
5697 break;
5698
5699 case ISVCE_CMD_CTL_SET_SEI_CCV_PARAMS:
5700 ret = isvce_set_sei_ccv_params(pv_api_ip, pv_api_op, ps_cfg);
5701 break;
5702
5703 case ISVCE_CMD_CTL_RESET:
5704
5705 /* invalidate config param struct as it is being served right away */
5706 ps_codec->as_cfg[i].u4_is_valid = 0;
5707
5708 ret = isvce_reset(ps_codec_obj, pv_api_ip, pv_api_op);
5709 break;
5710
5711 case ISVCE_CMD_CTL_SETDEFAULT:
5712 {
5713 /* ctrl call I/O structures */
5714 isvce_ctl_setdefault_op_t *ps_op = pv_api_op;
5715
5716 /* invalidate config param struct as it is being served right away */
5717 ps_codec->as_cfg[i].u4_is_valid = 0;
5718
5719 /* error status */
5720 ret = isvce_set_default_params(ps_cfg);
5721
5722 ps_op->s_ive_op.u4_error_code = ret;
5723
5724 break;
5725 }
5726
5727 case ISVCE_CMD_CTL_FLUSH:
5728
5729 /* invalidate config param struct as it is being served right away */
5730 ps_codec->as_cfg[i].u4_is_valid = 0;
5731
5732 ret = isvce_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op);
5733 break;
5734
5735 case ISVCE_CMD_CTL_GETBUFINFO:
5736
5737 /* invalidate config param struct as it is being served right away */
5738 ps_codec->as_cfg[i].u4_is_valid = 0;
5739
5740 ret = isvce_get_buf_info(ps_codec_obj->pv_codec_handle, pv_api_ip, pv_api_op);
5741 break;
5742
5743 case ISVCE_CMD_CTL_GETVERSION:
5744 {
5745 /* ctrl call I/O structures */
5746 isvce_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
5747 isvce_ctl_getversioninfo_op_t *ps_op = pv_api_op;
5748
5749 /* invalidate config param struct as it is being served right away */
5750 ps_codec->as_cfg[i].u4_is_valid = 0;
5751
5752 /* error status */
5753 ps_op->s_ive_op.u4_error_code = IV_SUCCESS;
5754
5755 if(ps_ip->s_ive_ip.u4_version_bufsize <= 0)
5756 {
5757 ps_op->s_ive_op.u4_error_code = IH264E_CXA_VERS_BUF_INSUFFICIENT;
5758 ret = IV_FAIL;
5759 }
5760 else
5761 {
5762 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version,
5763 ps_ip->s_ive_ip.u4_version_bufsize);
5764
5765 if(ret != IV_SUCCESS)
5766 {
5767 ps_op->s_ive_op.u4_error_code = IH264E_CXA_VERS_BUF_INSUFFICIENT;
5768 ret = IV_FAIL;
5769 }
5770 }
5771 break;
5772 }
5773
5774 case ISVCE_CMD_CTL_SET_NUM_CORES:
5775 ret = isvce_set_num_cores(pv_api_ip, pv_api_op, ps_cfg);
5776 break;
5777
5778 case ISVCE_CMD_CTL_GET_ENC_FRAME_DIMENSIONS:
5779 {
5780 ps_cfg = NULL;
5781
5782 for(i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
5783 {
5784 if(ps_codec->as_cfg[i].u4_is_valid &&
5785 (ps_codec->as_cfg[i].e_cmd == ISVCE_CMD_CTL_SET_DIMENSIONS))
5786 {
5787 ps_cfg = &ps_codec->as_cfg[i];
5788
5789 break;
5790 }
5791 }
5792
5793 if(NULL == ps_cfg)
5794 {
5795 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5796 1 << IVE_FATALERROR;
5797 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5798 IH264E_WIDTH_NOT_SUPPORTED;
5799 ((isvce_ctl_get_enc_dimensions_op_t *) pv_api_op)->u4_error_code |=
5800 IH264E_HEIGHT_NOT_SUPPORTED;
5801
5802 return IV_FAIL;
5803 }
5804
5805 ret = isvce_get_enc_frame_dimensions((isvce_ctl_get_enc_dimensions_ip_t *) pv_api_ip,
5806 (isvce_ctl_get_enc_dimensions_op_t *) pv_api_op,
5807 ps_cfg);
5808
5809 break;
5810 }
5811
5812 default:
5813 /* invalidate config param struct as it is being served right away */
5814 ps_codec->as_cfg[i].u4_is_valid = 0;
5815
5816 DEBUG("Warning !! unrecognized control api command \n");
5817 break;
5818 }
5819
5820 ithread_mutex_unlock(ps_codec->pv_ctl_mutex);
5821
5822 return ret;
5823 }
5824
5825 /**
5826 *******************************************************************************
5827 *
5828 * @brief
5829 * Codec entry point function. All the function calls to the codec are done
5830 * using this function with different values specified in command
5831 *
5832 * @par Description:
5833 * Arguments are tested for validity and then based on the command
5834 * appropriate function is called
5835 *
5836 * @param[in] ps_handle
5837 * API level handle for codec
5838 *
5839 * @param[in] pv_api_ip
5840 * Input argument structure
5841 *
5842 * @param[out] pv_api_op
5843 * Output argument structure
5844 *
5845 * @returns error_status
5846 *
5847 * @remarks
5848 *
5849 *******************************************************************************
5850 */
isvce_api_function(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op,isvce_api_cmds_t * ps_iv_api_cmds)5851 IV_STATUS_T isvce_api_function(iv_obj_t *ps_handle, void *pv_api_ip, void *pv_api_op,
5852 isvce_api_cmds_t *ps_iv_api_cmds)
5853 {
5854 IV_STATUS_T e_status;
5855 WORD32 ret;
5856
5857 ISVCE_API_COMMAND_TYPE_T e_cmd = ps_iv_api_cmds->e_cmd;
5858 ISVCE_CONTROL_API_COMMAND_TYPE_T e_ctl_cmd = ps_iv_api_cmds->e_ctl_cmd;
5859
5860 /* validate input / output structures */
5861 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op, ps_iv_api_cmds);
5862
5863 if(e_status != IV_SUCCESS)
5864 {
5865 DEBUG("error code = %d\n", *((UWORD32 *) pv_api_op + 1));
5866 return IV_FAIL;
5867 }
5868
5869 switch(e_cmd)
5870 {
5871 case ISVCE_CMD_GET_NUM_MEM_REC:
5872 ret = isvce_get_num_rec(pv_api_ip, pv_api_op);
5873 break;
5874
5875 case ISVCE_CMD_FILL_NUM_MEM_REC:
5876 ret = isvce_fill_num_mem_rec(pv_api_ip, pv_api_op);
5877 break;
5878
5879 case ISVCE_CMD_INIT:
5880 ret = isvce_init_mem_rec(ps_handle, pv_api_ip, pv_api_op);
5881 break;
5882
5883 case ISVCE_CMD_RETRIEVE_MEMREC:
5884 ret = isvce_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op);
5885 break;
5886
5887 case ISVCE_CMD_VIDEO_CTL:
5888 ret = isvce_ctl(ps_handle, pv_api_ip, pv_api_op, e_ctl_cmd);
5889 break;
5890
5891 case ISVCE_CMD_VIDEO_ENCODE:
5892 ret = isvce_encode(ps_handle, pv_api_ip, pv_api_op);
5893 break;
5894
5895 default:
5896 ret = IV_FAIL;
5897 break;
5898 }
5899
5900 return (IV_STATUS_T) ret;
5901 }
5902