xref: /aosp_15_r20/external/llvm/test/CodeGen/X86/vec_set-D.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
3
4define <4 x i32> @t(i32 %x, i32 %y) nounwind  {
5; CHECK-LABEL: t:
6; CHECK:       # BB#0:
7; CHECK-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
8; CHECK-NEXT:    retl
9  %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
10  %tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
11  ret <4 x i32> %tmp2
12}
13