xref: /aosp_15_r20/external/llvm/test/CodeGen/X86/vec_shift7.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
4
5; Verify that we don't fail when shift by zero is encountered.
6
7define i64 @test1(<2 x i64> %a) {
8; X32-LABEL: test1:
9; X32:       # BB#0: # %entry
10; X32-NEXT:    movdqa %xmm0, %xmm1
11; X32-NEXT:    psllq $2, %xmm1
12; X32-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
13; X32-NEXT:    movd %xmm1, %eax
14; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
15; X32-NEXT:    movd %xmm0, %edx
16; X32-NEXT:    retl
17;
18; X64-LABEL: test1:
19; X64:       # BB#0: # %entry
20; X64-NEXT:    movdqa %xmm0, %xmm1
21; X64-NEXT:    psllq $2, %xmm1
22; X64-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
23; X64-NEXT:    movd %xmm1, %rax
24; X64-NEXT:    retq
25entry:
26 %c = shl <2 x i64> %a, <i64 0, i64 2>
27 %d = extractelement <2 x i64> %c, i32 0
28 ret i64 %d
29}
30