1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_PM4_H 8 #define AC_PM4_H 9 10 #include "ac_gpu_info.h" 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 struct ac_pm4_state { 17 const struct radeon_info *info; 18 19 /* PKT3_SET_*_REG handling */ 20 uint16_t last_reg; /* register offset in dwords */ 21 uint16_t last_pm4; 22 uint16_t ndw; /* number of dwords in pm4 */ 23 uint8_t last_opcode; 24 uint8_t last_idx; 25 bool is_compute_queue; 26 bool packed_is_padded; /* whether SET_*_REG_PAIRS_PACKED is padded to an even number of regs */ 27 28 /* commands for the DE */ 29 uint16_t max_dw; 30 31 /* Used by SQTT to override the shader address */ 32 bool debug_sqtt; 33 uint32_t spi_shader_pgm_lo_reg; 34 35 /* This must be the last field because the array can continue after the structure. */ 36 uint32_t pm4[64]; 37 }; 38 39 void 40 ac_pm4_set_reg(struct ac_pm4_state *state, unsigned reg, uint32_t val); 41 42 void 43 ac_pm4_set_reg_custom(struct ac_pm4_state *state, unsigned reg, uint32_t val, 44 unsigned opcode, unsigned idx); 45 46 void 47 ac_pm4_set_reg_idx3(struct ac_pm4_state *state, unsigned reg, uint32_t val); 48 49 void 50 ac_pm4_clear_state(struct ac_pm4_state *state, const struct radeon_info *info, 51 bool debug_sqtt, bool is_compute_queue); 52 53 void 54 ac_pm4_cmd_begin(struct ac_pm4_state *state, unsigned opcode); 55 56 void 57 ac_pm4_cmd_add(struct ac_pm4_state *state, uint32_t dw); 58 59 void 60 ac_pm4_cmd_end(struct ac_pm4_state *state, bool predicate); 61 62 void 63 ac_pm4_finalize(struct ac_pm4_state *state); 64 65 struct ac_pm4_state * 66 ac_pm4_create_sized(const struct radeon_info *info, bool debug_sqtt, 67 unsigned max_dw, bool is_compute_queue); 68 69 void 70 ac_pm4_free_state(struct ac_pm4_state *state); 71 72 #ifdef __cplusplus 73 } 74 #endif 75 76 #endif 77