1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * Copyright 2020 Valve Corporation 4 * 5 * SPDX-License-Identifier: MIT 6 */ 7 8 #ifndef AC_RGP_H 9 #define AC_RGP_H 10 11 #include <stdint.h> 12 #include "compiler/shader_enums.h" 13 #include "util/list.h" 14 #include "util/simple_mtx.h" 15 16 struct radeon_info; 17 struct ac_sqtt_trace; 18 struct ac_sqtt; 19 struct ac_spm_trace; 20 21 enum rgp_hardware_stages { 22 RGP_HW_STAGE_VS = 0, 23 RGP_HW_STAGE_LS, 24 RGP_HW_STAGE_HS, 25 RGP_HW_STAGE_ES, 26 RGP_HW_STAGE_GS, 27 RGP_HW_STAGE_PS, 28 RGP_HW_STAGE_CS, 29 RGP_HW_STAGE_MAX, 30 }; 31 32 struct rgp_shader_data { 33 uint64_t hash[2]; 34 uint32_t code_size; 35 uint8_t *code; 36 uint32_t vgpr_count; 37 uint32_t sgpr_count; 38 uint32_t scratch_memory_size; 39 uint32_t lds_size; 40 uint32_t wavefront_size; 41 uint64_t base_address; 42 uint32_t elf_symbol_offset; 43 uint32_t hw_stage; 44 uint32_t is_combined; 45 char rt_shader_name[32]; 46 uint32_t rt_stack_size; 47 }; 48 49 struct rgp_code_object_record { 50 uint32_t shader_stages_mask; 51 struct rgp_shader_data shader_data[MESA_VULKAN_SHADER_STAGES]; 52 uint32_t num_shaders_combined; /* count combined shaders as one count */ 53 uint64_t pipeline_hash[2]; 54 55 bool is_rt; 56 struct list_head list; 57 }; 58 59 struct rgp_code_object { 60 uint32_t record_count; 61 struct list_head record; 62 simple_mtx_t lock; 63 }; 64 65 enum rgp_loader_event_type 66 { 67 RGP_LOAD_TO_GPU_MEMORY = 0, 68 RGP_UNLOAD_FROM_GPU_MEMORY, 69 }; 70 71 struct rgp_loader_events_record { 72 uint32_t loader_event_type; 73 uint32_t reserved; 74 uint64_t base_address; 75 uint64_t code_object_hash[2]; 76 uint64_t time_stamp; 77 struct list_head list; 78 }; 79 80 struct rgp_loader_events { 81 uint32_t record_count; 82 struct list_head record; 83 simple_mtx_t lock; 84 }; 85 86 struct rgp_pso_correlation_record { 87 uint64_t api_pso_hash; 88 uint64_t pipeline_hash[2]; 89 char api_level_obj_name[64]; 90 struct list_head list; 91 }; 92 93 struct rgp_pso_correlation { 94 uint32_t record_count; 95 struct list_head record; 96 simple_mtx_t lock; 97 }; 98 99 enum sqtt_queue_type { 100 SQTT_QUEUE_TYPE_UNKNOWN = 0x0, 101 SQTT_QUEUE_TYPE_UNIVERSAL = 0x1, 102 SQTT_QUEUE_TYPE_COMPUTE = 0x2, 103 SQTT_QUEUE_TYPE_DMA = 0x3, 104 }; 105 106 enum sqtt_engine_type { 107 SQTT_ENGINE_TYPE_UNKNOWN = 0x0, 108 SQTT_ENGINE_TYPE_UNIVERSAL = 0x1, 109 SQTT_ENGINE_TYPE_COMPUTE = 0x2, 110 SQTT_ENGINE_TYPE_EXCLUSIVE_COMPUTE = 0x3, 111 SQTT_ENGINE_TYPE_DMA = 0x4, 112 SQTT_ENGINE_TYPE_HIGH_PRIORITY_UNIVERSAL = 0x7, 113 SQTT_ENGINE_TYPE_HIGH_PRIORITY_GRAPHICS = 0x8, 114 }; 115 116 struct sqtt_queue_hardware_info { 117 union { 118 struct { 119 enum sqtt_queue_type queue_type : 8; 120 enum sqtt_engine_type engine_type : 8; 121 uint32_t reserved : 16; 122 }; 123 uint32_t value; 124 }; 125 }; 126 127 struct rgp_queue_info_record { 128 uint64_t queue_id; 129 uint64_t queue_context; 130 struct sqtt_queue_hardware_info hardware_info; 131 uint32_t reserved; 132 struct list_head list; 133 }; 134 135 struct rgp_queue_info { 136 uint32_t record_count; 137 struct list_head record; 138 simple_mtx_t lock; 139 }; 140 141 enum sqtt_queue_event_type { 142 SQTT_QUEUE_TIMING_EVENT_CMDBUF_SUBMIT, 143 SQTT_QUEUE_TIMING_EVENT_SIGNAL_SEMAPHORE, 144 SQTT_QUEUE_TIMING_EVENT_WAIT_SEMAPHORE, 145 SQTT_QUEUE_TIMING_EVENT_PRESENT 146 }; 147 148 struct rgp_queue_event_record { 149 enum sqtt_queue_event_type event_type; 150 uint32_t sqtt_cb_id; 151 uint64_t frame_index; 152 uint32_t queue_info_index; 153 uint32_t submit_sub_index; 154 uint64_t api_id; 155 uint64_t cpu_timestamp; 156 uint64_t *gpu_timestamps[2]; 157 struct list_head list; 158 }; 159 160 struct rgp_queue_event { 161 uint32_t record_count; 162 struct list_head record; 163 simple_mtx_t lock; 164 }; 165 166 struct rgp_clock_calibration_record { 167 uint64_t cpu_timestamp; 168 uint64_t gpu_timestamp; 169 struct list_head list; 170 }; 171 172 struct rgp_clock_calibration { 173 uint32_t record_count; 174 struct list_head record; 175 simple_mtx_t lock; 176 }; 177 178 int ac_dump_rgp_capture(const struct radeon_info *info, struct ac_sqtt_trace *sqtt_trace, 179 const struct ac_spm_trace *spm_trace); 180 181 void 182 ac_rgp_file_write_elf_object(FILE *output, size_t file_elf_start, 183 struct rgp_code_object_record *record, 184 uint32_t *written_size, uint32_t flags); 185 186 #endif 187