1 /* 2 * Copyright 2021 Valve Corporation 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_SPM_H 8 #define AC_SPM_H 9 10 #include <stdint.h> 11 12 #include "ac_perfcounter.h" 13 14 #define AC_SPM_MAX_COUNTER_PER_BLOCK 16 15 #define AC_SPM_GLOBAL_TIMESTAMP_COUNTERS 4 /* in unit of 16-bit counters*/ 16 #define AC_SPM_NUM_COUNTER_PER_MUXSEL 16 /* 16 16-bit counters per muxsel */ 17 #define AC_SPM_MUXSEL_LINE_SIZE ((AC_SPM_NUM_COUNTER_PER_MUXSEL * 2) / 4) /* in dwords */ 18 #define AC_SPM_NUM_PERF_SEL 4 19 20 /* GFX10+ */ 21 enum ac_spm_global_block { 22 AC_SPM_GLOBAL_BLOCK_CPG, 23 AC_SPM_GLOBAL_BLOCK_CPC, 24 AC_SPM_GLOBAL_BLOCK_CPF, 25 AC_SPM_GLOBAL_BLOCK_GDS, 26 AC_SPM_GLOBAL_BLOCK_GCR, 27 AC_SPM_GLOBAL_BLOCK_PH, 28 AC_SPM_GLOBAL_BLOCK_GE, 29 AC_SPM_GLOBAL_BLOCK_GE1 = AC_SPM_GLOBAL_BLOCK_GE, 30 AC_SPM_GLOBAL_BLOCK_GL2A, 31 AC_SPM_GLOBAL_BLOCK_GL2C, 32 AC_SPM_GLOBAL_BLOCK_SDMA, 33 AC_SPM_GLOBAL_BLOCK_GUS, 34 AC_SPM_GLOBAL_BLOCK_EA, 35 AC_SPM_GLOBAL_BLOCK_CHA, 36 AC_SPM_GLOBAL_BLOCK_CHC, 37 AC_SPM_GLOBAL_BLOCK_CHCG, 38 AC_SPM_GLOBAL_BLOCK_GPUVMATTCL2, 39 AC_SPM_GLOBAL_BLOCK_GPUVMVML2, 40 AC_SPM_GLOBAL_BLOCK_GE2SE, /* Per-SE counters */ 41 AC_SPM_GLOBAL_BLOCK_GE2DIST, 42 43 /* GFX11+ */ 44 /* gap */ 45 AC_SPM_GLOBAL_BLOCK_RSPM = 31, 46 }; 47 48 enum ac_spm_se_block { 49 AC_SPM_SE_BLOCK_CB, 50 AC_SPM_SE_BLOCK_DB, 51 AC_SPM_SE_BLOCK_PA, 52 AC_SPM_SE_BLOCK_SX, 53 AC_SPM_SE_BLOCK_SC, 54 AC_SPM_SE_BLOCK_TA, 55 AC_SPM_SE_BLOCK_TD, 56 AC_SPM_SE_BLOCK_TCP, 57 AC_SPM_SE_BLOCK_SPI, 58 AC_SPM_SE_BLOCK_SQG, 59 AC_SPM_SE_BLOCK_GL1A, 60 AC_SPM_SE_BLOCK_RMI, 61 AC_SPM_SE_BLOCK_GL1C, 62 AC_SPM_SE_BLOCK_GL1CG, 63 64 /* GFX11+ */ 65 AC_SPM_SE_BLOCK_CBR, 66 AC_SPM_SE_BLOCK_DBR, 67 AC_SPM_SE_BLOCK_GL1H, 68 AC_SPM_SE_BLOCK_SQC, 69 AC_SPM_SE_BLOCK_PC, 70 /* gap */ 71 AC_SPM_SE_BLOCK_SE_RPM = 31, 72 }; 73 74 enum ac_spm_segment_type { 75 AC_SPM_SEGMENT_TYPE_SE0, 76 AC_SPM_SEGMENT_TYPE_SE1, 77 AC_SPM_SEGMENT_TYPE_SE2, 78 AC_SPM_SEGMENT_TYPE_SE3, 79 AC_SPM_SEGMENT_TYPE_SE4, 80 AC_SPM_SEGMENT_TYPE_SE5, 81 AC_SPM_SEGMENT_TYPE_GLOBAL, 82 AC_SPM_SEGMENT_TYPE_COUNT, 83 }; 84 85 struct ac_spm_counter_descr { 86 enum ac_pc_gpu_block gpu_block; 87 uint32_t event_id; 88 }; 89 90 struct ac_spm_counter_create_info { 91 struct ac_spm_counter_descr *b; 92 uint32_t instance; 93 }; 94 95 union ac_spm_muxsel { 96 struct { 97 uint16_t counter : 6; 98 uint16_t block : 4; 99 uint16_t shader_array : 1; /* 0: SA0, 1: SA1 */ 100 uint16_t instance : 5; 101 } gfx10; 102 103 struct { 104 uint16_t counter : 5; 105 uint16_t instance : 5; 106 uint16_t shader_array : 1; 107 uint16_t block : 5; 108 } gfx11; 109 uint16_t value; 110 }; 111 112 struct ac_spm_muxsel_line { 113 union ac_spm_muxsel muxsel[AC_SPM_NUM_COUNTER_PER_MUXSEL]; 114 }; 115 116 struct ac_spm_counter_info { 117 /* General info. */ 118 enum ac_pc_gpu_block gpu_block; 119 uint32_t instance; 120 uint32_t event_id; 121 122 /* Muxsel info. */ 123 enum ac_spm_segment_type segment_type; 124 bool is_even; 125 union ac_spm_muxsel muxsel; 126 127 /* Output info. */ 128 uint64_t offset; 129 }; 130 131 struct ac_spm_counter_select { 132 uint8_t active; /* mask of used 16-bit counters. */ 133 uint32_t sel0; 134 uint32_t sel1; 135 }; 136 137 struct ac_spm_block_instance { 138 uint32_t grbm_gfx_index; 139 140 uint32_t num_counters; 141 struct ac_spm_counter_select counters[AC_SPM_MAX_COUNTER_PER_BLOCK]; 142 }; 143 144 struct ac_spm_block_select { 145 const struct ac_pc_block *b; 146 147 uint32_t num_instances; 148 struct ac_spm_block_instance *instances; 149 }; 150 151 struct ac_spm { 152 /* struct radeon_winsys_bo or struct pb_buffer */ 153 void *bo; 154 void *ptr; 155 uint8_t ptr_granularity; 156 uint32_t buffer_size; 157 uint16_t sample_interval; 158 159 /* Enabled counters. */ 160 unsigned num_counters; 161 struct ac_spm_counter_info *counters; 162 163 /* Block/counters selection. */ 164 uint32_t num_block_sel; 165 struct ac_spm_block_select *block_sel; 166 167 struct { 168 uint32_t num_counters; 169 struct ac_spm_counter_select counters[16]; 170 } sqg[AC_SPM_SEGMENT_TYPE_GLOBAL]; 171 172 struct { 173 uint32_t grbm_gfx_index; 174 uint32_t num_counters; 175 struct ac_spm_counter_select counters[16]; 176 } sq_wgp[AMD_MAX_WGP]; 177 178 /* Muxsel lines. */ 179 unsigned num_muxsel_lines[AC_SPM_SEGMENT_TYPE_COUNT]; 180 struct ac_spm_muxsel_line *muxsel_lines[AC_SPM_SEGMENT_TYPE_COUNT]; 181 unsigned max_se_muxsel_lines; 182 }; 183 184 struct ac_spm_trace { 185 void *ptr; 186 uint16_t sample_interval; 187 unsigned num_counters; 188 struct ac_spm_counter_info *counters; 189 uint32_t sample_size_in_bytes; 190 uint32_t num_samples; 191 }; 192 193 bool ac_init_spm(const struct radeon_info *info, 194 const struct ac_perfcounters *pc, 195 struct ac_spm *spm); 196 void ac_destroy_spm(struct ac_spm *spm); 197 198 void ac_spm_get_trace(const struct ac_spm *spm, struct ac_spm_trace *trace); 199 200 #endif 201