1 /* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright © 2015 Intel Corporation 7 * 8 * SPDX-License-Identifier: MIT 9 */ 10 #ifndef ACO_SHADER_INFO_H 11 #define ACO_SHADER_INFO_H 12 13 #include "ac_hw_stage.h" 14 #include "ac_shader_args.h" 15 #include "amd_family.h" 16 #include "shader_enums.h" 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #define ACO_MAX_SO_OUTPUTS 128 23 #define ACO_MAX_SO_BUFFERS 4 24 #define ACO_MAX_VERTEX_ATTRIBS 32 25 #define ACO_MAX_VBS 32 26 27 struct aco_vs_prolog_info { 28 struct ac_arg inputs; 29 30 uint32_t instance_rate_inputs; 31 uint32_t nontrivial_divisors; 32 uint32_t zero_divisors; 33 uint32_t post_shuffle; 34 /* Having two separate fields instead of a single uint64_t makes it easier to remove attributes 35 * using bitwise arithmetic. 36 */ 37 uint32_t alpha_adjust_lo; 38 uint32_t alpha_adjust_hi; 39 40 uint8_t formats[ACO_MAX_VERTEX_ATTRIBS]; 41 42 unsigned num_attributes; 43 uint32_t misaligned_mask; 44 uint32_t unaligned_mask; 45 bool is_ngg; 46 gl_shader_stage next_stage; 47 }; 48 49 struct aco_ps_epilog_info { 50 struct ac_arg colors[MAX_DRAW_BUFFERS]; 51 uint8_t color_map[MAX_DRAW_BUFFERS]; 52 53 uint32_t spi_shader_col_format; 54 55 /* Bitmasks, each bit represents one of the 8 MRTs. */ 56 uint8_t color_is_int8; 57 uint8_t color_is_int10; 58 59 bool mrt0_is_dual_src; 60 61 bool alpha_to_coverage_via_mrtz; 62 bool alpha_to_one; 63 64 /* OpenGL only */ 65 uint16_t color_types; 66 bool clamp_color; 67 bool skip_null_export; 68 unsigned broadcast_last_cbuf; 69 enum compare_func alpha_func; 70 struct ac_arg alpha_reference; 71 struct ac_arg depth; 72 struct ac_arg stencil; 73 struct ac_arg samplemask; 74 }; 75 76 struct aco_ps_prolog_info { 77 bool poly_stipple; 78 unsigned poly_stipple_buf_offset; 79 80 bool bc_optimize_for_persp; 81 bool bc_optimize_for_linear; 82 bool force_persp_sample_interp; 83 bool force_linear_sample_interp; 84 bool force_persp_center_interp; 85 bool force_linear_center_interp; 86 87 unsigned samplemask_log_ps_iter; 88 unsigned num_interp_inputs; 89 unsigned colors_read; 90 int color_interp_vgpr_index[2]; 91 int color_attr_index[2]; 92 bool color_two_side; 93 bool needs_wqm; 94 95 struct ac_arg internal_bindings; 96 }; 97 98 struct aco_shader_info { 99 enum ac_hw_stage hw_stage; 100 uint8_t wave_size; 101 bool has_ngg_culling; 102 bool has_ngg_early_prim_export; 103 bool image_2d_view_of_3d; 104 unsigned workgroup_size; 105 bool merged_shader_compiled_separately; /* GFX9+ */ 106 struct ac_arg next_stage_pc; 107 struct ac_arg epilog_pc; /* Vulkan only */ 108 struct { 109 bool tcs_in_out_eq; 110 uint64_t tcs_temp_only_input_mask; 111 bool has_prolog; 112 } vs; 113 struct { 114 struct ac_arg tcs_offchip_layout; 115 116 /* Vulkan only */ 117 uint32_t num_lds_blocks; 118 119 /* OpenGL only */ 120 bool pass_tessfactors_by_reg; 121 unsigned patch_stride; 122 struct ac_arg tes_offchip_addr; 123 struct ac_arg vs_state_bits; 124 } tcs; 125 struct { 126 uint32_t num_interp; 127 unsigned spi_ps_input_ena; 128 unsigned spi_ps_input_addr; 129 bool has_epilog; 130 131 /* OpenGL only */ 132 struct ac_arg alpha_reference; 133 } ps; 134 struct { 135 bool uses_full_subgroups; 136 } cs; 137 138 uint32_t gfx9_gs_ring_lds_size; 139 140 bool is_trap_handler_shader; 141 }; 142 143 enum aco_compiler_debug_level { 144 ACO_COMPILER_DEBUG_LEVEL_ERROR, 145 }; 146 147 struct aco_compiler_options { 148 bool dump_shader; 149 bool dump_preoptir; 150 bool record_ir; 151 bool record_stats; 152 bool has_ls_vgpr_init_bug; 153 bool load_grid_size_from_user_sgpr; 154 bool optimisations_disabled; 155 uint8_t enable_mrt_output_nan_fixup; 156 bool wgp_mode; 157 bool is_opengl; 158 enum radeon_family family; 159 enum amd_gfx_level gfx_level; 160 uint32_t address32_hi; 161 struct { 162 void (*func)(void* private_data, enum aco_compiler_debug_level level, const char* message); 163 void* private_data; 164 } debug; 165 }; 166 167 enum aco_statistic { 168 aco_statistic_hash, 169 aco_statistic_instructions, 170 aco_statistic_copies, 171 aco_statistic_branches, 172 aco_statistic_latency, 173 aco_statistic_inv_throughput, 174 aco_statistic_vmem_clauses, 175 aco_statistic_smem_clauses, 176 aco_statistic_sgpr_presched, 177 aco_statistic_vgpr_presched, 178 aco_statistic_valu, 179 aco_statistic_salu, 180 aco_statistic_vmem, 181 aco_statistic_smem, 182 aco_statistic_vopd, 183 aco_num_statistics 184 }; 185 186 enum aco_symbol_id { 187 aco_symbol_invalid, 188 aco_symbol_scratch_addr_lo, 189 aco_symbol_scratch_addr_hi, 190 aco_symbol_lds_ngg_scratch_base, 191 aco_symbol_lds_ngg_gs_out_vertex_base, 192 aco_symbol_const_data_addr, 193 }; 194 195 struct aco_symbol { 196 enum aco_symbol_id id; 197 unsigned offset; 198 }; 199 200 #ifdef __cplusplus 201 } 202 #endif 203 #endif 204