1 /* 2 * Copyright © 2023 Raspberry Pi Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef V3D_PERFORMANCE_COUNTERS_H 25 #define V3D_PERFORMANCE_COUNTERS_H 26 27 #define V3D_PERFCNT_CATEGORY 0 28 #define V3D_PERFCNT_NAME 1 29 #define V3D_PERFCNT_DESCRIPTION 2 30 31 #ifndef V3D_VERSION 32 # error "The V3D_VERSION macro must be defined" 33 #endif 34 35 #if (V3D_VERSION >= 71) 36 37 static const char *v3d_performance_counters[][3] = { 38 {"CORE", "cycle-count", "[CORE] Cycle counter"}, 39 {"CORE", "core-active", "[CORE] Bin/Render/Compute active cycles"}, 40 {"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"}, 41 {"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"}, 42 {"CORE", "compute-active-cycles", "[CORE] Compute active cycles"}, 43 {"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rendered pixels, for all rendered tiles"}, 44 {"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (primitives may be counted in more than one tile)"}, 45 {"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"}, 46 {"FEP", "FEP-valid-quads", "[FEP] Valid quads"}, 47 {"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test"}, 48 {"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and stencil tests"}, 49 {"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and stencil tests"}, 50 {"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buffer"}, 51 {"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour buffer"}, 52 {"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"}, 53 {"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside the viewport"}, 54 {"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"}, 55 {"PTB", "PTB-primitives-discarded-reversed", "[PTB] Primitives that are discarded because they are reversed"}, 56 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"}, 57 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"}, 58 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"}, 59 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"}, 60 {"TMU", "TMU-active-cycles", "[TMU] Active cycles"}, 61 {"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"}, 62 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"}, 63 {"TMU", "TMU-cache-x4-active-cycles", "[TMU] Cache active cycles for x4 access"}, 64 {"TMU", "TMU-cache-x4-stalled-cycles", "[TMU] Cache stalled cycles for x4 access"}, 65 {"TMU", "TMU-total-text-quads-x4-access", "[TMU] Total texture cache x4 access"}, 66 {"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"}, 67 {"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"}, 68 {"L2T", "L2T-local", "[L2T] Local mode access"}, 69 {"L2T", "L2T-writeback", "[L2T] Writeback"}, 70 {"L2T", "L2T-zero", "[L2T] Zero"}, 71 {"L2T", "L2T-merge", "[L2T] Merge"}, 72 {"L2T", "L2T-fill", "[L2T] Fill"}, 73 {"L2T", "L2T-stalls-no-wid", "[L2T] Stalls because no WID available"}, 74 {"L2T", "L2T-stalls-no-rid", "[L2T] Stalls because no RID available"}, 75 {"L2T", "L2T-stalls-queue-full", "[L2T] Stalls because internal queue full"}, 76 {"L2T", "L2T-stalls-wrightback", "[L2T] Stalls because writeback in flight"}, 77 {"L2T", "L2T-stalls-mem", "[L2T] Stalls because AXI blocks read"}, 78 {"L2T", "L2T-stalls-fill", "[L2T] Stalls because fill pending for victim cache-line"}, 79 {"L2T", "L2T-hitq", "[L2T] Sent request via hit queue"}, 80 {"L2T", "L2T-hitq-full", "[L2T] Sent request via main queue because hit queue is full"}, 81 {"L2T", "L2T-stalls-read-data", "[L2T] Stalls because waiting for data from SDRAM"}, 82 {"L2T", "L2T-TMU-read-hits", "[L2T] TMU read hits"}, 83 {"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"}, 84 {"L2T", "L2T-VCD-read-hits", "[L2T] VCD read hits"}, 85 {"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"}, 86 {"L2T", "L2T-SLC-read-hits", "[L2T] SLC read hits (all slices)"}, 87 {"L2T", "L2T-SLC-read-miss", "[L2T] SLC read misses (all slices)"}, 88 {"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"}, 89 {"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"}, 90 {"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"}, 91 {"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"}, 92 {"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"}, 93 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"}, 94 {"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"}, 95 {"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"}, 96 {"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"}, 97 {"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"}, 98 {"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"}, 99 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"}, 100 {"CORE", "core-memory-writes", "[CORE] Total memory writes"}, 101 {"L2T", "L2T-memory-writes", "[L2T] Total memory writes"}, 102 {"PTB", "PTB-memory-writes", "[PTB] Total memory writes"}, 103 {"TLB", "TLB-memory-writes", "[TLB] Total memory writes"}, 104 {"CORE", "core-memory-reads", "[CORE] Total memory reads"}, 105 {"L2T", "L2T-memory-reads", "[L2T] Total memory reads"}, 106 {"PTB", "PTB-memory-reads", "[PTB] Total memory reads"}, 107 {"PSE", "PSE-memory-reads", "[PSE] Total memory reads"}, 108 {"TLB", "TLB-memory-reads", "[TLB] Total memory reads"}, 109 {"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"}, 110 {"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"}, 111 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"}, 112 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"}, 113 {"AXI", "AXI-read-trans", "[AXI] Read transaction count"}, 114 {"AXI", "AXI-write-trans", "[AXI] Write transaction count"}, 115 {"AXI", "AXI-read-wait-cycles", "[AXI] Read total wait cycles"}, 116 {"AXI", "AXI-write-wait-cycles", "[AXI] Write total wait cycles"}, 117 {"AXI", "AXI-max-outstanding-reads", "[AXI] Maximium outstanding read transactions"}, 118 {"AXI", "AXI-max-outstanding-writes", "[AXI] Maximum outstanding write transactions"}, 119 {"QPU", "QPU-wait-bubble", "[QPU] Pipeline bubble in qcycles due all threads waiting"}, 120 {"QPU", "QPU-ic-miss-bubble", "[QPU] Pipeline bubble in qcycles due instruction-cache miss"}, 121 {"QPU", "QPU-active", "[QPU] Executed shader instruction"}, 122 {"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all QPUs doing fragment shading (counts only when QPU is not stalled)"}, 123 {"QPU", "QPU-stalls", "[QPU] Stalled qcycles executing shader instruction"}, 124 {"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all QPUs doing fragment shading"}, 125 {"QPU", "QPU-stalls-TMU", "[QPU] Stalled qcycles waiting for TMU"}, 126 {"QPU", "QPU-stalls-TLB", "[QPU] Stalled qcycles waiting for TLB"}, 127 {"QPU", "QPU-stalls-VPM", "[QPU] Stalled qcycles waiting for VPM"}, 128 {"QPU", "QPU-stalls-uniforms", "[QPU] Stalled qcycles waiting for uniforms"}, 129 {"QPU", "QPU-stalls-SFU", "[QPU] Stalled qcycles waiting for SFU"}, 130 {"QPU", "QPU-stalls-other", "[QPU] Stalled qcycles waiting for any other reason (vary/W/Z)"}, 131 }; 132 133 #elif (V3D_VERSION >= 42) 134 135 static const char *v3d_performance_counters[][3] = { 136 {"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rendered pixels, for all rendered tiles"}, 137 {"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (primitives may be counted in more than one tile)"}, 138 {"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"}, 139 {"FEP", "FEP-valid-quads", "[FEP] Valid quads"}, 140 {"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test"}, 141 {"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and stencil tests"}, 142 {"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and stencil tests"}, 143 {"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"}, 144 {"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"}, 145 {"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buffer"}, 146 {"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside the viewport"}, 147 {"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"}, 148 {"PTB", "PTB-primitives-discarded-reversed", "[PTB] Primitives that are discarded because they are reversed"}, 149 {"QPU", "QPU-total-idle-clk-cycles", "[QPU] Total idle clock cycles for all QPUs"}, 150 {"QPU", "QPU-total-active-clk-cycles-vertex-coord-shading", "[QPU] Total active clock cycles for all QPUs doing vertex/coordinate/user shading (counts only when QPU is not stalled)"}, 151 {"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all QPUs doing fragment shading (counts only when QPU is not stalled)"}, 152 {"QPU", "QPU-total-clk-cycles-executing-valid-instr", "[QPU] Total clock cycles for all QPUs executing valid instructions"}, 153 {"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting for TMUs only (counter won't increment if QPU also stalling for another reason)"}, 154 {"QPU", "QPU-total-clk-cycles-waiting-scoreboard", "[QPU] Total clock cycles for all QPUs stalled waiting for Scoreboard only (counter won't increment if QPU also stalling for another reason)"}, 155 {"QPU", "QPU-total-clk-cycles-waiting-varyings", "[QPU] Total clock cycles for all QPUs stalled waiting for Varyings only (counter won't increment if QPU also stalling for another reason)"}, 156 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"}, 157 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"}, 158 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"}, 159 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"}, 160 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"}, 161 {"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from memory/L2cache)"}, 162 {"VPM", "VPM-total-clk-cycles-VDW-stalled", "[VPM] Total clock cycles VDW is stalled waiting for VPM access"}, 163 {"VPM", "VPM-total-clk-cycles-VCD-stalled", "[VPM] Total clock cycles VCD is stalled waiting for VPM access"}, 164 {"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"}, 165 {"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"}, 166 {"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"}, 167 {"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"}, 168 {"CORE", "cycle-count", "[CORE] Cycle counter"}, 169 {"QPU", "QPU-total-clk-cycles-waiting-vertex-coord-shading", "[QPU] Total stalled clock cycles for all QPUs doing vertex/coordinate/user shading"}, 170 {"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all QPUs doing fragment shading"}, 171 {"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"}, 172 {"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"}, 173 {"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"}, 174 {"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"}, 175 {"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"}, 176 {"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"}, 177 {"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"}, 178 {"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"}, 179 {"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"}, 180 {"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"}, 181 {"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"}, 182 {"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"}, 183 {"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"}, 184 {"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour buffer"}, 185 {"TMU", "TMU-total-config-access", "[TMU] Total config accesses"}, 186 {"L2T", "L2T-no-id-stalled", "[L2T] No ID stall"}, 187 {"L2T", "L2T-command-queue-stalled", "[L2T] Command queue full stall"}, 188 {"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"}, 189 {"TMU", "TMU-active-cycles", "[TMU] Active cycles"}, 190 {"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"}, 191 {"CLE", "CLE-thread-active-cycles", "[CLE] Bin or render thread active cycles"}, 192 {"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"}, 193 {"L2T", "L2T-CLE-reads", "[L2T] CLE read accesses"}, 194 {"L2T", "L2T-VCD-reads", "[L2T] VCD read accesses"}, 195 {"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"}, 196 {"L2T", "L2T-SLC0-reads", "[L2T] SLC0 read accesses"}, 197 {"L2T", "L2T-SLC1-reads", "[L2T] SLC1 read accesses"}, 198 {"L2T", "L2T-SLC2-reads", "[L2T] SLC2 read accesses"}, 199 {"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"}, 200 {"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"}, 201 {"L2T", "L2T-CLE-read-miss", "[L2T] CLE read misses"}, 202 {"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"}, 203 {"L2T", "L2T-TMU-config-read-miss", "[L2T] TMU CFG read misses"}, 204 {"L2T", "L2T-SLC0-read-miss", "[L2T] SLC0 read misses"}, 205 {"L2T", "L2T-SLC1-read-miss", "[L2T] SLC1 read misses"}, 206 {"L2T", "L2T-SLC2-read-miss", "[L2T] SLC2 read misses"}, 207 {"CORE", "core-memory-writes", "[CORE] Total memory writes"}, 208 {"L2T", "L2T-memory-writes", "[L2T] Total memory writes"}, 209 {"PTB", "PTB-memory-writes", "[PTB] Total memory writes"}, 210 {"TLB", "TLB-memory-writes", "[TLB] Total memory writes"}, 211 {"CORE", "core-memory-reads", "[CORE] Total memory reads"}, 212 {"L2T", "L2T-memory-reads", "[L2T] Total memory reads"}, 213 {"PTB", "PTB-memory-reads", "[PTB] Total memory reads"}, 214 {"PSE", "PSE-memory-reads", "[PSE] Total memory reads"}, 215 {"TLB", "TLB-memory-reads", "[TLB] Total memory reads"}, 216 {"GMP", "GMP-memory-reads", "[GMP] Total memory reads"}, 217 {"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"}, 218 {"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"}, 219 {"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"}, 220 {"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"}, 221 {"TMU", "TMU-MRU-hits", "[TMU] Total MRU hits"}, 222 {"CORE", "compute-active-cycles", "[CORE] Compute active cycles"}, 223 }; 224 225 #else 226 static const char *v3d_performance_counters[][3] = { }; 227 #endif 228 229 #endif 230