1 /*
2 * Copyright © 2021 Raspberry Pi Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "v3d_util.h"
25 #include "util/macros.h"
26
27 /* Choose a number of workgroups per supergroup that maximizes
28 * lane occupancy. We can pack up to 16 workgroups into a supergroup.
29 */
30 uint32_t
v3d_csd_choose_workgroups_per_supergroup(struct v3d_device_info * devinfo,bool has_subgroups,bool has_tsy_barrier,uint32_t threads,uint32_t num_wgs,uint32_t wg_size)31 v3d_csd_choose_workgroups_per_supergroup(struct v3d_device_info *devinfo,
32 bool has_subgroups,
33 bool has_tsy_barrier,
34 uint32_t threads,
35 uint32_t num_wgs,
36 uint32_t wg_size)
37 {
38 /* FIXME: subgroups may restrict supergroup packing. For now, we disable it
39 * completely if the shader uses subgroups.
40 */
41 if (has_subgroups)
42 return 1;
43
44 /* Compute maximum number of batches in a supergroup for this workgroup size.
45 * Each batch is 16 elements, and we can have up to 16 work groups in a
46 * supergroup:
47 *
48 * max_batches_per_sg = (wg_size * max_wgs_per_sg) / elements_per_batch
49 * since max_wgs_per_sg = 16 and elements_per_batch = 16, we get:
50 * max_batches_per_sg = wg_size
51 */
52 uint32_t max_batches_per_sg = wg_size;
53
54 /* QPU threads will stall at TSY barriers until the entire supergroup
55 * reaches the barrier. Limit the supergroup size to half the QPU threads
56 * available, so we can have at least 2 supergroups executing in parallel
57 * and we don't stall all our QPU threads when a supergroup hits a barrier.
58 */
59 if (has_tsy_barrier) {
60 uint32_t max_qpu_threads = devinfo->qpu_count * threads;
61 max_batches_per_sg = MIN2(max_batches_per_sg, max_qpu_threads / 2);
62 }
63 uint32_t max_wgs_per_sg = max_batches_per_sg * 16 / wg_size;
64
65 uint32_t best_wgs_per_sg = 1;
66 uint32_t best_unused_lanes = 16;
67 for (uint32_t wgs_per_sg = 1; wgs_per_sg <= max_wgs_per_sg; wgs_per_sg++) {
68 /* Don't try to pack more workgroups per supergroup than the total amount
69 * of workgroups dispatched.
70 */
71 if (wgs_per_sg > num_wgs)
72 return best_wgs_per_sg;
73
74 /* Compute wasted lines for this configuration and keep track of the
75 * config with less waste.
76 */
77 uint32_t unused_lanes = (16 - ((wgs_per_sg * wg_size) % 16)) & 0x0f;
78 if (unused_lanes == 0)
79 return wgs_per_sg;
80
81 if (unused_lanes < best_unused_lanes) {
82 best_wgs_per_sg = wgs_per_sg;
83 best_unused_lanes = unused_lanes;
84 }
85 }
86
87 return best_wgs_per_sg;
88 }
89
90 #define V3D71_TLB_COLOR_SIZE (16 * 1024)
91 #define V3D71_TLB_DETPH_SIZE (16 * 1024)
92 #define V3D71_TLB_AUX_DETPH_SIZE (8 * 1024)
93
94 static bool
tile_size_valid(uint32_t pixel_count,uint32_t color_bpp,uint32_t depth_bpp)95 tile_size_valid(uint32_t pixel_count, uint32_t color_bpp, uint32_t depth_bpp)
96 {
97 /* First, we check if we can fit this tile size allocating the depth
98 * TLB memory to color.
99 */
100 if (pixel_count * depth_bpp <= V3D71_TLB_AUX_DETPH_SIZE &&
101 pixel_count * color_bpp <= V3D71_TLB_COLOR_SIZE + V3D71_TLB_DETPH_SIZE) {
102 return true;
103 }
104
105 /* Otherwise the tile must fit in the main TLB buffers */
106 return pixel_count * depth_bpp <= V3D71_TLB_DETPH_SIZE &&
107 pixel_count * color_bpp <= V3D71_TLB_COLOR_SIZE;
108 }
109
110 void
v3d_choose_tile_size(const struct v3d_device_info * devinfo,uint32_t color_attachment_count,uint32_t max_internal_bpp,uint32_t total_color_bpp,bool msaa,bool double_buffer,uint32_t * width,uint32_t * height)111 v3d_choose_tile_size(const struct v3d_device_info *devinfo,
112 uint32_t color_attachment_count,
113 /* V3D 4.x max internal bpp of all RTs */
114 uint32_t max_internal_bpp,
115 /* V3D 7.x accumulated bpp for all RTs (in bytes) */
116 uint32_t total_color_bpp,
117 bool msaa,
118 bool double_buffer,
119 uint32_t *width,
120 uint32_t *height)
121 {
122 static const uint8_t tile_sizes[] = {
123 64, 64,
124 64, 32,
125 32, 32,
126 32, 16,
127 16, 16,
128 16, 8,
129 8, 8
130 };
131
132 uint32_t idx = 0;
133 if (devinfo->ver >= 71) {
134 /* In V3D 7.x, we use the actual bpp used by color attachments to compute
135 * the tile size instead of the maximum bpp. This may allow us to choose a
136 * larger tile size than we would in 4.x in scenarios with multiple RTs
137 * with different bpps.
138 *
139 * Also, the TLB has an auxiliary buffer of 8KB that will be automatically
140 * used for depth instead of the main 16KB depth TLB buffer when the depth
141 * tile fits in the auxiliary buffer, allowing the hardware to allocate
142 * the 16KB from the main depth TLB to the color TLB. If we can do that,
143 * then we are effectively doubling the memory we have for color and we
144 * can also select a larger tile size. This is necessary to support
145 * the most expensive configuration: 8x128bpp RTs + MSAA.
146 *
147 * FIXME: the docs state that depth TLB memory can be used for color
148 * if depth testing is not used by setting the 'depth disable' bit in the
149 * rendering configuration. However, this comes with a requirement that
150 * occlussion queries must not be active. We need to clarify if this means
151 * active at the point at which we emit a tile rendering configuration
152 * item, meaning that the we have a query spanning a full render pass
153 * (this is something we can tell before we emit the rendering
154 * configuration item) or active in the subpass for which we are enabling
155 * the bit (which we can't tell until later, when we record commands for
156 * the subpass). If it is the latter, then we cannot use this feature.
157 *
158 * FIXME: pending handling double_buffer.
159 */
160 const uint32_t color_bpp = total_color_bpp * (msaa ? 4 : 1);
161 const uint32_t depth_bpp = 4 * (msaa ? 4 : 1);
162 do {
163 const uint32_t tile_w = tile_sizes[idx * 2];
164 const uint32_t tile_h = tile_sizes[idx * 2 + 1];
165 if (tile_size_valid(tile_w * tile_h, color_bpp, depth_bpp))
166 break;
167 idx++;
168 } while (idx < ARRAY_SIZE(tile_sizes) / 2);
169
170 /* FIXME: pending handling double_buffer */
171 assert(!double_buffer);
172 } else {
173 /* On V3D 4.x tile size is selected based on the number of RTs, the
174 * maximum bpp across all of them and whether 4x MSAA is used.
175 */
176 if (color_attachment_count > 4)
177 idx += 3;
178 else if (color_attachment_count > 2)
179 idx += 2;
180 else if (color_attachment_count > 1)
181 idx += 1;
182
183 /* MSAA and double-buffer are mutually exclusive */
184 assert(!msaa || !double_buffer);
185 if (msaa)
186 idx += 2;
187 else if (double_buffer)
188 idx += 1;
189
190 idx += max_internal_bpp;
191 }
192
193 assert(idx < ARRAY_SIZE(tile_sizes) / 2);
194
195 *width = tile_sizes[idx * 2];
196 *height = tile_sizes[idx * 2 + 1];
197 }
198
199 /* Translates a pipe swizzle to the swizzle values used in the
200 * TEXTURE_SHADER_STATE packet.
201 */
202 uint32_t
v3d_translate_pipe_swizzle(enum pipe_swizzle swizzle)203 v3d_translate_pipe_swizzle(enum pipe_swizzle swizzle)
204 {
205 switch (swizzle) {
206 case PIPE_SWIZZLE_0:
207 return 0;
208 case PIPE_SWIZZLE_1:
209 return 1;
210 case PIPE_SWIZZLE_X:
211 case PIPE_SWIZZLE_Y:
212 case PIPE_SWIZZLE_Z:
213 case PIPE_SWIZZLE_W:
214 return 2 + swizzle;
215 default:
216 unreachable("unknown swizzle");
217 }
218 }
219
220 /* Translates a pipe primitive type to a hw value we can use in the various
221 * draw packets.
222 */
223 uint32_t
v3d_hw_prim_type(enum mesa_prim prim_type)224 v3d_hw_prim_type(enum mesa_prim prim_type)
225 {
226 switch (prim_type) {
227 case MESA_PRIM_POINTS:
228 case MESA_PRIM_LINES:
229 case MESA_PRIM_LINE_LOOP:
230 case MESA_PRIM_LINE_STRIP:
231 case MESA_PRIM_TRIANGLES:
232 case MESA_PRIM_TRIANGLE_STRIP:
233 case MESA_PRIM_TRIANGLE_FAN:
234 return prim_type;
235
236 case MESA_PRIM_LINES_ADJACENCY:
237 case MESA_PRIM_LINE_STRIP_ADJACENCY:
238 case MESA_PRIM_TRIANGLES_ADJACENCY:
239 case MESA_PRIM_TRIANGLE_STRIP_ADJACENCY:
240 return 8 + (prim_type - MESA_PRIM_LINES_ADJACENCY);
241
242 default:
243 unreachable("Unsupported primitive type");
244 }
245 }
246
247 uint32_t
v3d_internal_bpp_words(uint32_t internal_bpp)248 v3d_internal_bpp_words(uint32_t internal_bpp)
249 {
250 switch (internal_bpp) {
251 case 0 /* V3D_INTERNAL_BPP_32 */:
252 return 1;
253 case 1 /* V3D_INTERNAL_BPP_64 */:
254 return 2;
255 case 2 /* V3D_INTERNAL_BPP_128 */:
256 return 4;
257 default:
258 unreachable("Unsupported internal BPP");
259 }
260 }
261
262 uint32_t
v3d_compute_rt_row_row_stride_128_bits(uint32_t tile_width,uint32_t bpp)263 v3d_compute_rt_row_row_stride_128_bits(uint32_t tile_width,
264 uint32_t bpp)
265 {
266 /* stride in multiples of 128 bits, and covers 2 rows. This is the
267 * reason we divide by 2 instead of 4, as we divide number of 32-bit
268 * words per row by 2.
269 */
270
271 return (tile_width * bpp) / 2;
272 }
273