1 /*
2 * Copyright © 2020 Google, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "nir.h"
25 #include "nir_builder.h"
26
27 /* A pass to split intrinsics with discontinuous writemasks into ones
28 * with contiguous writemasks starting with .x, ie:
29 *
30 * vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
31 * intrinsic store_ssbo (ssa_76, ssa_105, ssa_106) (2, 0, 4, 0) // wrmask=y
32 *
33 * is turned into:
34 *
35 * vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
36 * vec1 32 ssa_107 = load_const (0x00000001)
37 * vec1 32 ssa_108 = iadd ssa_106, ssa_107
38 * vec1 32 ssa_109 = mov ssa_76.y
39 * intrinsic store_ssbo (ssa_109, ssa_105, ssa_108) (1, 0, 4, 0) // wrmask=x
40 *
41 * and likewise:
42 *
43 * vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
44 * intrinsic store_ssbo (ssa_76, ssa_105, ssa_106) (15, 0, 4, 0) // wrmask=xzw
45 *
46 * is split into:
47 *
48 * // .x component:
49 * vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
50 * vec1 32 ssa_107 = load_const (0x00000000)
51 * vec1 32 ssa_108 = iadd ssa_106, ssa_107
52 * vec1 32 ssa_109 = mov ssa_76.x
53 * intrinsic store_ssbo (ssa_109, ssa_105, ssa_108) (1, 0, 4, 0) // wrmask=x
54 * // .zw components:
55 * vec1 32 ssa_110 = load_const (0x00000002)
56 * vec1 32 ssa_111 = iadd ssa_106, ssa_110
57 * vec2 32 ssa_112 = mov ssa_76.zw
58 * intrinsic store_ssbo (ssa_112, ssa_105, ssa_111) (3, 0, 4, 0) // wrmask=xy
59 */
60
61 static int
value_src(nir_intrinsic_op intrinsic)62 value_src(nir_intrinsic_op intrinsic)
63 {
64 switch (intrinsic) {
65 case nir_intrinsic_store_output:
66 case nir_intrinsic_store_per_vertex_output:
67 case nir_intrinsic_store_ssbo:
68 case nir_intrinsic_store_shared:
69 case nir_intrinsic_store_global:
70 case nir_intrinsic_store_scratch:
71 return 0;
72 default:
73 return -1;
74 }
75 }
76
77 static int
offset_src(nir_intrinsic_op intrinsic)78 offset_src(nir_intrinsic_op intrinsic)
79 {
80 switch (intrinsic) {
81 case nir_intrinsic_store_output:
82 case nir_intrinsic_store_shared:
83 case nir_intrinsic_store_global:
84 case nir_intrinsic_store_scratch:
85 return 1;
86 case nir_intrinsic_store_per_vertex_output:
87 case nir_intrinsic_store_ssbo:
88 return 2;
89 default:
90 return -1;
91 }
92 }
93
94 static void
split_wrmask(nir_builder * b,nir_intrinsic_instr * intr)95 split_wrmask(nir_builder *b, nir_intrinsic_instr *intr)
96 {
97 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
98
99 b->cursor = nir_before_instr(&intr->instr);
100
101 assert(!info->has_dest); /* expecting only store intrinsics */
102
103 unsigned num_srcs = info->num_srcs;
104 unsigned value_idx = value_src(intr->intrinsic);
105 unsigned offset_idx = offset_src(intr->intrinsic);
106
107 unsigned wrmask = nir_intrinsic_write_mask(intr);
108 while (wrmask) {
109 unsigned first_component = ffs(wrmask) - 1;
110 unsigned length = ffs(~(wrmask >> first_component)) - 1;
111
112 nir_def *value = intr->src[value_idx].ssa;
113 nir_def *offset = intr->src[offset_idx].ssa;
114
115 /* swizzle out the consecutive components that we'll store
116 * in this iteration:
117 */
118 unsigned cur_mask = (BITFIELD_MASK(length) << first_component);
119 value = nir_channels(b, value, cur_mask);
120
121 /* and create the replacement intrinsic: */
122 nir_intrinsic_instr *new_intr =
123 nir_intrinsic_instr_create(b->shader, intr->intrinsic);
124
125 nir_intrinsic_copy_const_indices(new_intr, intr);
126 nir_intrinsic_set_write_mask(new_intr, BITFIELD_MASK(length));
127
128 const int offset_units = value->bit_size / 8;
129
130 if (nir_intrinsic_has_align_mul(intr)) {
131 assert(nir_intrinsic_has_align_offset(intr));
132 unsigned align_mul = nir_intrinsic_align_mul(intr);
133 unsigned align_off = nir_intrinsic_align_offset(intr);
134
135 align_off += offset_units * first_component;
136 align_off = align_off % align_mul;
137
138 nir_intrinsic_set_align(new_intr, align_mul, align_off);
139 }
140
141 /* if the instruction has a BASE, fold the offset adjustment
142 * into that instead of adding alu instructions, otherwise add
143 * instructions
144 */
145 unsigned offset_adj = offset_units * first_component;
146 if (nir_intrinsic_has_base(intr)) {
147 nir_intrinsic_set_base(new_intr,
148 nir_intrinsic_base(intr) + offset_adj);
149 } else {
150 offset = nir_iadd(b, offset,
151 nir_imm_intN_t(b, offset_adj, offset->bit_size));
152 }
153
154 new_intr->num_components = length;
155
156 /* Copy the sources, replacing value/offset, and passing everything
157 * else through to the new instrution:
158 */
159 for (unsigned i = 0; i < num_srcs; i++) {
160 if (i == value_idx) {
161 new_intr->src[i] = nir_src_for_ssa(value);
162 } else if (i == offset_idx) {
163 new_intr->src[i] = nir_src_for_ssa(offset);
164 } else {
165 new_intr->src[i] = intr->src[i];
166 }
167 }
168
169 nir_builder_instr_insert(b, &new_intr->instr);
170
171 /* Clear the bits in the writemask that we just wrote, then try
172 * again to see if more channels are left.
173 */
174 wrmask &= ~cur_mask;
175 }
176
177 /* Finally remove the original intrinsic. */
178 nir_instr_remove(&intr->instr);
179 }
180
181 struct nir_lower_wrmasks_state {
182 nir_instr_filter_cb cb;
183 const void *data;
184 };
185
186 static bool
nir_lower_wrmasks_instr(nir_builder * b,nir_instr * instr,void * data)187 nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data)
188 {
189 struct nir_lower_wrmasks_state *state = data;
190
191 if (instr->type != nir_instr_type_intrinsic)
192 return false;
193
194 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
195
196 /* if no wrmask, then skip it: */
197 if (!nir_intrinsic_has_write_mask(intr))
198 return false;
199
200 /* if wrmask is already contiguous, then nothing to do: */
201 if (nir_intrinsic_write_mask(intr) == BITFIELD_MASK(intr->num_components))
202 return false;
203
204 /* do we know how to lower this instruction? */
205 if (value_src(intr->intrinsic) < 0)
206 return false;
207
208 assert(offset_src(intr->intrinsic) >= 0);
209
210 /* does backend need us to lower this intrinsic? */
211 if (state->cb && !state->cb(instr, state->data))
212 return false;
213
214 split_wrmask(b, intr);
215
216 return true;
217 }
218
219 bool
nir_lower_wrmasks(nir_shader * shader,nir_instr_filter_cb cb,const void * data)220 nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data)
221 {
222 struct nir_lower_wrmasks_state state = {
223 .cb = cb,
224 .data = data,
225 };
226
227 return nir_shader_instructions_pass(shader,
228 nir_lower_wrmasks_instr,
229 nir_metadata_control_flow,
230 &state);
231 }
232