1 #ifndef STATE_XML 2 #define STATE_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 9 10 The rules-ng-ng source files this header was generated from are: 11 - state.xml ( 30526 bytes, from 2024-06-12 08:52:00) 12 - common.xml ( 35664 bytes, from 2024-04-10 11:43:40) 13 - common_3d.xml ( 15069 bytes, from 2024-04-10 11:43:40) 14 - state_hi.xml ( 35854 bytes, from 2024-04-10 11:43:40) 15 - copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) 16 - state_2d.xml ( 52271 bytes, from 2024-04-10 11:43:40) 17 - state_3d.xml ( 89522 bytes, from 2024-04-10 11:43:40) 18 - state_blt.xml ( 14592 bytes, from 2024-04-10 11:43:40) 19 - state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) 20 21 Copyright (C) 2012-2024 by the following authors: 22 - Wladimir J. van der Laan <[email protected]> 23 - Christian Gmeiner <[email protected]> 24 - Lucas Stach <[email protected]> 25 - Russell King <[email protected]> 26 27 Permission is hereby granted, free of charge, to any person obtaining a 28 copy of this software and associated documentation files (the "Software"), 29 to deal in the Software without restriction, including without limitation 30 the rights to use, copy, modify, merge, publish, distribute, sub license, 31 and/or sell copies of the Software, and to permit persons to whom the 32 Software is furnished to do so, subject to the following conditions: 33 34 The above copyright notice and this permission notice (including the 35 next paragraph) shall be included in all copies or substantial portions 36 of the Software. 37 38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 39 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 40 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 41 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 42 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 44 DEALINGS IN THE SOFTWARE. 45 */ 46 47 48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000 49 #define VARYING_COMPONENT_USE_USED 0x00000001 50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002 51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003 52 #define VARYING_INTERPOLATION_MODE_SMOOTH 0x00000000 53 #define VARYING_INTERPOLATION_MODE_NONPERSPECTIVE 0x00000001 54 #define VARYING_INTERPOLATION_MODE_FLAT 0x00000002 55 #define VARYING_INTERPOLATION_MODE_UNK 0x00000003 56 #define VARYING_LOCATION_CENTROID 0x00000001 57 #define FE_DATA_TYPE_BYTE 0x00000000 58 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001 59 #define FE_DATA_TYPE_SHORT 0x00000002 60 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003 61 #define FE_DATA_TYPE_INT 0x00000004 62 #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005 63 #define FE_DATA_TYPE_INT_2_10_10_10_REV 0x00000006 64 #define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV 0x00000007 65 #define FE_DATA_TYPE_FLOAT 0x00000008 66 #define FE_DATA_TYPE_HALF_FLOAT 0x00000009 67 #define FE_DATA_TYPE_FIXED 0x0000000b 68 #define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c 69 #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d 70 #define FE_DATA_TYPE_BYTE_I 0x0000000e 71 #define FE_DATA_TYPE_SHORT_I 0x0000000f 72 #define VARYING_SEMANTIC_MODE__MASK 0x00000003 73 #define VARYING_SEMANTIC_MODE__SHIFT 0 74 #define VARYING_SEMANTIC_MODE(x) (((x) << VARYING_SEMANTIC_MODE__SHIFT) & VARYING_SEMANTIC_MODE__MASK) 75 #define VARYING_SEMANTIC_LOCATION__MASK 0x00000004 76 #define VARYING_SEMANTIC_LOCATION__SHIFT 2 77 #define VARYING_SEMANTIC_LOCATION(x) (((x) << VARYING_SEMANTIC_LOCATION__SHIFT) & VARYING_SEMANTIC_LOCATION__MASK) 78 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff 79 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0 80 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK) 81 #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000 82 #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 16 83 #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK) 84 #define VIVS_FE 0x00000000 85 86 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) 87 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE 0x00000004 88 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010 89 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f 90 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0 91 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK) 92 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030 93 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4 94 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK) 95 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE 0x00000080 96 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK 0x00000700 97 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT 8 98 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK) 99 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK 0x00003000 100 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT 12 101 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK) 102 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000 103 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14 104 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000 105 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND 0x00004000 106 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000 107 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000 108 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16 109 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK) 110 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK 0xff000000 111 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT 24 112 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK) 113 114 #define VIVS_FE_CMD_STREAM_BASE_ADDR 0x00000640 115 116 #define VIVS_FE_INDEX_STREAM_BASE_ADDR 0x00000644 117 118 #define VIVS_FE_INDEX_STREAM_CONTROL 0x00000648 119 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK 0x00000003 120 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT 0 121 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000 122 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001 123 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002 124 #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100 125 126 #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c 127 128 #define VIVS_FE_VERTEX_STREAM_CONTROL 0x00000650 129 130 #define VIVS_FE_COMMAND_ADDRESS 0x00000654 131 132 #define VIVS_FE_COMMAND_CONTROL 0x00000658 133 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff 134 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT 0 135 #define VIVS_FE_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK) 136 #define VIVS_FE_COMMAND_CONTROL_ENABLE 0x00010000 137 138 #define VIVS_FE_DMA_STATUS 0x0000065c 139 140 #define VIVS_FE_DMA_DEBUG_STATE 0x00000660 141 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK 0x0000001f 142 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT 0 143 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE 0x00000000 144 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC 0x00000001 145 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0 0x00000002 146 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0 0x00000003 147 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1 0x00000004 148 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1 0x00000005 149 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR 0x00000006 150 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD 0x00000007 151 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL 0x00000008 152 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL 0x00000009 153 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA 0x0000000a 154 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX 0x0000000b 155 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW 0x0000000c 156 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0 0x0000000d 157 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1 0x0000000e 158 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0 0x0000000f 159 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1 0x00000010 160 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO 0x00000011 161 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT 0x00000012 162 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK 0x00000013 163 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END 0x00000014 164 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL 0x00000015 165 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK 0x00000300 166 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT 8 167 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE 0x00000000 168 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START 0x00000100 169 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ 0x00000200 170 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END 0x00000300 171 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK 0x00000c00 172 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT 10 173 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE 0x00000000 174 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID 0x00000400 175 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID 0x00000800 176 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK 0x00003000 177 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT 12 178 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE 0x00000000 179 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX 0x00001000 180 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL 0x00002000 181 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK 0x0000c000 182 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT 14 183 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE 0x00000000 184 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR 0x00004000 185 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC 0x00008000 186 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK 0x00030000 187 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT 16 188 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE 0x00000000 189 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE 0x00010000 190 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS 0x00020000 191 192 #define VIVS_FE_DMA_ADDRESS 0x00000664 193 194 #define VIVS_FE_DMA_LOW 0x00000668 195 196 #define VIVS_FE_DMA_HIGH 0x0000066c 197 198 #define VIVS_FE_AUTO_FLUSH 0x00000670 199 200 #define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674 201 202 #define VIVS_FE_UNK00678 0x00000678 203 204 #define VIVS_FE_UNK0067C 0x0000067c 205 206 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 207 #define VIVS_FE_VERTEX_STREAMS__ESIZE 0x00000004 208 #define VIVS_FE_VERTEX_STREAMS__LEN 0x00000008 209 210 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) 211 212 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) 213 214 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) 215 #define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004 216 #define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010 217 218 #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) 219 220 #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) 221 222 #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) 223 224 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) 225 226 #define VIVS_FE_HALTI5_ID_CONFIG 0x000007c4 227 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE 0x00000001 228 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE 0x00000002 229 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK 0x0000ff00 230 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT 8 231 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK) 232 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK 0x00ff0000 233 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT 16 234 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK) 235 236 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) 237 #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004 238 #define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002 239 240 #define VIVS_FE_HALTI5_UNK007D8 0x000007d8 241 242 #define VIVS_FE_DESC_START 0x000007dc 243 244 #define VIVS_FE_DESC_END 0x000007e0 245 246 #define VIVS_FE_DESC_AVAIL 0x000007e4 247 #define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f 248 #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0 249 #define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK) 250 251 #define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8 252 253 #define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4 254 255 #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8 256 257 #define VIVS_FE_MULTI_CLUSTER_UNK007FC 0x000007fc 258 259 #define VIVS_GL 0x00000000 260 261 #define VIVS_GL_PIPE_SELECT 0x00003800 262 #define VIVS_GL_PIPE_SELECT_PIPE__MASK 0x00000001 263 #define VIVS_GL_PIPE_SELECT_PIPE__SHIFT 0 264 #define VIVS_GL_PIPE_SELECT_PIPE(x) (((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK) 265 266 #define VIVS_GL_EVENT 0x00003804 267 #define VIVS_GL_EVENT_EVENT_ID__MASK 0x0000001f 268 #define VIVS_GL_EVENT_EVENT_ID__SHIFT 0 269 #define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK) 270 #define VIVS_GL_EVENT_FROM_FE 0x00000020 271 #define VIVS_GL_EVENT_FROM_PE 0x00000040 272 #define VIVS_GL_EVENT_FROM_BLT 0x00000080 273 #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00 274 #define VIVS_GL_EVENT_SOURCE__SHIFT 8 275 #define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK) 276 277 #define VIVS_GL_SEMAPHORE_TOKEN 0x00003808 278 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK 0x0000001f 279 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT 0 280 #define VIVS_GL_SEMAPHORE_TOKEN_FROM(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK) 281 #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00 282 #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8 283 #define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK) 284 #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000 285 #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28 286 #define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK) 287 288 #define VIVS_GL_FLUSH_CACHE 0x0000380c 289 #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001 290 #define VIVS_GL_FLUSH_CACHE_COLOR 0x00000002 291 #define VIVS_GL_FLUSH_CACHE_TEXTURE 0x00000004 292 #define VIVS_GL_FLUSH_CACHE_PE2D 0x00000008 293 #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010 294 #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020 295 #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040 296 #define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400 297 #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800 298 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000 299 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000 300 #define VIVS_GL_FLUSH_CACHE_UNK14 0x00004000 301 302 #define VIVS_GL_FLUSH_MMU 0x00003810 303 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 304 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK1 0x00000002 305 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK2 0x00000004 306 #define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU 0x00000008 307 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010 308 309 #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814 310 #define VIVS_GL_VERTEX_ELEMENT_CONFIG_UNK0 0x00000001 311 #define VIVS_GL_VERTEX_ELEMENT_CONFIG_REUSE 0x00000010 312 313 #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818 314 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003 315 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT 0 316 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE 0x00000000 317 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X 0x00000001 318 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X 0x00000002 319 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK 0x00000008 320 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK 0x000000f0 321 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT 4 322 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK) 323 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK 0x00000100 324 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK 0x00007000 325 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT 12 326 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK) 327 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK 0x00008000 328 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK 0x00030000 329 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT 16 330 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK) 331 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK 0x00080000 332 333 #define VIVS_GL_VARYING_TOTAL_COMPONENTS 0x0000381c 334 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK 0x000000ff 335 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT 0 336 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK) 337 338 #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820 339 340 #define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824 341 342 #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) 343 #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004 344 #define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002 345 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK 0x00000003 346 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT 0 347 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK) 348 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK 0x0000000c 349 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT 2 350 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK) 351 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK 0x00000030 352 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT 4 353 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK) 354 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK 0x000000c0 355 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT 6 356 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK) 357 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK 0x00000300 358 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT 8 359 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK) 360 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK 0x00000c00 361 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT 10 362 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK) 363 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK 0x00003000 364 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT 12 365 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK) 366 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK 0x0000c000 367 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT 14 368 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK) 369 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK 0x00030000 370 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT 16 371 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK) 372 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK 0x000c0000 373 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT 18 374 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK) 375 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK 0x00300000 376 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT 20 377 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK) 378 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK 0x00c00000 379 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT 22 380 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK) 381 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK 0x03000000 382 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT 24 383 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK) 384 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK 0x0c000000 385 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT 26 386 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK) 387 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK 0x30000000 388 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT 28 389 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK) 390 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK 0xc0000000 391 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30 392 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK) 393 394 #define VIVS_GL_UNK0382C 0x0000382c 395 396 #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 397 398 #define VIVS_GL_VARYING_NUM_COMPONENTS2 0x00003834 399 400 #define VIVS_GL_UNK03838 0x00003838 401 402 #define VIVS_GL_API_MODE 0x0000384c 403 #define VIVS_GL_API_MODE_OPENGL 0x00000000 404 #define VIVS_GL_API_MODE_OPENVG 0x00000001 405 #define VIVS_GL_API_MODE_OPENCL 0x00000002 406 407 #define VIVS_GL_CONTEXT_POINTER 0x00003850 408 409 #define VIVS_GL_UNK03854 0x00003854 410 411 #define VIVS_GL_BUG_FIXES 0x00003860 412 413 #define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868 414 415 #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c 416 417 #define VIVS_GL_USC_CONTROL 0x00003884 418 #define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK 0x00000007 419 #define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT 0 420 #define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK) 421 #define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK 0x00000f00 422 #define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT 8 423 #define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK) 424 #define VIVS_GL_USC_CONTROL_UNK16__MASK 0x001f0000 425 #define VIVS_GL_USC_CONTROL_UNK16__SHIFT 16 426 #define VIVS_GL_USC_CONTROL_UNK16(x) (((x) << VIVS_GL_USC_CONTROL_UNK16__SHIFT) & VIVS_GL_USC_CONTROL_UNK16__MASK) 427 428 #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 429 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f 430 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0 431 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK) 432 #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00 433 #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8 434 #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK) 435 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000 436 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16 437 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK) 438 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000 439 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24 440 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK) 441 442 #define VIVS_GL_GS_UNK0388C 0x0000388c 443 444 #define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898 445 446 #define VIVS_GL_SHADER_INDEX 0x0000389c 447 448 #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) 449 #define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004 450 #define VIVS_GL_GS_UNK038A0__LEN 0x00000008 451 452 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES(i0) (0x000038c0 + 0x4*(i0)) 453 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES__ESIZE 0x00000004 454 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES__LEN 0x00000010 455 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_X__MASK 0x00000007 456 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_X__SHIFT 0 457 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_X(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_X__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_X__MASK) 458 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Y__MASK 0x00000070 459 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Y__SHIFT 4 460 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Y(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Y__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Y__MASK) 461 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Z__MASK 0x00000700 462 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Z__SHIFT 8 463 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Z(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Z__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_Z__MASK) 464 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_W__MASK 0x00007000 465 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_W__SHIFT 12 466 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_W(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_W__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V0_W__MASK) 467 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_X__MASK 0x00070000 468 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_X__SHIFT 16 469 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_X(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_X__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_X__MASK) 470 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Y__MASK 0x00700000 471 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Y__SHIFT 20 472 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Y(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Y__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Y__MASK) 473 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Z__MASK 0x07000000 474 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Z__SHIFT 24 475 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Z(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Z__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_Z__MASK) 476 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_W__MASK 0x70000000 477 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_W__SHIFT 28 478 #define VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_W(x) (((x) << VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_W__SHIFT) & VIVS_GL_HALTI5_SHADER_ATTRIBUTES_V1_W__MASK) 479 480 #define VIVS_GL_SECURITY_UNK3900 0x00003900 481 482 #define VIVS_GL_SECURITY_UNK3904 0x00003904 483 484 #define VIVS_GL_MULTI_CLUSTER_UNK3908 0x00003908 485 #define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK 0x00000007 486 #define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT 0 487 #define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK) 488 489 #define VIVS_GL_MULTI_CLUSTER_UNK3910(i0) (0x00003910 + 0x4*(i0)) 490 #define VIVS_GL_MULTI_CLUSTER_UNK3910__ESIZE 0x00000004 491 #define VIVS_GL_MULTI_CLUSTER_UNK3910__LEN 0x00000004 492 #define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK 0x000000ff 493 #define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT 0 494 #define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK) 495 496 #define VIVS_GL_NN_CONFIG 0x00003930 497 #define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003 498 #define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0 499 #define VIVS_GL_NN_CONFIG_UNK0(x) (((x) << VIVS_GL_NN_CONFIG_UNK0__SHIFT) & VIVS_GL_NN_CONFIG_UNK0__MASK) 500 #define VIVS_GL_NN_CONFIG_DISABLE_ZDPN 0x00000004 501 #define VIVS_GL_NN_CONFIG_DISABLE_SWTILING 0x00000008 502 #define VIVS_GL_NN_CONFIG_SMALL_BATCH 0x00000010 503 #define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK 0x00000060 504 #define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT 5 505 #define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE(x) (((x) << VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT) & VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK) 506 #define VIVS_GL_NN_CONFIG_UNK7 0x00000080 507 #define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK 0x00000f00 508 #define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT 8 509 #define VIVS_GL_NN_CONFIG_NN_CORE_COUNT(x) (((x) << VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT) & VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK) 510 #define VIVS_GL_NN_CONFIG_UNK12 0x00001000 511 512 #define VIVS_GL_SRAM_REMAP_ADDRESS 0x00003938 513 514 #define VIVS_GL_OCB_REMAP_START 0x0000393c 515 516 #define VIVS_GL_OCB_REMAP_END 0x00003940 517 518 #define VIVS_GL_TP_CONFIG 0x0000394c 519 520 #define VIVS_GL_UNK03950 0x00003950 521 522 #define VIVS_GL_UNK03A00 0x00003a00 523 #define VIVS_GL_UNK03A00_UNK0__MASK 0x00000007 524 #define VIVS_GL_UNK03A00_UNK0__SHIFT 0 525 #define VIVS_GL_UNK03A00_UNK0(x) (((x) << VIVS_GL_UNK03A00_UNK0__SHIFT) & VIVS_GL_UNK03A00_UNK0__MASK) 526 527 #define VIVS_GL_UNK03A04 0x00003a04 528 529 #define VIVS_GL_UNK03A08 0x00003a08 530 531 #define VIVS_GL_UNK03A0C 0x00003a0c 532 533 #define VIVS_GL_UNK03A10 0x00003a10 534 535 #define VIVS_GL_STALL_TOKEN 0x00003c00 536 #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f 537 #define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0 538 #define VIVS_GL_STALL_TOKEN_FROM(x) (((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK) 539 #define VIVS_GL_STALL_TOKEN_TO__MASK 0x00001f00 540 #define VIVS_GL_STALL_TOKEN_TO__SHIFT 8 541 #define VIVS_GL_STALL_TOKEN_TO(x) (((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK) 542 #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000 543 #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000 544 545 #define VIVS_NFE 0x00000000 546 547 #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 548 #define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004 549 #define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010 550 551 #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0)) 552 553 #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) 554 555 #define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0) (0x00014680 + 0x4*(i0)) 556 557 #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) 558 559 #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) 560 #define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004 561 #define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020 562 563 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0)) 564 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f 565 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0 566 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK) 567 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030 568 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4 569 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK) 570 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000f00 571 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8 572 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK) 573 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000 574 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12 575 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK) 576 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000 577 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14 578 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000 579 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000 580 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000 581 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16 582 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK) 583 584 #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0)) 585 586 #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0)) 587 588 #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0)) 589 590 #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0)) 591 592 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0)) 593 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff 594 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0 595 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK) 596 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800 597 598 #define VIVS_DUMMY 0x00000000 599 600 #define VIVS_DUMMY_DUMMY 0x0003fffc 601 602 #define VIVS_WD 0x00000000 603 604 #define VIVS_WD_UNK18404 0x00018404 605 #define VIVS_WD_UNK18404_UNK0__MASK 0x00000003 606 #define VIVS_WD_UNK18404_UNK0__SHIFT 0 607 #define VIVS_WD_UNK18404_UNK0(x) (((x) << VIVS_WD_UNK18404_UNK0__SHIFT) & VIVS_WD_UNK18404_UNK0__MASK) 608 609 610 #endif /* STATE_XML */ 611