1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef IRIS_SCREEN_H
24 #define IRIS_SCREEN_H
25
26 #include "pipe/p_screen.h"
27 #include "frontend/drm_driver.h"
28 #include "util/disk_cache.h"
29 #include "util/slab.h"
30 #include "util/u_screen.h"
31 #include "intel/dev/intel_device_info.h"
32 #include "intel/isl/isl.h"
33 #include "iris_bufmgr.h"
34 #include "iris_binder.h"
35 #include "iris_measure.h"
36 #include "iris_resource.h"
37
38 struct intel_l3_config;
39 struct intel_vue_map;
40 struct iris_vs_prog_key;
41 struct iris_tcs_prog_key;
42 struct iris_tes_prog_key;
43 struct iris_gs_prog_key;
44 struct iris_fs_prog_key;
45 struct iris_cs_prog_key;
46 enum iris_program_cache_id;
47
48 typedef struct nir_builder nir_builder;
49 typedef struct nir_shader nir_shader;
50
51 struct u_trace;
52
53 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
54 #define WRITE_ONCE(x, v) *(volatile __typeof__(x) *)&(x) = (v)
55
56 #define IRIS_MAX_TEXTURES 128
57 #define IRIS_MAX_SAMPLERS 32
58 #define IRIS_MAX_IMAGES 64
59 #define IRIS_MAX_SOL_BUFFERS 4
60 #define IRIS_MAP_BUFFER_ALIGNMENT 64
61
62 /**
63 * Virtual table for generation-specific (genxml) function calls.
64 */
65 struct iris_vtable {
66 void (*destroy_state)(struct iris_context *ice);
67 void (*init_render_context)(struct iris_batch *batch);
68 void (*init_compute_context)(struct iris_batch *batch);
69 void (*init_copy_context)(struct iris_batch *batch);
70 void (*upload_render_state)(struct iris_context *ice,
71 struct iris_batch *batch,
72 const struct pipe_draw_info *draw,
73 unsigned drawid_offset,
74 const struct pipe_draw_indirect_info *indirect,
75 const struct pipe_draw_start_count_bias *sc);
76 void (*upload_indirect_render_state)(struct iris_context *ice,
77 const struct pipe_draw_info *draw,
78 const struct pipe_draw_indirect_info *indirect,
79 const struct pipe_draw_start_count_bias *sc);
80 void (*upload_indirect_shader_render_state)(struct iris_context *ice,
81 const struct pipe_draw_info *draw,
82 const struct pipe_draw_indirect_info *indirect,
83 const struct pipe_draw_start_count_bias *sc);
84 void (*update_binder_address)(struct iris_batch *batch,
85 struct iris_binder *binder);
86 void (*upload_compute_state)(struct iris_context *ice,
87 struct iris_batch *batch,
88 const struct pipe_grid_info *grid);
89 void (*rebind_buffer)(struct iris_context *ice,
90 struct iris_resource *res);
91 void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
92 uint32_t src);
93 void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
94 uint32_t src);
95 void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
96 uint32_t val);
97 void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
98 uint64_t val);
99 void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
100 struct iris_bo *bo, uint32_t offset);
101 void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
102 struct iris_bo *bo, uint32_t offset);
103 void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
104 struct iris_bo *bo, uint32_t offset,
105 bool predicated);
106 void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
107 struct iris_bo *bo, uint32_t offset,
108 bool predicated);
109 void (*store_data_imm32)(struct iris_batch *batch,
110 struct iris_bo *bo, uint32_t offset,
111 uint32_t value);
112 void (*store_data_imm64)(struct iris_batch *batch,
113 struct iris_bo *bo, uint32_t offset,
114 uint64_t value);
115 void (*copy_mem_mem)(struct iris_batch *batch,
116 struct iris_bo *dst_bo, uint32_t dst_offset,
117 struct iris_bo *src_bo, uint32_t src_offset,
118 unsigned bytes);
119 void (*emit_raw_pipe_control)(struct iris_batch *batch,
120 const char *reason, uint32_t flags,
121 struct iris_bo *bo, uint32_t offset,
122 uint64_t imm);
123
124 void (*emit_mi_report_perf_count)(struct iris_batch *batch,
125 struct iris_bo *bo,
126 uint32_t offset_in_bytes,
127 uint32_t report_id);
128
129 void (*rewrite_compute_walker_pc)(struct iris_batch *batch,
130 uint32_t *walker,
131 struct iris_bo *bo,
132 uint32_t offset);
133
134 unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
135 void (*store_derived_program_state)(const struct intel_device_info *devinfo,
136 enum iris_program_cache_id cache_id,
137 struct iris_compiled_shader *shader);
138 uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
139 const struct intel_vue_map *vue_map);
140 void (*populate_vs_key)(const struct iris_context *ice,
141 const struct shader_info *info,
142 gl_shader_stage last_stage,
143 struct iris_vs_prog_key *key);
144 void (*populate_tcs_key)(const struct iris_context *ice,
145 struct iris_tcs_prog_key *key);
146 void (*populate_tes_key)(const struct iris_context *ice,
147 const struct shader_info *info,
148 gl_shader_stage last_stage,
149 struct iris_tes_prog_key *key);
150 void (*populate_gs_key)(const struct iris_context *ice,
151 const struct shader_info *info,
152 gl_shader_stage last_stage,
153 struct iris_gs_prog_key *key);
154 void (*populate_fs_key)(const struct iris_context *ice,
155 const struct shader_info *info,
156 struct iris_fs_prog_key *key);
157 void (*populate_cs_key)(const struct iris_context *ice,
158 struct iris_cs_prog_key *key);
159 void (*lost_genx_state)(struct iris_context *ice, struct iris_batch *batch);
160 void (*disable_rhwo_optimization)(struct iris_batch *batch, bool disable);
161
162 nir_shader *(*load_shader_lib)(struct iris_screen *screen, void *mem_ctx);
163 unsigned (*call_generation_shader)(struct iris_screen *screen, nir_builder *b);
164 };
165
166 struct iris_address {
167 struct iris_bo *bo;
168 uint64_t offset;
169 enum iris_domain access;
170 };
171
172 struct iris_screen {
173 struct pipe_screen base;
174
175 uint32_t refcount;
176
177 /** Global slab allocator for iris_transfer_map objects */
178 struct slab_parent_pool transfer_pool;
179
180 /** drm device file descriptor, shared with bufmgr, do not close. */
181 int fd;
182
183 /**
184 * drm device file descriptor to used for window system integration, owned
185 * by iris_screen, can be a different DRM instance than fd.
186 */
187 int winsys_fd;
188
189 struct iris_vtable vtbl;
190
191 /** Global program_string_id counter (see get_program_string_id()) */
192 unsigned program_id;
193
194 /** Precompile shaders at link time? (Can be disabled for debugging.) */
195 bool precompile;
196
197 /** driconf options and application workarounds */
198 struct {
199 /** Dual color blend by location instead of index (for broken apps) */
200 bool dual_color_blend_by_location;
201 bool disable_throttling;
202 bool always_flush_cache;
203 bool sync_compile;
204 bool limit_trig_input_range;
205 float lower_depth_range_rate;
206 bool intel_enable_wa_14018912822;
207 bool enable_tbimr;
208 unsigned generated_indirect_threshold;
209 } driconf;
210
211 /** Does the kernel support various features (KERNEL_HAS_* bitfield)? */
212 unsigned kernel_features;
213 #define KERNEL_HAS_WAIT_FOR_SUBMIT (1U<<0)
214 #define KERNEL_HAS_PROTECTED_CONTEXT (1U<<1)
215
216 /**
217 * Last sequence number allocated by the cache tracking mechanism.
218 *
219 * These are used for synchronization and are expected to identify a single
220 * section of a batch, so they should be monotonically increasing and
221 * unique across a single pipe_screen.
222 */
223 uint64_t last_seqno;
224
225 const struct intel_device_info *devinfo;
226 struct isl_device isl_dev;
227 struct iris_bufmgr *bufmgr;
228 struct brw_compiler *brw;
229 struct elk_compiler *elk;
230 struct intel_perf_config *perf_cfg;
231
232 const struct intel_l3_config *l3_config_3d;
233 const struct intel_l3_config *l3_config_cs;
234
235 /**
236 * A buffer containing a marker + description of the driver. This buffer is
237 * added to all execbufs syscalls so that we can identify the driver that
238 * generated a hang by looking at the content of the buffer in the error
239 * state. It is also used for hardware workarounds that require scratch
240 * writes or reads from some unimportant memory. To avoid overriding the
241 * debug data, use the workaround_address field for workarounds.
242 */
243 struct iris_bo *workaround_bo;
244 struct iris_address workaround_address;
245
246 struct util_queue shader_compiler_queue;
247
248 struct disk_cache *disk_cache;
249
250 struct intel_measure_device measure;
251
252 /** Every screen on a bufmgr has an unique ID assigned by the bufmgr. */
253 int id;
254
255 struct iris_bo *breakpoint_bo;
256 };
257
258 struct pipe_screen *
259 iris_screen_create(int fd, const struct pipe_screen_config *config);
260
261 void iris_screen_destroy(struct iris_screen *screen);
262
263 UNUSED static inline struct pipe_screen *
iris_pscreen_ref(struct pipe_screen * pscreen)264 iris_pscreen_ref(struct pipe_screen *pscreen)
265 {
266 struct iris_screen *screen = (struct iris_screen *) pscreen;
267
268 p_atomic_inc(&screen->refcount);
269 return pscreen;
270 }
271
272 UNUSED static inline void
iris_pscreen_unref(struct pipe_screen * pscreen)273 iris_pscreen_unref(struct pipe_screen *pscreen)
274 {
275 struct iris_screen *screen = (struct iris_screen *) pscreen;
276
277 if (p_atomic_dec_zero(&screen->refcount))
278 iris_screen_destroy(screen);
279 }
280
281 bool
282 iris_is_format_supported(struct pipe_screen *pscreen,
283 enum pipe_format format,
284 enum pipe_texture_target target,
285 unsigned sample_count,
286 unsigned storage_sample_count,
287 unsigned usage);
288
289 void iris_disk_cache_init(struct iris_screen *screen);
290
291 #endif
292