1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * SPDX-License-Identifier: MIT
4 */
5
6 /* This file implements randomized SDMA texture blit tests. */
7
8 #include "r600_pipe_common.h"
9 #include "util/u_surface.h"
10 #include "util/rand_xor.h"
11
12 static uint64_t seed_xorshift128plus[2];
13
14 #define RAND_NUM_SIZE 8
15
16 /* The GPU blits are emulated on the CPU using these CPU textures. */
17
18 struct cpu_texture {
19 uint8_t *ptr;
20 uint64_t size;
21 uint64_t layer_stride;
22 unsigned stride;
23 };
24
alloc_cpu_texture(struct cpu_texture * tex,struct pipe_resource * templ,int bpp)25 static void alloc_cpu_texture(struct cpu_texture *tex,
26 struct pipe_resource *templ, int bpp)
27 {
28 tex->stride = align(templ->width0 * bpp, RAND_NUM_SIZE);
29 tex->layer_stride = (uint64_t)tex->stride * templ->height0;
30 tex->size = tex->layer_stride * templ->array_size;
31 tex->ptr = malloc(tex->size);
32 assert(tex->ptr);
33 }
34
set_random_pixels(struct pipe_context * ctx,struct pipe_resource * tex,struct cpu_texture * cpu)35 static void set_random_pixels(struct pipe_context *ctx,
36 struct pipe_resource *tex,
37 struct cpu_texture *cpu)
38 {
39 struct pipe_transfer *t;
40 uint8_t *map;
41 unsigned x,y,z;
42
43 map = pipe_texture_map_3d(ctx, tex, 0, PIPE_MAP_WRITE,
44 0, 0, 0, tex->width0, tex->height0,
45 tex->array_size, &t);
46 assert(map);
47
48 for (z = 0; z < tex->array_size; z++) {
49 for (y = 0; y < tex->height0; y++) {
50 uint64_t *ptr = (uint64_t*)
51 (map + t->layer_stride*z + t->stride*y);
52 uint64_t *ptr_cpu = (uint64_t*)
53 (cpu->ptr + cpu->layer_stride*z + cpu->stride*y);
54 unsigned size = cpu->stride / RAND_NUM_SIZE;
55
56 assert(t->stride % RAND_NUM_SIZE == 0);
57 assert(cpu->stride % RAND_NUM_SIZE == 0);
58
59 for (x = 0; x < size; x++) {
60 *ptr++ = *ptr_cpu++ =
61 rand_xorshift128plus(seed_xorshift128plus);
62 }
63 }
64 }
65
66 pipe_texture_unmap(ctx, t);
67 }
68
compare_textures(struct pipe_context * ctx,struct pipe_resource * tex,struct cpu_texture * cpu,int bpp)69 static bool compare_textures(struct pipe_context *ctx,
70 struct pipe_resource *tex,
71 struct cpu_texture *cpu, int bpp)
72 {
73 struct pipe_transfer *t;
74 uint8_t *map;
75 int y,z;
76 bool pass = true;
77
78 map = pipe_texture_map_3d(ctx, tex, 0, PIPE_MAP_READ,
79 0, 0, 0, tex->width0, tex->height0,
80 tex->array_size, &t);
81 assert(map);
82
83 for (z = 0; z < tex->array_size; z++) {
84 for (y = 0; y < tex->height0; y++) {
85 uint8_t *ptr = map + t->layer_stride*z + t->stride*y;
86 uint8_t *cpu_ptr = cpu->ptr +
87 cpu->layer_stride*z + cpu->stride*y;
88
89 if (memcmp(ptr, cpu_ptr, tex->width0 * bpp)) {
90 pass = false;
91 goto done;
92 }
93 }
94 }
95 done:
96 pipe_texture_unmap(ctx, t);
97 return pass;
98 }
99
get_format_from_bpp(int bpp)100 static enum pipe_format get_format_from_bpp(int bpp)
101 {
102 switch (bpp) {
103 case 1:
104 return PIPE_FORMAT_R8_UINT;
105 case 2:
106 return PIPE_FORMAT_R16_UINT;
107 case 4:
108 return PIPE_FORMAT_R32_UINT;
109 case 8:
110 return PIPE_FORMAT_R32G32_UINT;
111 case 16:
112 return PIPE_FORMAT_R32G32B32A32_UINT;
113 default:
114 assert(0);
115 return PIPE_FORMAT_NONE;
116 }
117 }
118
array_mode_to_string(struct r600_common_screen * rscreen,struct radeon_surf * surf)119 static const char *array_mode_to_string(struct r600_common_screen *rscreen,
120 struct radeon_surf *surf)
121 {
122 if (rscreen->gfx_level >= GFX9) {
123 /* TODO */
124 return " UNKNOWN";
125 } else {
126 switch (surf->u.legacy.level[0].mode) {
127 case RADEON_SURF_MODE_LINEAR_ALIGNED:
128 return "LINEAR_ALIGNED";
129 case RADEON_SURF_MODE_1D:
130 return "1D_TILED_THIN1";
131 case RADEON_SURF_MODE_2D:
132 return "2D_TILED_THIN1";
133 default:
134 assert(0);
135 return " UNKNOWN";
136 }
137 }
138 }
139
generate_max_tex_side(unsigned max_tex_side)140 static unsigned generate_max_tex_side(unsigned max_tex_side)
141 {
142 switch (rand() % 4) {
143 case 0:
144 /* Try to hit large sizes in 1/4 of the cases. */
145 return max_tex_side;
146 case 1:
147 /* Try to hit 1D tiling in 1/4 of the cases. */
148 return 128;
149 default:
150 /* Try to hit common sizes in 2/4 of the cases. */
151 return 2048;
152 }
153 }
154
r600_test_dma(struct r600_common_screen * rscreen)155 void r600_test_dma(struct r600_common_screen *rscreen)
156 {
157 struct pipe_screen *screen = &rscreen->b;
158 struct pipe_context *ctx = screen->context_create(screen, NULL, 0);
159 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
160 uint64_t max_alloc_size;
161 unsigned i, iterations, num_partial_copies, max_tex_side;
162 unsigned num_pass = 0, num_fail = 0;
163
164 max_tex_side = screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE);
165
166 /* Max 128 MB allowed for both textures. */
167 max_alloc_size = 128 * 1024 * 1024;
168
169 /* the seed for random test parameters */
170 srand(0x9b47d95b);
171 /* the seed for random pixel data */
172 s_rand_xorshift128plus(seed_xorshift128plus, false);
173
174 iterations = 1000000000; /* just kill it when you are bored */
175 num_partial_copies = 30;
176
177 /* These parameters are randomly generated per test:
178 * - whether to do one whole-surface copy or N partial copies per test
179 * - which tiling modes to use (LINEAR_ALIGNED, 1D, 2D)
180 * - which texture dimensions to use
181 * - whether to use VRAM (all tiling modes) and GTT (staging, linear
182 * only) allocations
183 * - random initial pixels in src
184 * - generate random subrectangle copies for partial blits
185 */
186 for (i = 0; i < iterations; i++) {
187 struct pipe_resource tsrc = {}, tdst = {}, *src, *dst;
188 struct r600_texture *rdst;
189 struct r600_texture *rsrc;
190 struct cpu_texture src_cpu, dst_cpu;
191 unsigned bpp, max_width, max_height, max_depth, j, num;
192 unsigned gfx_blits = 0, dma_blits = 0, max_tex_side_gen;
193 unsigned max_tex_layers;
194 bool pass;
195 bool do_partial_copies = rand() & 1;
196
197 /* generate a random test case */
198 tsrc.target = tdst.target = PIPE_TEXTURE_2D_ARRAY;
199 tsrc.depth0 = tdst.depth0 = 1;
200
201 bpp = 1 << (rand() % 5);
202 tsrc.format = tdst.format = get_format_from_bpp(bpp);
203
204 max_tex_side_gen = generate_max_tex_side(max_tex_side);
205 max_tex_layers = rand() % 4 ? 1 : 5;
206
207 tsrc.width0 = (rand() % max_tex_side_gen) + 1;
208 tsrc.height0 = (rand() % max_tex_side_gen) + 1;
209 tsrc.array_size = (rand() % max_tex_layers) + 1;
210
211 /* Have a 1/4 chance of getting power-of-two dimensions. */
212 if (rand() % 4 == 0) {
213 tsrc.width0 = util_next_power_of_two(tsrc.width0);
214 tsrc.height0 = util_next_power_of_two(tsrc.height0);
215 }
216
217 if (!do_partial_copies) {
218 /* whole-surface copies only, same dimensions */
219 tdst = tsrc;
220 } else {
221 max_tex_side_gen = generate_max_tex_side(max_tex_side);
222 max_tex_layers = rand() % 4 ? 1 : 5;
223
224 /* many partial copies, dimensions can be different */
225 tdst.width0 = (rand() % max_tex_side_gen) + 1;
226 tdst.height0 = (rand() % max_tex_side_gen) + 1;
227 tdst.array_size = (rand() % max_tex_layers) + 1;
228
229 /* Have a 1/4 chance of getting power-of-two dimensions. */
230 if (rand() % 4 == 0) {
231 tdst.width0 = util_next_power_of_two(tdst.width0);
232 tdst.height0 = util_next_power_of_two(tdst.height0);
233 }
234 }
235
236 /* check texture sizes */
237 if ((uint64_t)tsrc.width0 * tsrc.height0 * tsrc.array_size * bpp +
238 (uint64_t)tdst.width0 * tdst.height0 * tdst.array_size * bpp >
239 max_alloc_size) {
240 /* too large, try again */
241 i--;
242 continue;
243 }
244
245 /* VRAM + the tiling mode depends on dimensions (3/4 of cases),
246 * or GTT + linear only (1/4 of cases)
247 */
248 tsrc.usage = rand() % 4 ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STAGING;
249 tdst.usage = rand() % 4 ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STAGING;
250
251 /* Allocate textures (both the GPU and CPU copies).
252 * The CPU will emulate what the GPU should be doing.
253 */
254 src = screen->resource_create(screen, &tsrc);
255 dst = screen->resource_create(screen, &tdst);
256 assert(src);
257 assert(dst);
258 rdst = (struct r600_texture*)dst;
259 rsrc = (struct r600_texture*)src;
260 alloc_cpu_texture(&src_cpu, &tsrc, bpp);
261 alloc_cpu_texture(&dst_cpu, &tdst, bpp);
262
263 printf("%4u: dst = (%5u x %5u x %u, %s), "
264 " src = (%5u x %5u x %u, %s), bpp = %2u, ",
265 i, tdst.width0, tdst.height0, tdst.array_size,
266 array_mode_to_string(rscreen, &rdst->surface),
267 tsrc.width0, tsrc.height0, tsrc.array_size,
268 array_mode_to_string(rscreen, &rsrc->surface), bpp);
269 fflush(stdout);
270
271 /* set src pixels */
272 set_random_pixels(ctx, src, &src_cpu);
273
274 /* clear dst pixels */
275 rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
276 memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
277
278 /* preparation */
279 max_width = MIN2(tsrc.width0, tdst.width0);
280 max_height = MIN2(tsrc.height0, tdst.height0);
281 max_depth = MIN2(tsrc.array_size, tdst.array_size);
282
283 num = do_partial_copies ? num_partial_copies : 1;
284 for (j = 0; j < num; j++) {
285 int width, height, depth;
286 int srcx, srcy, srcz, dstx, dsty, dstz;
287 struct pipe_box box;
288 unsigned old_num_draw_calls = rctx->num_draw_calls;
289 unsigned old_num_dma_calls = rctx->num_dma_calls;
290
291 if (!do_partial_copies) {
292 /* copy whole src to dst */
293 width = max_width;
294 height = max_height;
295 depth = max_depth;
296
297 srcx = srcy = srcz = dstx = dsty = dstz = 0;
298 } else {
299 /* random sub-rectangle copies from src to dst */
300 depth = (rand() % max_depth) + 1;
301 srcz = rand() % (tsrc.array_size - depth + 1);
302 dstz = rand() % (tdst.array_size - depth + 1);
303
304 /* special code path to hit the tiled partial copies */
305 if (!rsrc->surface.is_linear &&
306 !rdst->surface.is_linear &&
307 rand() & 1) {
308 if (max_width < 8 || max_height < 8)
309 continue;
310 width = ((rand() % (max_width / 8)) + 1) * 8;
311 height = ((rand() % (max_height / 8)) + 1) * 8;
312
313 srcx = rand() % (tsrc.width0 - width + 1) & ~0x7;
314 srcy = rand() % (tsrc.height0 - height + 1) & ~0x7;
315
316 dstx = rand() % (tdst.width0 - width + 1) & ~0x7;
317 dsty = rand() % (tdst.height0 - height + 1) & ~0x7;
318 } else {
319 /* just make sure that it doesn't divide by zero */
320 assert(max_width > 0 && max_height > 0);
321
322 width = (rand() % max_width) + 1;
323 height = (rand() % max_height) + 1;
324
325 srcx = rand() % (tsrc.width0 - width + 1);
326 srcy = rand() % (tsrc.height0 - height + 1);
327
328 dstx = rand() % (tdst.width0 - width + 1);
329 dsty = rand() % (tdst.height0 - height + 1);
330 }
331
332 /* special code path to hit out-of-bounds reads in L2T */
333 if (rsrc->surface.is_linear &&
334 !rdst->surface.is_linear &&
335 rand() % 4 == 0) {
336 srcx = 0;
337 srcy = 0;
338 srcz = 0;
339 }
340 }
341
342 /* GPU copy */
343 u_box_3d(srcx, srcy, srcz, width, height, depth, &box);
344 rctx->dma_copy(ctx, dst, 0, dstx, dsty, dstz, src, 0, &box);
345
346 /* See which engine was used. */
347 gfx_blits += rctx->num_draw_calls > old_num_draw_calls;
348 dma_blits += rctx->num_dma_calls > old_num_dma_calls;
349
350 /* CPU copy */
351 util_copy_box(dst_cpu.ptr, tdst.format, dst_cpu.stride,
352 dst_cpu.layer_stride,
353 dstx, dsty, dstz, width, height, depth,
354 src_cpu.ptr, src_cpu.stride,
355 src_cpu.layer_stride,
356 srcx, srcy, srcz);
357 }
358
359 pass = compare_textures(ctx, dst, &dst_cpu, bpp);
360 if (pass)
361 num_pass++;
362 else
363 num_fail++;
364
365 printf("BLITs: GFX = %2u, DMA = %2u, %s [%u/%u]\n",
366 gfx_blits, dma_blits, pass ? "pass" : "fail",
367 num_pass, num_pass+num_fail);
368
369 /* cleanup */
370 pipe_resource_reference(&src, NULL);
371 pipe_resource_reference(&dst, NULL);
372 free(src_cpu.ptr);
373 free(dst_cpu.ptr);
374 }
375
376 ctx->destroy(ctx);
377 exit(0);
378 }
379