1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "si_build_pm4.h"
8
9 #include "util/hash_table.h"
10 #define XXH_INLINE_ALL
11 #include "util/xxhash.h"
12 #include "util/u_cpu_detect.h"
13 #include "util/u_index_modify.h"
14 #include "util/u_prim.h"
15 #include "util/u_upload_mgr.h"
16 #include "ac_rtld.h"
17 #include "si_build_pm4.h"
18 #include "si_tracepoints.h"
19
20 #if (GFX_VER == 6)
21 #define GFX(name) name##GFX6
22 #elif (GFX_VER == 7)
23 #define GFX(name) name##GFX7
24 #elif (GFX_VER == 8)
25 #define GFX(name) name##GFX8
26 #elif (GFX_VER == 9)
27 #define GFX(name) name##GFX9
28 #elif (GFX_VER == 10)
29 #define GFX(name) name##GFX10
30 #elif (GFX_VER == 103)
31 #define GFX(name) name##GFX10_3
32 #elif (GFX_VER == 11)
33 #define GFX(name) name##GFX11
34 #elif (GFX_VER == 115)
35 #define GFX(name) name##GFX11_5
36 #elif (GFX_VER == 12)
37 #define GFX(name) name##GFX12
38 #else
39 #error "Unknown gfx level"
40 #endif
41
42 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
si_update_shaders(struct si_context * sctx)43 static bool si_update_shaders(struct si_context *sctx)
44 {
45 struct pipe_context *ctx = (struct pipe_context *)sctx;
46 struct si_shader *old_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current;
47 unsigned old_pa_cl_vs_out_cntl = old_vs ? old_vs->pa_cl_vs_out_cntl : 0;
48 bool old_uses_vs_state_provoking_vertex = old_vs ? old_vs->uses_vs_state_provoking_vertex : false;
49 bool old_uses_gs_state_outprim = old_vs ? old_vs->uses_gs_state_outprim : false;
50 struct si_shader *old_ps = sctx->shader.ps.current;
51 unsigned old_spi_shader_col_format =
52 old_ps ? old_ps->key.ps.part.epilog.spi_shader_col_format : 0;
53 int r;
54
55 /* Update TCS and TES. */
56 if (HAS_TESS) {
57 if (!sctx->has_tessellation) {
58 si_init_tess_factor_ring(sctx);
59 if (!sctx->has_tessellation)
60 return false;
61 }
62
63 if (!sctx->is_user_tcs) {
64 if (!si_set_tcs_to_fixed_func_shader(sctx))
65 return false;
66 }
67
68 r = si_shader_select(ctx, &sctx->shader.tcs);
69 if (r)
70 return false;
71 si_pm4_bind_state(sctx, hs, sctx->shader.tcs.current);
72
73 if (!HAS_GS || GFX_VERSION <= GFX8) {
74 r = si_shader_select(ctx, &sctx->shader.tes);
75 if (r)
76 return false;
77
78 if (HAS_GS) {
79 /* TES as ES */
80 assert(GFX_VERSION <= GFX8);
81 si_pm4_bind_state(sctx, es, sctx->shader.tes.current);
82 } else if (NGG) {
83 si_pm4_bind_state(sctx, gs, sctx->shader.tes.current);
84 } else {
85 si_pm4_bind_state(sctx, vs, sctx->shader.tes.current);
86 }
87 }
88 } else {
89 /* Reset TCS to clear fixed function shader. */
90 if (!sctx->is_user_tcs && sctx->shader.tcs.cso) {
91 sctx->shader.tcs.cso = NULL;
92 sctx->shader.tcs.current = NULL;
93 }
94
95 if (GFX_VERSION <= GFX8) {
96 si_pm4_bind_state(sctx, ls, NULL);
97 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
98 }
99 si_pm4_bind_state(sctx, hs, NULL);
100 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
101 }
102
103 /* Update GS. */
104 if (HAS_GS) {
105 r = si_shader_select(ctx, &sctx->shader.gs);
106 if (r)
107 return false;
108 si_pm4_bind_state(sctx, gs, sctx->shader.gs.current);
109 if (!NGG) {
110 si_pm4_bind_state(sctx, vs, sctx->shader.gs.current->gs_copy_shader);
111
112 if (!si_update_gs_ring_buffers(sctx))
113 return false;
114 } else if (GFX_VERSION < GFX11) {
115 si_pm4_bind_state(sctx, vs, NULL);
116 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
117 }
118 } else {
119 if (!NGG) {
120 si_pm4_bind_state(sctx, gs, NULL);
121 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
122 if (GFX_VERSION <= GFX8) {
123 si_pm4_bind_state(sctx, es, NULL);
124 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
125 }
126 }
127 }
128
129 /* Update VS. */
130 if ((!HAS_TESS && !HAS_GS) || GFX_VERSION <= GFX8) {
131 r = si_shader_select(ctx, &sctx->shader.vs);
132 if (r)
133 return false;
134
135 if (!HAS_TESS && !HAS_GS) {
136 if (NGG) {
137 si_pm4_bind_state(sctx, gs, sctx->shader.vs.current);
138 if (GFX_VERSION < GFX11) {
139 si_pm4_bind_state(sctx, vs, NULL);
140 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
141 }
142 } else {
143 si_pm4_bind_state(sctx, vs, sctx->shader.vs.current);
144 }
145 } else if (HAS_TESS) {
146 si_pm4_bind_state(sctx, ls, sctx->shader.vs.current);
147 } else {
148 assert(HAS_GS);
149 si_pm4_bind_state(sctx, es, sctx->shader.vs.current);
150 }
151 }
152
153 if (GFX_VERSION >= GFX9 && HAS_TESS)
154 sctx->vs_uses_base_instance = sctx->queued.named.hs->uses_base_instance;
155 else if (GFX_VERSION >= GFX9 && HAS_GS)
156 sctx->vs_uses_base_instance = sctx->shader.gs.current->uses_base_instance;
157 else
158 sctx->vs_uses_base_instance = sctx->shader.vs.current->uses_base_instance;
159
160 /* Update VGT_SHADER_STAGES_EN. */
161 uint32_t vgt_stages = 0;
162
163 if (HAS_TESS) {
164 if (GFX_VERSION >= GFX12) {
165 vgt_stages |= S_028A98_HS_EN(1) |
166 S_028A98_HS_W32_EN(sctx->queued.named.hs->wave_size == 32);
167 } else {
168 vgt_stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
169 S_028B54_HS_EN(1) |
170 S_028B54_DYNAMIC_HS(1) |
171 S_028B54_HS_W32_EN(GFX_VERSION >= GFX10 &&
172 sctx->queued.named.hs->wave_size == 32);
173 }
174 }
175
176 if (NGG) {
177 vgt_stages |= si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ngg.vgt_shader_stages_en;
178 } else {
179 if (HAS_GS) {
180 /* Legacy GS only supports Wave64. */
181 assert(sctx->shader.gs.current->wave_size == 64);
182
183 vgt_stages |= S_028B54_ES_EN(HAS_TESS ? V_028B54_ES_STAGE_DS : V_028B54_ES_STAGE_REAL) |
184 S_028B54_GS_EN(1) |
185 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER) |
186 S_028B54_VS_W32_EN(GFX_VERSION >= GFX10 &&
187 sctx->shader.gs.current->gs_copy_shader->wave_size == 32);
188 } else if (HAS_TESS) {
189 vgt_stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
190 }
191
192 vgt_stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(GFX_VERSION >= GFX9 ? 2 : 0) |
193 S_028B54_VS_W32_EN(!HAS_GS && GFX_VERSION >= GFX10 &&
194 si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->wave_size == 32);
195 }
196
197 /* Update GE_CNTL. */
198 uint32_t ge_cntl = 0;
199
200 if (GFX_VERSION >= GFX10) {
201 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
202
203 if (NGG) {
204 if (HAS_TESS) {
205 if (GFX_VERSION >= GFX11) {
206 ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl |
207 S_03096C_BREAK_PRIMGRP_AT_EOI(key.u.tess_uses_prim_id);
208 } else {
209 /* PRIM_GRP_SIZE_GFX10 is set by si_emit_vgt_pipeline_state. */
210 ge_cntl = S_03096C_VERT_GRP_SIZE(0) |
211 S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
212 }
213 } else {
214 ge_cntl = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ge_cntl;
215 }
216
217 if (GFX_VERSION >= GFX12)
218 ge_cntl |= S_03096C_DIS_PG_SIZE_ADJUST_FOR_STRIP(1);
219 } else {
220 unsigned primgroup_size;
221 unsigned vertgroup_size;
222 assert(GFX_VERSION < GFX11);
223
224 if (HAS_TESS) {
225 primgroup_size = 0; /* this is set by si_emit_vgt_pipeline_state */
226 vertgroup_size = 0;
227 } else if (HAS_GS) {
228 unsigned vgt_gs_onchip_cntl = sctx->shader.gs.current->gs.vgt_gs_onchip_cntl;
229 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
230 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
231 } else {
232 primgroup_size = 128; /* recommended without a GS and tess */
233 vertgroup_size = 0;
234 }
235
236 ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(primgroup_size) |
237 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
238 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
239 }
240
241 /* Note: GE_CNTL.PACKET_TO_ONE_PA should only be set if LINE_STIPPLE_TEX_ENA == 1.
242 * Since we don't use that, we don't have to do anything.
243 */
244 }
245
246 if (vgt_stages != sctx->vgt_shader_stages_en ||
247 (GFX_VERSION >= GFX10 && ge_cntl != sctx->ge_cntl)) {
248 sctx->vgt_shader_stages_en = vgt_stages;
249 sctx->ge_cntl = ge_cntl;
250 si_mark_atom_dirty(sctx, &sctx->atoms.s.vgt_pipeline_state);
251 }
252
253 struct si_shader *hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current;
254
255 if (old_pa_cl_vs_out_cntl != hw_vs->pa_cl_vs_out_cntl)
256 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
257
258 /* If we start to use any of these, we need to update the SGPR. */
259 if ((hw_vs->uses_vs_state_provoking_vertex && !old_uses_vs_state_provoking_vertex) ||
260 (hw_vs->uses_gs_state_outprim && !old_uses_gs_state_outprim)) {
261 si_update_ngg_sgpr_state_out_prim(sctx, hw_vs, NGG);
262 si_update_ngg_sgpr_state_provoking_vtx(sctx, hw_vs, NGG);
263 }
264
265 r = si_shader_select(ctx, &sctx->shader.ps);
266 if (r)
267 return false;
268 si_pm4_bind_state(sctx, ps, sctx->shader.ps.current);
269
270 unsigned db_shader_control = sctx->shader.ps.current->ps.db_shader_control;
271 if (sctx->ps_db_shader_control != db_shader_control) {
272 sctx->ps_db_shader_control = db_shader_control;
273 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
274 if (sctx->screen->dpbb_allowed)
275 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
276 }
277
278 unsigned pa_sc_hisz_control = sctx->shader.ps.current->ps.pa_sc_hisz_control;
279 if (GFX_VERSION >= GFX12 && sctx->screen->dpbb_allowed &&
280 sctx->ps_pa_sc_hisz_control != pa_sc_hisz_control) {
281 sctx->ps_pa_sc_hisz_control = pa_sc_hisz_control;
282 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
283 }
284
285 if (si_pm4_state_changed(sctx, ps) ||
286 (!NGG && si_pm4_state_changed(sctx, vs)) ||
287 (NGG && si_pm4_state_changed(sctx, gs))) {
288 sctx->atoms.s.spi_map.emit = sctx->emit_spi_map[sctx->shader.ps.current->ps.num_interp];
289 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
290 }
291
292 if ((GFX_VERSION >= GFX10_3 || (GFX_VERSION >= GFX9 && sctx->screen->info.rbplus_allowed)) &&
293 si_pm4_state_changed(sctx, ps) &&
294 (!old_ps || old_spi_shader_col_format !=
295 sctx->shader.ps.current->key.ps.part.epilog.spi_shader_col_format))
296 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
297
298 if (sctx->smoothing_enabled !=
299 sctx->shader.ps.current->key.ps.mono.poly_line_smoothing) {
300 sctx->smoothing_enabled = sctx->shader.ps.current->key.ps.mono.poly_line_smoothing;
301 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
302
303 /* NGG cull state uses smoothing_enabled. */
304 if (GFX_VERSION >= GFX10 && sctx->screen->use_ngg_culling)
305 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
306
307 if (GFX_VERSION == GFX11 && sctx->screen->info.has_export_conflict_bug)
308 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
309
310 if (sctx->framebuffer.nr_samples <= 1)
311 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_locations);
312 }
313
314 if (HAS_TESS)
315 si_update_tess_io_layout_state(sctx);
316
317 if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt)) {
318 /* Pretend the bound shaders form a vk pipeline. Include the scratch size in
319 * the hash calculation to force re-emitting the pipeline if the scratch bo
320 * changes.
321 */
322 uint64_t scratch_bo_size = sctx->scratch_buffer ? sctx->scratch_buffer->bo_size : 0;
323 uint32_t total_size = 0;
324
325 /* Compute pipeline code hash. */
326 XXH64_state_t* xh = XXH64_createState();
327 XXH64_reset(xh, scratch_bo_size);
328
329 for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
330 struct si_shader *shader = sctx->shaders[i].current;
331 if (sctx->shaders[i].cso && shader) {
332 /* Hash the key. */
333 XXH64_update(xh, &shader->key, sizeof(shader->key));
334 /* Hash the main part binary. */
335 XXH64_update(xh, shader->binary.code_buffer, shader->binary.code_size);
336
337 total_size += (uint32_t)align_uintptr(shader->binary.uploaded_code_size, 256);
338 }
339 }
340
341 XXH64_hash_t pipeline_code_hash = XXH64_digest(xh);
342 XXH64_freeState(xh);
343
344 struct si_sqtt_fake_pipeline *pipeline = NULL;
345 if (!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline_code_hash)) {
346 /* This is a new pipeline. Allocate a new bo to hold all the shaders. Without
347 * this, shader code export process creates huge rgp files because RGP assumes
348 * the shaders live sequentially in memory (shader N address = shader 0 + offset N)
349 */
350 struct si_resource *bo = si_aligned_buffer_create(
351 &sctx->screen->b,
352 SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_32BIT,
353 PIPE_USAGE_IMMUTABLE, align(total_size, SI_CPDMA_ALIGNMENT), 256);
354
355 char *ptr = (char *) (bo ? sctx->screen->ws->buffer_map(sctx->screen->ws,
356 bo->buf, NULL,
357 (enum pipe_map_flags)(PIPE_MAP_READ_WRITE | PIPE_MAP_UNSYNCHRONIZED | RADEON_MAP_TEMPORARY)) :
358 NULL);
359
360 uint32_t offset = 0;
361 uint64_t scratch_va = sctx->scratch_buffer ? sctx->scratch_buffer->gpu_address : 0;
362
363 if (ptr) {
364 pipeline = (struct si_sqtt_fake_pipeline *)
365 CALLOC(1, sizeof(struct si_sqtt_fake_pipeline));
366
367 pipeline->code_hash = pipeline_code_hash;
368 pipeline->bo = bo;
369
370 /* Re-upload all gfx shaders and init PM4. */
371 si_pm4_clear_state(&pipeline->pm4, sctx->screen, false);
372
373 uint32_t gfx_sh_offsets[SI_NUM_GRAPHICS_SHADERS] = { 0 };
374 for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
375 struct si_shader *shader = sctx->shaders[i].current;
376 if (sctx->shaders[i].cso && shader) {
377 struct si_resource *original_bo = shader->bo;
378
379 /* Temp override for si_shader_binary_upload_at to work. */
380 shader->bo = pipeline->bo;
381
382 int size = si_shader_binary_upload_at(sctx->screen, shader, scratch_va, offset);
383
384 shader->bo = original_bo;
385
386 assert(size == (int)shader->binary.uploaded_code_size);
387
388 gfx_sh_offsets[i] = offset;
389 offset += align(size, 256);
390
391 struct si_pm4_state *pm4 = &shader->pm4;
392
393 /* Patch the SPI_SHADER_PGM_LO_* register to point to the new bo address,
394 * with the proper offset.
395 */
396 uint64_t va_low = shader->gpu_address >> 8;
397 uint32_t reg = pm4->base.spi_shader_pgm_lo_reg;
398 ac_pm4_set_reg(&pipeline->pm4.base, reg, va_low);
399 }
400 }
401 ac_pm4_finalize(&pipeline->pm4.base);
402 sctx->screen->ws->buffer_unmap(sctx->screen->ws, bo->buf);
403
404 _mesa_hash_table_u64_insert(sctx->sqtt->pipeline_bos,
405 pipeline_code_hash, pipeline);
406
407 si_sqtt_register_pipeline(sctx, pipeline, gfx_sh_offsets);
408 } else {
409 if (bo)
410 si_resource_reference(&bo, NULL);
411 }
412 } else {
413 pipeline = (struct si_sqtt_fake_pipeline *)_mesa_hash_table_u64_search(
414 sctx->sqtt->pipeline_bos, pipeline_code_hash);
415 }
416 assert(pipeline);
417
418 si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 0);
419 si_pm4_bind_state(sctx, sqtt_pipeline, pipeline);
420 }
421
422 if ((GFX_VERSION <= GFX8 &&
423 (si_pm4_state_enabled_and_changed(sctx, ls) || si_pm4_state_enabled_and_changed(sctx, es))) ||
424 si_pm4_state_enabled_and_changed(sctx, hs) || si_pm4_state_enabled_and_changed(sctx, gs) ||
425 (!NGG && si_pm4_state_enabled_and_changed(sctx, vs)) || si_pm4_state_enabled_and_changed(sctx, ps)) {
426 unsigned scratch_size = 0;
427
428 if (HAS_TESS) {
429 if (GFX_VERSION <= GFX8) /* LS */
430 scratch_size = MAX2(scratch_size, sctx->shader.vs.current->config.scratch_bytes_per_wave);
431
432 scratch_size = MAX2(scratch_size, sctx->queued.named.hs->config.scratch_bytes_per_wave);
433
434 if (HAS_GS) {
435 if (GFX_VERSION <= GFX8) /* ES */
436 scratch_size = MAX2(scratch_size, sctx->shader.tes.current->config.scratch_bytes_per_wave);
437
438 scratch_size = MAX2(scratch_size, sctx->shader.gs.current->config.scratch_bytes_per_wave);
439 } else {
440 scratch_size = MAX2(scratch_size, sctx->shader.tes.current->config.scratch_bytes_per_wave);
441 }
442 } else if (HAS_GS) {
443 if (GFX_VERSION <= GFX8) /* ES */
444 scratch_size = MAX2(scratch_size, sctx->shader.vs.current->config.scratch_bytes_per_wave);
445
446 scratch_size = MAX2(scratch_size, sctx->shader.gs.current->config.scratch_bytes_per_wave);
447 } else {
448 scratch_size = MAX2(scratch_size, sctx->shader.vs.current->config.scratch_bytes_per_wave);
449 }
450
451 scratch_size = MAX2(scratch_size, sctx->shader.ps.current->config.scratch_bytes_per_wave);
452
453 if (scratch_size && !si_update_spi_tmpring_size(sctx, scratch_size))
454 return false;
455
456 if (GFX_VERSION >= GFX7) {
457 if (GFX_VERSION <= GFX8 && HAS_TESS && si_pm4_state_enabled_and_changed(sctx, ls))
458 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
459
460 if (HAS_TESS && si_pm4_state_enabled_and_changed(sctx, hs))
461 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
462
463 if (GFX_VERSION <= GFX8 && HAS_GS && si_pm4_state_enabled_and_changed(sctx, es))
464 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
465
466 if ((HAS_GS || NGG) && si_pm4_state_enabled_and_changed(sctx, gs))
467 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
468
469 if (!NGG && si_pm4_state_enabled_and_changed(sctx, vs))
470 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
471
472 if (si_pm4_state_enabled_and_changed(sctx, ps))
473 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
474 }
475 }
476
477 /* si_shader_select_with_key can clear the ngg_culling in the shader key if the shader
478 * compilation hasn't finished. Set it to the same value in si_context.
479 */
480 if (GFX_VERSION >= GFX10 && NGG)
481 sctx->ngg_culling = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->key.ge.opt.ngg_culling;
482
483 sctx->do_update_shaders = false;
484 return true;
485 }
486
487 ALWAYS_INLINE
si_conv_pipe_prim(unsigned mode)488 static unsigned si_conv_pipe_prim(unsigned mode)
489 {
490 static const unsigned prim_conv[] = {
491 [MESA_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
492 [MESA_PRIM_LINES] = V_008958_DI_PT_LINELIST,
493 [MESA_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
494 [MESA_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
495 [MESA_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
496 [MESA_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
497 [MESA_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
498 [MESA_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
499 [MESA_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
500 [MESA_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
501 [MESA_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
502 [MESA_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
503 [MESA_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
504 [MESA_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
505 [MESA_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
506 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST};
507 assert(mode < ARRAY_SIZE(prim_conv));
508 return prim_conv[mode];
509 }
510
511 template<amd_gfx_level GFX_VERSION>
si_cp_dma_prefetch_inline(struct si_context * sctx,uint64_t address,unsigned size)512 static void si_cp_dma_prefetch_inline(struct si_context *sctx, uint64_t address, unsigned size)
513 {
514 assert(GFX_VERSION >= GFX7);
515 assert(sctx->screen->info.has_cp_dma);
516
517 if (GFX_VERSION >= GFX11)
518 size = MIN2(size, 32768 - SI_CPDMA_ALIGNMENT);
519
520 /* The prefetch address and size must be aligned, so that we don't have to apply
521 * the complicated hw bug workaround.
522 *
523 * The size should also be less than 2 MB, so that we don't have to use a loop.
524 * Callers shouldn't need to prefetch more than 2 MB.
525 */
526 assert(size % SI_CPDMA_ALIGNMENT == 0);
527 assert(address % SI_CPDMA_ALIGNMENT == 0);
528 assert(size < S_415_BYTE_COUNT_GFX6(~0u));
529
530 uint32_t header = S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
531 uint32_t command = S_415_BYTE_COUNT_GFX6(size);
532
533 if (GFX_VERSION >= GFX9) {
534 command |= S_415_DISABLE_WR_CONFIRM_GFX9(1);
535 header |= S_411_DST_SEL(V_411_NOWHERE);
536 } else {
537 command |= S_415_DISABLE_WR_CONFIRM_GFX6(1);
538 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
539 }
540
541 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
542 radeon_begin(cs);
543 radeon_emit(PKT3(PKT3_DMA_DATA, 5, 0));
544 radeon_emit(header);
545 radeon_emit(address); /* SRC_ADDR_LO [31:0] */
546 radeon_emit(address >> 32); /* SRC_ADDR_HI [31:0] */
547 radeon_emit(address); /* DST_ADDR_LO [31:0] */
548 radeon_emit(address >> 32); /* DST_ADDR_HI [31:0] */
549 radeon_emit(command);
550 radeon_end();
551 }
552
553 #if GFX_VER == 6 /* declare this function only once because it handles all chips. */
554
si_cp_dma_prefetch(struct si_context * sctx,struct pipe_resource * buf,unsigned offset,unsigned size)555 void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf,
556 unsigned offset, unsigned size)
557 {
558 uint64_t address = si_resource(buf)->gpu_address + offset;
559 switch (sctx->gfx_level) {
560 case GFX7:
561 si_cp_dma_prefetch_inline<GFX7>(sctx, address, size);
562 break;
563 case GFX8:
564 si_cp_dma_prefetch_inline<GFX8>(sctx, address, size);
565 break;
566 case GFX9:
567 si_cp_dma_prefetch_inline<GFX9>(sctx, address, size);
568 break;
569 case GFX10:
570 si_cp_dma_prefetch_inline<GFX10>(sctx, address, size);
571 break;
572 case GFX10_3:
573 si_cp_dma_prefetch_inline<GFX10_3>(sctx, address, size);
574 break;
575 case GFX11:
576 si_cp_dma_prefetch_inline<GFX11>(sctx, address, size);
577 break;
578 case GFX11_5:
579 si_cp_dma_prefetch_inline<GFX11_5>(sctx, address, size);
580 break;
581 case GFX12:
582 si_cp_dma_prefetch_inline<GFX12>(sctx, address, size);
583 break;
584 default:
585 break;
586 }
587 }
588
589 #endif
590
591 template<amd_gfx_level GFX_VERSION>
si_prefetch_shader_async(struct si_context * sctx,struct si_shader * shader)592 static void si_prefetch_shader_async(struct si_context *sctx, struct si_shader *shader)
593 {
594 struct pipe_resource *bo = &shader->bo->b.b;
595 si_cp_dma_prefetch_inline<GFX_VERSION>(sctx, shader->gpu_address, bo->width0);
596 }
597
598 /**
599 * Prefetch shaders.
600 */
601 template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
602 ALWAYS_INLINE
si_prefetch_shaders(struct si_context * sctx)603 static void si_prefetch_shaders(struct si_context *sctx)
604 {
605 unsigned mask = sctx->prefetch_L2_mask;
606
607 /* GFX6 doesn't support the L2 prefetch. */
608 if (GFX_VERSION < GFX7 || !mask)
609 return;
610
611 /* Prefetch shaders and VBO descriptors into L2. */
612 if (GFX_VERSION >= GFX11) {
613 if (HAS_TESS && mask & SI_PREFETCH_HS)
614 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.hs);
615
616 if (mask & SI_PREFETCH_GS)
617 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
618 } else if (GFX_VERSION >= GFX9) {
619 if (HAS_TESS) {
620 if (mask & SI_PREFETCH_HS)
621 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.hs);
622 }
623 if ((HAS_GS || NGG) && mask & SI_PREFETCH_GS)
624 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
625 if (!NGG && mask & SI_PREFETCH_VS)
626 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.vs);
627 } else {
628 /* GFX6-GFX8 */
629 /* Choose the right spot for the VBO prefetch. */
630 if (HAS_TESS) {
631 if (mask & SI_PREFETCH_LS)
632 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.ls);
633 if (mask & SI_PREFETCH_HS)
634 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.hs);
635 if (mask & SI_PREFETCH_ES)
636 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.es);
637 if (mask & SI_PREFETCH_GS)
638 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
639 } else if (HAS_GS) {
640 if (mask & SI_PREFETCH_ES)
641 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.es);
642 if (mask & SI_PREFETCH_GS)
643 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.gs);
644 }
645 if (mask & SI_PREFETCH_VS)
646 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.vs);
647 }
648
649 if (mask & SI_PREFETCH_PS)
650 si_prefetch_shader_async<GFX_VERSION>(sctx, sctx->queued.named.ps);
651
652 /* This must be cleared only when AFTER_DRAW is true. */
653 sctx->prefetch_L2_mask = 0;
654 }
655
si_num_prims_for_vertices(enum mesa_prim prim,unsigned count,unsigned vertices_per_patch)656 static unsigned si_num_prims_for_vertices(enum mesa_prim prim,
657 unsigned count, unsigned vertices_per_patch)
658 {
659 switch (prim) {
660 case MESA_PRIM_PATCHES:
661 return count / vertices_per_patch;
662 case MESA_PRIM_POLYGON:
663 /* It's a triangle fan with different edge flags. */
664 return count >= 3 ? count - 2 : 0;
665 case SI_PRIM_RECTANGLE_LIST:
666 return count / 3;
667 default:
668 return u_decomposed_prims_for_vertices(prim, count);
669 }
670 }
671
si_get_init_multi_vgt_param(struct si_screen * sscreen,union si_vgt_param_key * key)672 static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_vgt_param_key *key)
673 {
674 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 2);
675 unsigned max_primgroup_in_wave = 2;
676
677 /* SWITCH_ON_EOP(0) is always preferable. */
678 bool wd_switch_on_eop = false;
679 bool ia_switch_on_eop = false;
680 bool ia_switch_on_eoi = false;
681 bool partial_vs_wave = false;
682 bool partial_es_wave = false;
683
684 if (key->u.uses_tess) {
685 /* SWITCH_ON_EOI must be set if PrimID is used. */
686 if (key->u.tess_uses_prim_id)
687 ia_switch_on_eoi = true;
688
689 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
690 if ((sscreen->info.family == CHIP_TAHITI || sscreen->info.family == CHIP_PITCAIRN ||
691 sscreen->info.family == CHIP_BONAIRE) &&
692 key->u.uses_gs)
693 partial_vs_wave = true;
694
695 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
696 if (sscreen->info.has_distributed_tess) {
697 if (key->u.uses_gs) {
698 if (sscreen->info.gfx_level == GFX8)
699 partial_es_wave = true;
700 } else {
701 partial_vs_wave = true;
702 }
703 }
704 }
705
706 /* This is a hardware requirement. */
707 if (key->u.line_stipple_enabled || (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
708 ia_switch_on_eop = true;
709 wd_switch_on_eop = true;
710 }
711
712 if (sscreen->info.gfx_level >= GFX7) {
713 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
714 * 4 shader engines. Set 1 to pass the assertion below.
715 * The other cases are hardware requirements.
716 *
717 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
718 * for points, line strips, and tri strips.
719 */
720 if (sscreen->info.max_se <= 2 || key->u.prim == MESA_PRIM_POLYGON ||
721 key->u.prim == MESA_PRIM_LINE_LOOP || key->u.prim == MESA_PRIM_TRIANGLE_FAN ||
722 key->u.prim == MESA_PRIM_TRIANGLE_STRIP_ADJACENCY ||
723 (key->u.primitive_restart &&
724 (sscreen->info.family < CHIP_POLARIS10 ||
725 (key->u.prim != MESA_PRIM_POINTS && key->u.prim != MESA_PRIM_LINE_STRIP &&
726 key->u.prim != MESA_PRIM_TRIANGLE_STRIP))) ||
727 key->u.count_from_stream_output)
728 wd_switch_on_eop = true;
729
730 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
731 * We don't know that for indirect drawing, so treat it as
732 * always problematic. */
733 if (sscreen->info.family == CHIP_HAWAII && key->u.uses_instancing)
734 wd_switch_on_eop = true;
735
736 /* Performance recommendation for 4 SE Gfx7-8 parts if
737 * instances are smaller than a primgroup.
738 * Assume indirect draws always use small instances.
739 * This is needed for good VS wave utilization.
740 */
741 if (sscreen->info.gfx_level <= GFX8 && sscreen->info.max_se == 4 &&
742 key->u.multi_instances_smaller_than_primgroup)
743 wd_switch_on_eop = true;
744
745 /* Required on GFX7 and later. */
746 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
747 ia_switch_on_eoi = true;
748
749 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
750 * to work around a GS hang.
751 */
752 if (key->u.uses_gs &&
753 (sscreen->info.family == CHIP_TONGA || sscreen->info.family == CHIP_FIJI ||
754 sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11 ||
755 sscreen->info.family == CHIP_POLARIS12 || sscreen->info.family == CHIP_VEGAM))
756 partial_vs_wave = true;
757
758 /* Required by Hawaii and, for some special cases, by GFX8. */
759 if (ia_switch_on_eoi &&
760 (sscreen->info.family == CHIP_HAWAII ||
761 (sscreen->info.gfx_level == GFX8 && (key->u.uses_gs || max_primgroup_in_wave != 2))))
762 partial_vs_wave = true;
763
764 /* Instancing bug on Bonaire. */
765 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi && key->u.uses_instancing)
766 partial_vs_wave = true;
767
768 /* This only applies to Polaris10 and later 4 SE chips.
769 * wd_switch_on_eop is already true on all other chips.
770 */
771 if (!wd_switch_on_eop && key->u.primitive_restart)
772 partial_vs_wave = true;
773
774 /* If the WD switch is false, the IA switch must be false too. */
775 assert(wd_switch_on_eop || !ia_switch_on_eop);
776 }
777
778 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
779 if (sscreen->info.gfx_level <= GFX8 && ia_switch_on_eoi)
780 partial_es_wave = true;
781
782 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
783 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
784 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
785 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.gfx_level >= GFX7 ? wd_switch_on_eop : 0) |
786 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
787 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.gfx_level == GFX8 ? max_primgroup_in_wave
788 : 0) |
789 S_030960_EN_INST_OPT_BASIC(sscreen->info.gfx_level >= GFX9) |
790 S_030960_EN_INST_OPT_ADV(sscreen->info.gfx_level >= GFX9);
791 }
792
si_init_ia_multi_vgt_param_table(struct si_context * sctx)793 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
794 {
795 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
796 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
797 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
798 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
799 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
800 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
801 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
802 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
803 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
804 union si_vgt_param_key key;
805
806 key.index = 0;
807 key.u.prim = prim;
808 key.u.uses_instancing = uses_instancing;
809 key.u.multi_instances_smaller_than_primgroup = multi_instances;
810 key.u.primitive_restart = primitive_restart;
811 key.u.count_from_stream_output = count_from_so;
812 key.u.line_stipple_enabled = line_stipple;
813 key.u.uses_tess = uses_tess;
814 key.u.tess_uses_prim_id = tess_uses_primid;
815 key.u.uses_gs = uses_gs;
816
817 sctx->ia_multi_vgt_param[key.index] =
818 si_get_init_multi_vgt_param(sctx->screen, &key);
819 }
820 }
821
si_is_line_stipple_enabled(struct si_context * sctx)822 static bool si_is_line_stipple_enabled(struct si_context *sctx)
823 {
824 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
825
826 return rs->line_stipple_enable && sctx->current_rast_prim != MESA_PRIM_POINTS &&
827 (rs->polygon_mode_is_lines || util_prim_is_lines(sctx->current_rast_prim));
828 }
829
830 enum si_is_draw_vertex_state {
831 DRAW_VERTEX_STATE_OFF,
832 DRAW_VERTEX_STATE_ON,
833 };
834
835 enum si_has_sh_pairs_packed {
836 HAS_SH_PAIRS_PACKED_OFF,
837 HAS_SH_PAIRS_PACKED_ON,
838 };
839
840 template <si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
num_instanced_prims_less_than(const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned min_vertex_count,unsigned instance_count,unsigned num_prims,uint8_t vertices_per_patch)841 static bool num_instanced_prims_less_than(const struct pipe_draw_indirect_info *indirect,
842 enum mesa_prim prim,
843 unsigned min_vertex_count,
844 unsigned instance_count,
845 unsigned num_prims,
846 uint8_t vertices_per_patch)
847 {
848 if (IS_DRAW_VERTEX_STATE)
849 return 0;
850
851 if (indirect) {
852 return indirect->buffer ||
853 (instance_count > 1 && indirect->count_from_stream_output);
854 } else {
855 return instance_count > 1 &&
856 si_num_prims_for_vertices(prim, min_vertex_count, vertices_per_patch) < num_prims;
857 }
858 }
859
860 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS,
861 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
si_get_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count)862 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
863 const struct pipe_draw_indirect_info *indirect,
864 enum mesa_prim prim, unsigned instance_count,
865 bool primitive_restart, unsigned min_vertex_count)
866 {
867 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
868 unsigned primgroup_size;
869 unsigned ia_multi_vgt_param;
870
871 if (HAS_TESS) {
872 primgroup_size = sctx->num_patches_per_workgroup;
873 } else if (HAS_GS) {
874 primgroup_size = 64; /* recommended with a GS */
875 } else {
876 primgroup_size = 128; /* recommended without a GS and tess */
877 }
878
879 key.u.prim = prim;
880 key.u.uses_instancing = !IS_DRAW_VERTEX_STATE &&
881 ((indirect && indirect->buffer) || instance_count > 1);
882 key.u.multi_instances_smaller_than_primgroup =
883 num_instanced_prims_less_than<IS_DRAW_VERTEX_STATE>(indirect, prim, min_vertex_count,
884 instance_count, primgroup_size,
885 sctx->patch_vertices);
886 key.u.primitive_restart = !IS_DRAW_VERTEX_STATE && primitive_restart;
887 key.u.count_from_stream_output = !IS_DRAW_VERTEX_STATE && indirect &&
888 indirect->count_from_stream_output;
889 key.u.line_stipple_enabled = si_is_line_stipple_enabled(sctx);
890
891 ia_multi_vgt_param =
892 sctx->ia_multi_vgt_param[key.index] | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
893
894 if (HAS_GS) {
895 /* GS requirement. */
896 if (GFX_VERSION <= GFX8 &&
897 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
898 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
899
900 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
901 * The hw doc says all multi-SE chips are affected, but Vulkan
902 * only applies it to Hawaii. Do what Vulkan does.
903 */
904 if (GFX_VERSION == GFX7 &&
905 sctx->family == CHIP_HAWAII && G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
906 num_instanced_prims_less_than<IS_DRAW_VERTEX_STATE>(indirect, prim, min_vertex_count,
907 instance_count, 2, sctx->patch_vertices)) {
908 /* The cache flushes should have been emitted already. */
909 assert(sctx->barrier_flags == 0);
910 sctx->barrier_flags = SI_BARRIER_EVENT_VGT_FLUSH;
911 si_emit_barrier_direct(sctx);
912 }
913 }
914
915 return ia_multi_vgt_param;
916 }
917
918 /* rast_prim is the primitive type after GS. */
919 template<amd_gfx_level GFX_VERSION, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE
si_emit_rasterizer_prim_state(struct si_context * sctx)920 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
921 {
922 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
923
924 radeon_begin(cs);
925
926 if (unlikely(si_is_line_stipple_enabled(sctx))) {
927 /* For lines, reset the stipple pattern at each primitive. Otherwise,
928 * reset the stipple pattern at each packet (line strips, line loops).
929 */
930 enum mesa_prim rast_prim = sctx->current_rast_prim;
931 bool reset_per_prim = rast_prim == MESA_PRIM_LINES ||
932 rast_prim == MESA_PRIM_LINES_ADJACENCY;
933 /* 0 = no reset, 1 = reset per prim, 2 = reset per packet */
934 if (GFX_VERSION >= GFX12) {
935 radeon_opt_set_context_reg(R_028A44_PA_SC_LINE_STIPPLE_RESET,
936 SI_TRACKED_PA_SC_LINE_STIPPLE_RESET,
937 S_028A44_AUTO_RESET_CNTL(reset_per_prim ? 1 : 2));
938 } else {
939 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
940
941 radeon_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE,
942 SI_TRACKED_PA_SC_LINE_STIPPLE,
943 rs->pa_sc_line_stipple |
944 S_028A0C_AUTO_RESET_CNTL(reset_per_prim ? 1 : 2));
945 }
946 }
947
948 if (NGG || HAS_GS) {
949 if (GFX_VERSION >= GFX11) {
950 radeon_opt_set_uconfig_reg(R_030998_VGT_GS_OUT_PRIM_TYPE,
951 SI_TRACKED_VGT_GS_OUT_PRIM_TYPE_UCONFIG, sctx->gs_out_prim);
952 } else {
953 radeon_opt_set_context_reg(R_028A6C_VGT_GS_OUT_PRIM_TYPE,
954 SI_TRACKED_VGT_GS_OUT_PRIM_TYPE, sctx->gs_out_prim);
955 }
956 }
957
958 if (GFX_VERSION == GFX9)
959 radeon_end_update_context_roll();
960 else
961 radeon_end();
962 }
963
964 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
965 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED> ALWAYS_INLINE
si_emit_vs_state(struct si_context * sctx,unsigned index_size)966 static void si_emit_vs_state(struct si_context *sctx, unsigned index_size)
967 {
968 if (!IS_DRAW_VERTEX_STATE && sctx->num_vs_blit_sgprs) {
969 /* Re-emit the state after we leave u_blitter. */
970 sctx->last_vs_state = ~0;
971 sctx->last_gs_state = ~0;
972 return;
973 }
974
975 unsigned vs_state = sctx->current_vs_state; /* all VS bits */
976 unsigned gs_state = sctx->current_gs_state; /* only GS and NGG bits; VS bits will be copied here */
977
978 if (sctx->shader.vs.cso->info.uses_base_vertex && index_size)
979 vs_state |= ENCODE_FIELD(VS_STATE_INDEXED, 1);
980
981 /* Copy all state bits from vs_state to gs_state. */
982 gs_state |= vs_state;
983
984 if (vs_state != sctx->last_vs_state ||
985 ((HAS_GS || NGG) && gs_state != sctx->last_gs_state)) {
986 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
987
988 /* These are all constant expressions. */
989 unsigned vs_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
990 PIPE_SHADER_VERTEX);
991 unsigned tes_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
992 PIPE_SHADER_TESS_EVAL);
993 unsigned gs_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
994 PIPE_SHADER_GEOMETRY);
995 unsigned gs_copy_base = R_00B130_SPI_SHADER_USER_DATA_VS_0;
996
997 radeon_begin(cs);
998 if (HAS_GS) {
999 radeon_set_or_push_gfx_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state);
1000
1001 /* GS always uses the state bits for emulating VGT_ESGS_RING_ITEMSIZE on Gfx9
1002 * (via nir_load_esgs_vertex_stride_amd) and for emulating GS pipeline statistics
1003 * on gfx10.x. NGG GS also has lots of states in there.
1004 */
1005 if (GFX_VERSION >= GFX9)
1006 radeon_set_or_push_gfx_sh_reg(gs_base + SI_SGPR_VS_STATE_BITS * 4, gs_state);
1007
1008 /* The GS copy shader (for legacy GS) always uses the state bits. */
1009 if (!NGG)
1010 radeon_set_or_push_gfx_sh_reg(gs_copy_base + SI_SGPR_VS_STATE_BITS * 4, gs_state);
1011 } else if (HAS_TESS) {
1012 radeon_set_or_push_gfx_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state);
1013 radeon_set_or_push_gfx_sh_reg(tes_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state);
1014 } else {
1015 radeon_set_or_push_gfx_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state);
1016 }
1017 radeon_end();
1018
1019 sctx->last_vs_state = vs_state;
1020 if (HAS_GS || NGG)
1021 sctx->last_gs_state = gs_state;
1022 }
1023 }
1024
1025 template <amd_gfx_level GFX_VERSION> ALWAYS_INLINE
si_prim_restart_index_changed(struct si_context * sctx,unsigned index_size,bool primitive_restart,unsigned restart_index)1026 static bool si_prim_restart_index_changed(struct si_context *sctx, unsigned index_size,
1027 bool primitive_restart, unsigned restart_index)
1028 {
1029 if (!primitive_restart)
1030 return false;
1031
1032 if (sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)
1033 return true;
1034
1035 /* GFX8+ only compares the index type number of bits of the restart index, so the unused bits
1036 * are "don't care".
1037 *
1038 * Summary of restart index comparator behavior:
1039 * - GFX6-7: Compare all bits.
1040 * - GFX8: Only compare index type bits.
1041 * - GFX9+: If MATCH_ALL_BITS, compare all bits, else only compare index type bits.
1042 */
1043 if (GFX_VERSION >= GFX8) {
1044 /* This masking eliminates no-op 0xffffffff -> 0xffff restart index changes that cause
1045 * unnecessary context rolls when switching the index type.
1046 */
1047 unsigned index_mask = BITFIELD_MASK(index_size * 8);
1048 return (restart_index & index_mask) != (sctx->last_restart_index & index_mask);
1049 } else {
1050 return restart_index != sctx->last_restart_index;
1051 }
1052 }
1053
1054 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS,
1055 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
si_emit_ia_multi_vgt_param(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned instance_count,bool primitive_restart,unsigned min_vertex_count)1056 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
1057 const struct pipe_draw_indirect_info *indirect,
1058 enum mesa_prim prim, unsigned instance_count,
1059 bool primitive_restart, unsigned min_vertex_count)
1060 {
1061 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1062 unsigned ia_multi_vgt_param;
1063
1064 ia_multi_vgt_param =
1065 si_get_ia_multi_vgt_param<GFX_VERSION, HAS_TESS, HAS_GS, IS_DRAW_VERTEX_STATE>
1066 (sctx, indirect, prim, instance_count, primitive_restart, min_vertex_count);
1067
1068 radeon_begin(cs);
1069 if (GFX_VERSION == GFX9) {
1070 /* Workaround for SpecviewPerf13 Catia hang on GFX9. */
1071 if (prim != sctx->last_prim)
1072 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG);
1073
1074 radeon_opt_set_uconfig_reg_idx(R_030960_IA_MULTI_VGT_PARAM,
1075 SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG,
1076 4, ia_multi_vgt_param);
1077 } else if (GFX_VERSION >= GFX7) {
1078 radeon_opt_set_context_reg_idx(R_028AA8_IA_MULTI_VGT_PARAM,
1079 SI_TRACKED_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
1080 } else {
1081 radeon_opt_set_context_reg(R_028AA8_IA_MULTI_VGT_PARAM,
1082 SI_TRACKED_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
1083 }
1084 radeon_end();
1085 }
1086
1087 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1088 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE> ALWAYS_INLINE
si_emit_draw_registers(struct si_context * sctx,const struct pipe_draw_indirect_info * indirect,enum mesa_prim prim,unsigned index_size,unsigned instance_count,bool primitive_restart,unsigned restart_index,unsigned min_vertex_count)1089 static void si_emit_draw_registers(struct si_context *sctx,
1090 const struct pipe_draw_indirect_info *indirect,
1091 enum mesa_prim prim, unsigned index_size,
1092 unsigned instance_count, bool primitive_restart,
1093 unsigned restart_index, unsigned min_vertex_count)
1094 {
1095 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1096
1097 if (GFX_VERSION <= GFX9) {
1098 si_emit_ia_multi_vgt_param<GFX_VERSION, HAS_TESS, HAS_GS, IS_DRAW_VERTEX_STATE>
1099 (sctx, indirect, prim, instance_count, primitive_restart, min_vertex_count);
1100 }
1101
1102 radeon_begin(cs);
1103
1104 if (prim != sctx->last_prim) {
1105 unsigned vgt_prim = HAS_TESS ? V_008958_DI_PT_PATCH : si_conv_pipe_prim(prim);
1106
1107 if (GFX_VERSION >= GFX12 && HAS_TESS)
1108 vgt_prim |= S_030908_NUM_INPUT_CP(sctx->patch_vertices);
1109
1110 if (GFX_VERSION >= GFX10)
1111 radeon_set_uconfig_reg(R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
1112 else if (GFX_VERSION >= GFX7)
1113 radeon_set_uconfig_reg_idx(R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
1114 else
1115 radeon_set_config_reg(R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
1116
1117 sctx->last_prim = prim;
1118 }
1119
1120 /* Primitive restart. */
1121 if (GFX_VERSION >= GFX11) {
1122 /* GFX11+ can ignore primitive restart for non-indexed draws because it has no effect.
1123 * (it's disabled for non-indexed draws by setting DISABLE_FOR_AUTO_INDEX in the preamble)
1124 */
1125 if (index_size) {
1126 if (primitive_restart != sctx->last_primitive_restart_en) {
1127 radeon_set_uconfig_reg(R_03092C_GE_MULTI_PRIM_IB_RESET_EN,
1128 S_03092C_RESET_EN(primitive_restart) |
1129 /* This disables primitive restart for non-indexed draws.
1130 * By keeping this set, we don't have to unset RESET_EN
1131 * for non-indexed draws. */
1132 S_03092C_DISABLE_FOR_AUTO_INDEX(1));
1133 sctx->last_primitive_restart_en = primitive_restart;
1134 }
1135 if (si_prim_restart_index_changed<GFX_VERSION>(sctx, index_size, primitive_restart,
1136 restart_index)) {
1137 radeon_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, restart_index);
1138 sctx->last_restart_index = restart_index;
1139 }
1140 }
1141 } else {
1142 if (primitive_restart != sctx->last_primitive_restart_en) {
1143 if (GFX_VERSION >= GFX9)
1144 radeon_set_uconfig_reg(R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
1145 else
1146 radeon_set_context_reg(R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
1147 sctx->last_primitive_restart_en = primitive_restart;
1148 }
1149 if (si_prim_restart_index_changed<GFX_VERSION>(sctx, index_size, primitive_restart,
1150 restart_index)) {
1151 radeon_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, restart_index);
1152 sctx->last_restart_index = restart_index;
1153 if (GFX_VERSION == GFX9)
1154 sctx->context_roll = true;
1155 }
1156 }
1157 radeon_end();
1158 }
1159
1160 static ALWAYS_INLINE void
gfx11_emit_buffered_sh_regs_inline(struct si_context * sctx,unsigned * num_regs,struct gfx11_reg_pair * reg_pairs)1161 gfx11_emit_buffered_sh_regs_inline(struct si_context *sctx, unsigned *num_regs,
1162 struct gfx11_reg_pair *reg_pairs)
1163 {
1164 unsigned reg_count = *num_regs;
1165
1166 if (!reg_count)
1167 return;
1168
1169 *num_regs = 0;
1170
1171 /* If there is only one register, we can't use the packed SET packet. */
1172 if (reg_count == 1) {
1173 radeon_begin(&sctx->gfx_cs);
1174 radeon_emit(PKT3(PKT3_SET_SH_REG, 1, 0));
1175 radeon_emit(reg_pairs[0].reg_offset[0]);
1176 radeon_emit(reg_pairs[0].reg_value[0]);
1177 radeon_end();
1178 return;
1179 }
1180
1181 unsigned packet = reg_count <= 14 ? PKT3_SET_SH_REG_PAIRS_PACKED_N :
1182 PKT3_SET_SH_REG_PAIRS_PACKED;
1183 unsigned padded_reg_count = align(reg_count, 2);
1184
1185 radeon_begin(&sctx->gfx_cs);
1186 radeon_emit(PKT3(packet, (padded_reg_count / 2) * 3, 0) | PKT3_RESET_FILTER_CAM_S(1));
1187 radeon_emit(padded_reg_count);
1188 radeon_emit_array(reg_pairs, (reg_count / 2) * 3);
1189
1190 if (reg_count % 2 == 1) {
1191 unsigned i = reg_count / 2;
1192
1193 /* Pad the packet by setting the first register again at the end because the register
1194 * count must be even and 2 consecutive offsets must not be equal.
1195 */
1196 radeon_emit(reg_pairs[i].reg_offset[0] | ((uint32_t)reg_pairs[0].reg_offset[0] << 16));
1197 radeon_emit(reg_pairs[i].reg_value[0]);
1198 radeon_emit(reg_pairs[0].reg_value[0]);
1199 }
1200 radeon_end();
1201 }
1202
1203 #define gfx12_emit_buffered_sh_regs_inline(num_regs, regs) do { \
1204 unsigned __reg_count = *(num_regs); \
1205 if (__reg_count) { \
1206 radeon_emit(PKT3(PKT3_SET_SH_REG_PAIRS, __reg_count * 2 - 1, 0) | PKT3_RESET_FILTER_CAM_S(1)); \
1207 radeon_emit_array(regs, __reg_count * 2); \
1208 *(num_regs) = 0; \
1209 } \
1210 } while (0)
1211
1212 #if GFX_VER == 6 /* declare this function only once because there is only one variant. */
1213
si_emit_buffered_compute_sh_regs(struct si_context * sctx)1214 void si_emit_buffered_compute_sh_regs(struct si_context *sctx)
1215 {
1216 if (sctx->gfx_level >= GFX12) {
1217 radeon_begin(&sctx->gfx_cs);
1218 gfx12_emit_buffered_sh_regs_inline(&sctx->num_buffered_compute_sh_regs,
1219 sctx->gfx12.buffered_compute_sh_regs);
1220 radeon_end();
1221 } else {
1222 gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_compute_sh_regs,
1223 sctx->gfx11.buffered_compute_sh_regs);
1224 }
1225 }
1226
1227 #endif
1228
1229 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1230 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED> ALWAYS_INLINE
si_emit_draw_packets(struct si_context * sctx,const struct pipe_draw_info * info,unsigned drawid_base,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,struct pipe_resource * indexbuf,unsigned index_size,unsigned index_offset,unsigned instance_count)1231 static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw_info *info,
1232 unsigned drawid_base,
1233 const struct pipe_draw_indirect_info *indirect,
1234 const struct pipe_draw_start_count_bias *draws,
1235 unsigned num_draws,
1236 struct pipe_resource *indexbuf, unsigned index_size,
1237 unsigned index_offset, unsigned instance_count)
1238 {
1239 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1240
1241 if (unlikely(sctx->sqtt_enabled)) {
1242 si_sqtt_write_event_marker(sctx, &sctx->gfx_cs, sctx->sqtt_next_event,
1243 UINT_MAX, UINT_MAX, UINT_MAX);
1244 }
1245
1246 uint32_t use_opaque = 0;
1247
1248 if (!IS_DRAW_VERTEX_STATE && indirect && indirect->count_from_stream_output) {
1249 struct si_streamout_target *t = (struct si_streamout_target *)indirect->count_from_stream_output;
1250
1251 radeon_begin(cs);
1252 radeon_set_context_reg(R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1253 radeon_end();
1254
1255 if (GFX_VERSION >= GFX9) {
1256 /* Use PKT3_LOAD_CONTEXT_REG_INDEX instead of si_cp_copy_data to support state shadowing. */
1257 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_draw_count_offset;
1258
1259 radeon_begin(cs);
1260
1261 // TODO: GFX12: This may be discarded by PFP if the shadow base address is provided by the MQD.
1262 radeon_emit(PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
1263 radeon_emit(va);
1264 radeon_emit(va >> 32);
1265 radeon_emit((R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE - SI_CONTEXT_REG_OFFSET) >> 2);
1266 radeon_emit(1);
1267
1268 radeon_end();
1269 } else {
1270 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_REG, NULL,
1271 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2, COPY_DATA_SRC_MEM,
1272 t->buf_filled_size, t->buf_filled_size_draw_count_offset);
1273 }
1274 use_opaque = S_0287F0_USE_OPAQUE(1);
1275 indirect = NULL;
1276 }
1277
1278 uint32_t index_max_size = 0;
1279 uint64_t index_va = 0;
1280 bool disable_instance_packing = false;
1281
1282 radeon_begin(cs);
1283
1284 if (GFX_VERSION == GFX10_3) {
1285 /* Workaround for incorrect stats with adjacent primitive types
1286 * (see PAL's waDisableInstancePacking).
1287 */
1288 if (sctx->num_pipeline_stat_queries &&
1289 sctx->shader.gs.cso == NULL &&
1290 (instance_count > 1 || indirect) &&
1291 (1 << info->mode) & (1 << MESA_PRIM_LINES_ADJACENCY |
1292 1 << MESA_PRIM_LINE_STRIP_ADJACENCY |
1293 1 << MESA_PRIM_TRIANGLES_ADJACENCY |
1294 1 << MESA_PRIM_TRIANGLE_STRIP_ADJACENCY)) {
1295 disable_instance_packing = true;
1296 }
1297 }
1298
1299 /* draw packet */
1300 if (index_size) {
1301 /* Register shadowing doesn't shadow INDEX_TYPE. */
1302 if (index_size != sctx->last_index_size ||
1303 (GFX_VERSION == GFX10_3 && disable_instance_packing != sctx->disable_instance_packing)) {
1304 unsigned index_type;
1305
1306 /* Index type computation. When we look at how we need to translate index_size,
1307 * we can see that we just need 2 shifts to get the hw value.
1308 *
1309 * 1 = 001b --> 10b = 2
1310 * 2 = 010b --> 00b = 0
1311 * 4 = 100b --> 01b = 1
1312 */
1313 index_type = (((index_size >> 2) | (index_size << 1)) & 0x3) |
1314 S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing);
1315
1316 if (GFX_VERSION <= GFX7 && UTIL_ARCH_BIG_ENDIAN) {
1317 /* GFX7 doesn't support ubyte indices. */
1318 index_type |= index_size == 2 ? V_028A7C_VGT_DMA_SWAP_16_BIT
1319 : V_028A7C_VGT_DMA_SWAP_32_BIT;
1320 }
1321
1322 if (GFX_VERSION >= GFX9) {
1323 radeon_set_uconfig_reg_idx(R_03090C_VGT_INDEX_TYPE, 2, index_type);
1324 } else {
1325 radeon_emit(PKT3(PKT3_INDEX_TYPE, 0, 0));
1326 radeon_emit(index_type);
1327 }
1328
1329 sctx->last_index_size = index_size;
1330 if (GFX_VERSION == GFX10_3)
1331 sctx->disable_instance_packing = disable_instance_packing;
1332 }
1333
1334 index_max_size = (indexbuf->width0 - index_offset) >> util_logbase2(index_size);
1335 /* Skip draw calls with 0-sized index buffers.
1336 * They cause a hang on some chips, like Navi10-14.
1337 */
1338 if (!index_max_size) {
1339 radeon_end();
1340 return;
1341 }
1342
1343 index_va = si_resource(indexbuf)->gpu_address + index_offset;
1344
1345 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indexbuf),
1346 RADEON_USAGE_READ | RADEON_PRIO_INDEX_BUFFER);
1347 } else {
1348 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
1349 * so the state must be re-emitted before the next indexed draw.
1350 */
1351 if (GFX_VERSION >= GFX7)
1352 sctx->last_index_size = -1;
1353 if (GFX_VERSION == GFX10_3 && disable_instance_packing != sctx->disable_instance_packing) {
1354 radeon_set_uconfig_reg_idx(R_03090C_VGT_INDEX_TYPE, 2,
1355 S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing));
1356 sctx->disable_instance_packing = disable_instance_packing;
1357 }
1358 }
1359
1360 unsigned sh_base_reg = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
1361 PIPE_SHADER_VERTEX);
1362 bool render_cond_bit = sctx->render_cond_enabled;
1363 unsigned tracked_base_vertex_reg;
1364
1365 if (HAS_TESS)
1366 tracked_base_vertex_reg = SI_TRACKED_SPI_SHADER_USER_DATA_LS__BASE_VERTEX;
1367 else if (HAS_GS || NGG)
1368 tracked_base_vertex_reg = SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX;
1369 else
1370 tracked_base_vertex_reg = SI_TRACKED_SPI_SHADER_USER_DATA_VS__BASE_VERTEX;
1371
1372 if (!IS_DRAW_VERTEX_STATE && indirect) {
1373 assert(num_draws == 1);
1374 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
1375
1376 assert(indirect_va % 8 == 0);
1377
1378 if (GFX_VERSION >= GFX12) {
1379 gfx12_emit_buffered_sh_regs_inline(&sctx->num_buffered_gfx_sh_regs,
1380 sctx->gfx12.buffered_gfx_sh_regs);
1381 } else if (HAS_SH_PAIRS_PACKED) {
1382 radeon_end();
1383 gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_gfx_sh_regs,
1384 sctx->gfx11.buffered_gfx_sh_regs);
1385 radeon_begin_again(cs);
1386 }
1387
1388 /* Invalidate tracked draw constants because DrawIndirect overwrites them. */
1389 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1390 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1391 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 2); /* StartInstance */
1392 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1393
1394 radeon_emit(PKT3(PKT3_SET_BASE, 2, 0));
1395 radeon_emit(1);
1396 radeon_emit(indirect_va);
1397 radeon_emit(indirect_va >> 32);
1398
1399 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indirect->buffer),
1400 RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
1401
1402 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
1403
1404 assert(indirect->offset % 4 == 0);
1405
1406 if (index_size) {
1407 radeon_emit(PKT3(PKT3_INDEX_BASE, 1, 0));
1408 radeon_emit(index_va);
1409 radeon_emit(index_va >> 32);
1410
1411 radeon_emit(PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1412 radeon_emit(index_max_size);
1413 }
1414
1415 if (!sctx->screen->has_draw_indirect_multi) {
1416 radeon_emit(PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT : PKT3_DRAW_INDIRECT, 3,
1417 render_cond_bit));
1418 radeon_emit(indirect->offset);
1419 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1420 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1421 radeon_emit(di_src_sel);
1422 } else {
1423 uint64_t count_va = 0;
1424
1425 if (indirect->indirect_draw_count) {
1426 struct si_resource *params_buf = si_resource(indirect->indirect_draw_count);
1427
1428 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, params_buf,
1429 RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
1430
1431 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
1432 }
1433
1434 radeon_emit(PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI : PKT3_DRAW_INDIRECT_MULTI, 8,
1435 render_cond_bit));
1436 radeon_emit(indirect->offset);
1437 radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
1438 radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
1439 radeon_emit(((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
1440 S_2C3_DRAW_INDEX_ENABLE(sctx->shader.vs.cso->info.uses_drawid) |
1441 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
1442 radeon_emit(indirect->draw_count);
1443 radeon_emit(count_va);
1444 radeon_emit(count_va >> 32);
1445 radeon_emit(indirect->stride);
1446 radeon_emit(di_src_sel);
1447 }
1448 } else {
1449 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
1450 sctx->last_instance_count != instance_count) {
1451 radeon_emit(PKT3(PKT3_NUM_INSTANCES, 0, 0));
1452 radeon_emit(instance_count);
1453 sctx->last_instance_count = instance_count;
1454 }
1455
1456 /* Base vertex and start instance. */
1457 int base_vertex = index_size ? draws[0].index_bias : draws[0].start;
1458
1459 bool set_draw_id = !IS_DRAW_VERTEX_STATE && sctx->vs_uses_draw_id;
1460 bool set_base_instance = sctx->vs_uses_base_instance;
1461 bool is_blit = !IS_DRAW_VERTEX_STATE && sctx->num_vs_blit_sgprs;
1462
1463 if (!is_blit) {
1464 /* Prefer SET_SH_REG_PAIRS_PACKED* on Gfx11+. */
1465 if (GFX_VERSION >= GFX12) {
1466 gfx12_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1467 tracked_base_vertex_reg, base_vertex);
1468 if (set_draw_id) {
1469 gfx12_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_DRAWID * 4,
1470 tracked_base_vertex_reg + 1, drawid_base);
1471 }
1472 if (set_base_instance) {
1473 gfx12_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_START_INSTANCE * 4,
1474 tracked_base_vertex_reg + 2, info->start_instance);
1475 }
1476 } else if (HAS_SH_PAIRS_PACKED) {
1477 gfx11_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1478 tracked_base_vertex_reg, base_vertex);
1479 if (set_draw_id) {
1480 gfx11_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_DRAWID * 4,
1481 tracked_base_vertex_reg + 1, drawid_base);
1482 }
1483 if (set_base_instance) {
1484 gfx11_opt_push_gfx_sh_reg(sh_base_reg + SI_SGPR_START_INSTANCE * 4,
1485 tracked_base_vertex_reg + 2, info->start_instance);
1486 }
1487 } else {
1488 if (set_base_instance) {
1489 radeon_opt_set_sh_reg3(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1490 tracked_base_vertex_reg, base_vertex, drawid_base,
1491 info->start_instance);
1492 } else if (set_draw_id) {
1493 radeon_opt_set_sh_reg2(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1494 tracked_base_vertex_reg, base_vertex, drawid_base);
1495 } else {
1496 radeon_opt_set_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
1497 tracked_base_vertex_reg, base_vertex);
1498 }
1499 }
1500 }
1501
1502 if (GFX_VERSION >= GFX12) {
1503 gfx12_emit_buffered_sh_regs_inline(&sctx->num_buffered_gfx_sh_regs,
1504 sctx->gfx12.buffered_gfx_sh_regs);
1505 } else if (HAS_SH_PAIRS_PACKED) {
1506 radeon_end();
1507 gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->num_buffered_gfx_sh_regs,
1508 sctx->gfx11.buffered_gfx_sh_regs);
1509 radeon_begin_again(cs);
1510 }
1511
1512 /* Blit SGPRs must be set after gfx1X_emit_buffered_sh_regs_inline because they can
1513 * overwrite them.
1514 */
1515 if (is_blit) {
1516 /* Re-emit draw constants after we leave u_blitter. */
1517 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1518 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1519 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 2); /* StartInstance */
1520
1521 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
1522 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs);
1523 radeon_emit_array(sctx->vs_blit_sh_data, sctx->num_vs_blit_sgprs);
1524 }
1525
1526 /* Don't update draw_id in the following code if it doesn't increment. */
1527 bool increment_draw_id = !IS_DRAW_VERTEX_STATE && num_draws > 1 &&
1528 set_draw_id && info->increment_draw_id;
1529
1530 if (index_size) {
1531 /* NOT_EOP allows merging multiple draws into 1 wave, but only user VGPRs
1532 * can be changed between draws, and GS fast launch must be disabled.
1533 * NOT_EOP doesn't work on gfx9 and older.
1534 *
1535 * Instead of doing this, which evaluates the case conditions repeatedly:
1536 * for (all draws) {
1537 * if (case1);
1538 * else;
1539 * }
1540 *
1541 * Use this structuring to evaluate the case conditions once:
1542 * if (case1) for (all draws);
1543 * else for (all draws);
1544 *
1545 */
1546 bool index_bias_varies = !IS_DRAW_VERTEX_STATE && num_draws > 1 &&
1547 info->index_bias_varies;
1548
1549 if (increment_draw_id) {
1550 if (index_bias_varies) {
1551 for (unsigned i = 0; i < num_draws; i++) {
1552 uint64_t va = index_va + draws[i].start * index_size;
1553
1554 if (i > 0) {
1555 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1556 radeon_emit(draws[i].index_bias);
1557 radeon_emit(drawid_base + i);
1558 }
1559
1560 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1561 radeon_emit(index_max_size);
1562 radeon_emit(va);
1563 radeon_emit(va >> 32);
1564 radeon_emit(draws[i].count);
1565 radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */
1566 }
1567 if (num_draws > 1) {
1568 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1569 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1570 }
1571 } else {
1572 /* Only DrawID varies. */
1573 for (unsigned i = 0; i < num_draws; i++) {
1574 uint64_t va = index_va + draws[i].start * index_size;
1575
1576 if (i > 0)
1577 radeon_set_sh_reg(sh_base_reg + SI_SGPR_DRAWID * 4, drawid_base + i);
1578
1579 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1580 radeon_emit(index_max_size);
1581 radeon_emit(va);
1582 radeon_emit(va >> 32);
1583 radeon_emit(draws[i].count);
1584 radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */
1585 }
1586 if (num_draws > 1) {
1587 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1588 }
1589 }
1590 } else {
1591 if (index_bias_varies) {
1592 /* Only BaseVertex varies. */
1593 for (unsigned i = 0; i < num_draws; i++) {
1594 uint64_t va = index_va + draws[i].start * index_size;
1595
1596 if (i > 0)
1597 radeon_set_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, draws[i].index_bias);
1598
1599 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1600 radeon_emit(index_max_size);
1601 radeon_emit(va);
1602 radeon_emit(va >> 32);
1603 radeon_emit(draws[i].count);
1604 radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */
1605 }
1606 if (num_draws > 1) {
1607 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1608 }
1609 } else {
1610 /* DrawID and BaseVertex are constant. */
1611 if (GFX_VERSION == GFX10) {
1612 /* GFX10 has a bug that consecutive draw packets with NOT_EOP must not have
1613 * count == 0 in the last draw (which doesn't set NOT_EOP).
1614 *
1615 * So remove all trailing draws with count == 0.
1616 */
1617 while (num_draws > 1 && !draws[num_draws - 1].count)
1618 num_draws--;
1619 }
1620
1621 for (unsigned i = 0; i < num_draws; i++) {
1622 uint64_t va = index_va + draws[i].start * index_size;
1623
1624 radeon_emit(PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1625 radeon_emit(index_max_size);
1626 radeon_emit(va);
1627 radeon_emit(va >> 32);
1628 radeon_emit(draws[i].count);
1629 radeon_emit(V_0287F0_DI_SRC_SEL_DMA |
1630 S_0287F0_NOT_EOP(GFX_VERSION >= GFX10 && GFX_VERSION < GFX12 &&
1631 i < num_draws - 1));
1632 }
1633 }
1634 }
1635 } else {
1636 if (GFX_VERSION == GFX12 && !IS_DRAW_VERTEX_STATE &&
1637 indirect && indirect->count_from_stream_output) {
1638 /* DrawTransformFeedback requires 3 SQ_NON_EVENTs after the packet. */
1639 assert(num_draws == 1);
1640
1641 radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1642 radeon_emit(0);
1643 radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);
1644
1645 for (unsigned i = 0; i < 3; i++)
1646 radeon_event_write(V_028A90_SQ_NON_EVENT);
1647 } else if (increment_draw_id) {
1648 for (unsigned i = 0; i < num_draws; i++) {
1649 if (i > 0) {
1650 unsigned draw_id = drawid_base + i;
1651
1652 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1653 radeon_emit(draws[i].start);
1654 radeon_emit(draw_id);
1655 }
1656
1657 radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1658 radeon_emit(draws[i].count);
1659 radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);
1660 }
1661 if (num_draws > 1 && (IS_DRAW_VERTEX_STATE || !sctx->num_vs_blit_sgprs)) {
1662 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1663 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */
1664 }
1665 } else {
1666 for (unsigned i = 0; i < num_draws; i++) {
1667 if (i > 0)
1668 radeon_set_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, draws[i].start);
1669
1670 radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1671 radeon_emit(draws[i].count);
1672 radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);
1673 }
1674 if (num_draws > 1 && (IS_DRAW_VERTEX_STATE || !sctx->num_vs_blit_sgprs)) {
1675 BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */
1676 }
1677 }
1678 }
1679 }
1680
1681 if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt_enabled))
1682 radeon_event_write(V_028A90_THREAD_TRACE_MARKER);
1683 radeon_end();
1684 }
1685
1686 /* Return false if not bound. */
1687 template<amd_gfx_level GFX_VERSION>
si_set_vb_descriptor(struct si_vertex_elements * velems,const struct pipe_vertex_buffer * vb,unsigned index,uint32_t * desc)1688 static void ALWAYS_INLINE si_set_vb_descriptor(struct si_vertex_elements *velems,
1689 const struct pipe_vertex_buffer *vb,
1690 unsigned index, /* vertex element index */
1691 uint32_t *desc) /* where to upload descriptors */
1692 {
1693 struct si_resource *buf = si_resource(vb->buffer.resource);
1694 int64_t offset = (int64_t)((int)vb->buffer_offset) + velems->elem[index].src_offset;
1695
1696 if (!buf || offset >= buf->b.b.width0) {
1697 memset(desc, 0, 16);
1698 return;
1699 }
1700
1701 uint64_t va = buf->gpu_address + offset;
1702 unsigned stride = velems->elem[index].stride;
1703
1704 int64_t num_records = (int64_t)buf->b.b.width0 - offset;
1705 if (GFX_VERSION != GFX8 && stride) {
1706 /* Round up by rounding down and adding 1 */
1707 num_records = (num_records - velems->elem[index].format_size) / stride + 1;
1708 }
1709 assert(num_records >= 0 && num_records <= UINT_MAX);
1710
1711 desc[0] = va;
1712 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1713 desc[2] = num_records;
1714 desc[3] = velems->elem[index].rsrc_word3;
1715 }
1716
1717 #if GFX_VER == 6 /* declare this function only once because it supports all chips. */
1718
si_set_vertex_buffer_descriptor(struct si_screen * sscreen,struct si_vertex_elements * velems,const struct pipe_vertex_buffer * vb,unsigned element_index,uint32_t * out)1719 void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
1720 const struct pipe_vertex_buffer *vb, unsigned element_index,
1721 uint32_t *out)
1722 {
1723 switch (sscreen->info.gfx_level) {
1724 case GFX6:
1725 si_set_vb_descriptor<GFX6>(velems, vb, element_index, out);
1726 break;
1727 case GFX7:
1728 si_set_vb_descriptor<GFX7>(velems, vb, element_index, out);
1729 break;
1730 case GFX8:
1731 si_set_vb_descriptor<GFX8>(velems, vb, element_index, out);
1732 break;
1733 case GFX9:
1734 si_set_vb_descriptor<GFX9>(velems, vb, element_index, out);
1735 break;
1736 case GFX10:
1737 si_set_vb_descriptor<GFX10>(velems, vb, element_index, out);
1738 break;
1739 case GFX10_3:
1740 si_set_vb_descriptor<GFX10_3>(velems, vb, element_index, out);
1741 break;
1742 case GFX11:
1743 si_set_vb_descriptor<GFX11>(velems, vb, element_index, out);
1744 break;
1745 case GFX11_5:
1746 si_set_vb_descriptor<GFX11_5>(velems, vb, element_index, out);
1747 break;
1748 case GFX12:
1749 si_set_vb_descriptor<GFX12>(velems, vb, element_index, out);
1750 break;
1751 default:
1752 unreachable("unhandled gfx level");
1753 }
1754 }
1755
1756 #endif
1757
1758 template<util_popcnt POPCNT>
get_next_vertex_state_elem(struct pipe_vertex_state * state,uint32_t * partial_velem_mask)1759 static ALWAYS_INLINE unsigned get_next_vertex_state_elem(struct pipe_vertex_state *state,
1760 uint32_t *partial_velem_mask)
1761 {
1762 unsigned semantic_index = u_bit_scan(partial_velem_mask);
1763 assert(state->input.full_velem_mask & BITFIELD_BIT(semantic_index));
1764 /* A prefix mask of the full mask gives us the index in pipe_vertex_state. */
1765 return util_bitcount_fast<POPCNT>(state->input.full_velem_mask & BITFIELD_MASK(semantic_index));
1766 }
1767
1768 template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
get_vb_descriptor_sgpr_ptr_offset(void)1769 static unsigned get_vb_descriptor_sgpr_ptr_offset(void)
1770 {
1771 /* Find the location of the VB descriptor pointer. */
1772 unsigned dw_offset = SI_VS_NUM_USER_SGPR;
1773 if (GFX_VERSION >= GFX9) {
1774 if (HAS_TESS)
1775 dw_offset = GFX9_TCS_NUM_USER_SGPR;
1776 else if (HAS_GS || NGG)
1777 dw_offset = GFX9_GS_NUM_USER_SGPR;
1778 }
1779 return dw_offset * 4;
1780 }
1781
1782 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1783 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED,
1784 util_popcnt POPCNT> ALWAYS_INLINE
si_upload_and_prefetch_VB_descriptors(struct si_context * sctx,struct pipe_vertex_state * state,uint32_t partial_velem_mask)1785 static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx,
1786 struct pipe_vertex_state *state,
1787 uint32_t partial_velem_mask)
1788 {
1789 struct si_vertex_state *vstate = (struct si_vertex_state *)state;
1790 unsigned count = IS_DRAW_VERTEX_STATE ? util_bitcount_fast<POPCNT>(partial_velem_mask) :
1791 sctx->num_vertex_elements;
1792 unsigned sh_base = si_get_user_data_base(GFX_VERSION, HAS_TESS, HAS_GS, NGG,
1793 PIPE_SHADER_VERTEX);
1794 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs_inline(GFX_VERSION);
1795
1796 assert(count <= SI_MAX_ATTRIBS);
1797
1798 if (sctx->vertex_buffers_dirty || IS_DRAW_VERTEX_STATE) {
1799 assert(count || IS_DRAW_VERTEX_STATE);
1800
1801 struct si_vertex_elements *velems = sctx->vertex_elements;
1802 unsigned alloc_size = IS_DRAW_VERTEX_STATE ?
1803 vstate->velems.vb_desc_list_alloc_size :
1804 velems->vb_desc_list_alloc_size;
1805 uint64_t vb_descriptors_address = 0;
1806 uint32_t *ptr;
1807
1808 if (alloc_size) {
1809 unsigned offset;
1810
1811 /* Vertex buffer descriptors are the only ones which are uploaded directly
1812 * and don't go through si_upload_graphics_shader_descriptors.
1813 */
1814 u_upload_alloc(sctx->b.const_uploader, 0, alloc_size,
1815 si_optimal_tcc_alignment(sctx, alloc_size), &offset,
1816 (struct pipe_resource **)&sctx->last_const_upload_buffer, (void **)&ptr);
1817 if (!sctx->last_const_upload_buffer)
1818 return false;
1819
1820 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->last_const_upload_buffer,
1821 RADEON_USAGE_READ | RADEON_PRIO_DESCRIPTORS);
1822 vb_descriptors_address = sctx->last_const_upload_buffer->gpu_address + offset;
1823
1824 /* GFX6 doesn't support the L2 prefetch. */
1825 if (GFX_VERSION >= GFX7) {
1826 uint64_t address = sctx->last_const_upload_buffer->gpu_address + offset;
1827 si_cp_dma_prefetch_inline<GFX_VERSION>(sctx, address, alloc_size);
1828 }
1829 }
1830
1831 unsigned count_in_user_sgprs = MIN2(count, num_vbos_in_user_sgprs);
1832 unsigned i = 0;
1833
1834 if (IS_DRAW_VERTEX_STATE) {
1835 radeon_begin(&sctx->gfx_cs);
1836
1837 if (count_in_user_sgprs) {
1838 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, count_in_user_sgprs * 4);
1839
1840 /* the first iteration always executes */
1841 do {
1842 unsigned velem_index = get_next_vertex_state_elem<POPCNT>(state, &partial_velem_mask);
1843
1844 radeon_emit_array(&vstate->descriptors[velem_index * 4], 4);
1845 } while (++i < count_in_user_sgprs);
1846 }
1847
1848 if (partial_velem_mask) {
1849 assert(alloc_size);
1850
1851 unsigned vb_desc_offset =
1852 sh_base + get_vb_descriptor_sgpr_ptr_offset<GFX_VERSION, HAS_TESS, HAS_GS, NGG>();
1853
1854 radeon_set_or_push_gfx_sh_reg(vb_desc_offset, vb_descriptors_address);
1855
1856 /* the first iteration always executes */
1857 do {
1858 unsigned velem_index = get_next_vertex_state_elem<POPCNT>(state, &partial_velem_mask);
1859 uint32_t *desc = &ptr[(i - num_vbos_in_user_sgprs) * 4];
1860
1861 memcpy(desc, &vstate->descriptors[velem_index * 4], 16);
1862 i++;
1863 } while (partial_velem_mask);
1864 }
1865 radeon_end();
1866
1867 if (vstate->b.input.vbuffer.buffer.resource != vstate->b.input.indexbuf) {
1868 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs,
1869 si_resource(vstate->b.input.vbuffer.buffer.resource),
1870 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER);
1871 }
1872
1873 /* The next draw_vbo should recompute and rebind vertex buffer descriptors. */
1874 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
1875 } else {
1876 if (count_in_user_sgprs) {
1877 radeon_begin(&sctx->gfx_cs);
1878 radeon_set_sh_reg_seq(sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4,
1879 count_in_user_sgprs * 4);
1880
1881 /* the first iteration always executes */
1882 do {
1883 unsigned vbo_index = velems->vertex_buffer_index[i];
1884 const struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbo_index];
1885 uint32_t *desc;
1886
1887 radeon_emit_array_get_ptr(4, &desc);
1888
1889 si_set_vb_descriptor<GFX_VERSION>(velems, vb, i, desc);
1890 } while (++i < count_in_user_sgprs);
1891
1892 radeon_end();
1893 }
1894
1895 if (alloc_size) {
1896 /* the first iteration always executes */
1897 do {
1898 unsigned vbo_index = velems->vertex_buffer_index[i];
1899 const struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbo_index];
1900 uint32_t *desc = &ptr[(i - num_vbos_in_user_sgprs) * 4];
1901
1902 si_set_vb_descriptor<GFX_VERSION>(velems, vb, i, desc);
1903 } while (++i < count);
1904
1905 unsigned vb_desc_ptr_offset =
1906 sh_base + get_vb_descriptor_sgpr_ptr_offset<GFX_VERSION, HAS_TESS, HAS_GS, NGG>();
1907 radeon_begin(&sctx->gfx_cs);
1908 radeon_set_or_push_gfx_sh_reg(vb_desc_ptr_offset, vb_descriptors_address);
1909 radeon_end();
1910 }
1911
1912 sctx->vertex_buffers_dirty = false;
1913 }
1914 }
1915
1916 return true;
1917 }
1918
si_get_draw_start_count(struct si_context * sctx,const struct pipe_draw_info * info,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,unsigned * start,unsigned * count)1919 static void si_get_draw_start_count(struct si_context *sctx, const struct pipe_draw_info *info,
1920 const struct pipe_draw_indirect_info *indirect,
1921 const struct pipe_draw_start_count_bias *draws,
1922 unsigned num_draws, unsigned *start, unsigned *count)
1923 {
1924 if (indirect && !indirect->count_from_stream_output) {
1925 unsigned indirect_count;
1926 struct pipe_transfer *transfer;
1927 unsigned begin, end;
1928 unsigned map_size;
1929 unsigned *data;
1930
1931 if (indirect->indirect_draw_count) {
1932 data = (unsigned*)
1933 pipe_buffer_map_range(&sctx->b, indirect->indirect_draw_count,
1934 indirect->indirect_draw_count_offset, sizeof(unsigned),
1935 PIPE_MAP_READ, &transfer);
1936
1937 indirect_count = *data;
1938
1939 pipe_buffer_unmap(&sctx->b, transfer);
1940 } else {
1941 indirect_count = indirect->draw_count;
1942 }
1943
1944 if (!indirect_count) {
1945 *start = *count = 0;
1946 return;
1947 }
1948
1949 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1950 data = (unsigned*)
1951 pipe_buffer_map_range(&sctx->b, indirect->buffer, indirect->offset, map_size,
1952 PIPE_MAP_READ, &transfer);
1953
1954 begin = UINT_MAX;
1955 end = 0;
1956
1957 for (unsigned i = 0; i < indirect_count; ++i) {
1958 unsigned count = data[0];
1959 unsigned start = data[2];
1960
1961 if (count > 0) {
1962 begin = MIN2(begin, start);
1963 end = MAX2(end, start + count);
1964 }
1965
1966 data += indirect->stride / sizeof(unsigned);
1967 }
1968
1969 pipe_buffer_unmap(&sctx->b, transfer);
1970
1971 if (begin < end) {
1972 *start = begin;
1973 *count = end - begin;
1974 } else {
1975 *start = *count = 0;
1976 }
1977 } else {
1978 unsigned min_element = UINT_MAX;
1979 unsigned max_element = 0;
1980
1981 for (unsigned i = 0; i < num_draws; i++) {
1982 min_element = MIN2(min_element, draws[i].start);
1983 max_element = MAX2(max_element, draws[i].start + draws[i].count);
1984 }
1985
1986 *start = min_element;
1987 *count = max_element - min_element;
1988 }
1989 }
1990
1991 ALWAYS_INLINE
si_emit_all_states(struct si_context * sctx,uint64_t skip_atom_mask)1992 static void si_emit_all_states(struct si_context *sctx, uint64_t skip_atom_mask)
1993 {
1994 /* Emit states by calling their emit functions. */
1995 uint64_t dirty = sctx->dirty_atoms & ~skip_atom_mask;
1996
1997 if (dirty) {
1998 sctx->dirty_atoms &= skip_atom_mask;
1999
2000 /* u_bit_scan64 is too slow on i386. */
2001 if (sizeof(void*) == 8) {
2002 do {
2003 unsigned i = u_bit_scan64(&dirty);
2004 sctx->atoms.array[i].emit(sctx, i);
2005 } while (dirty);
2006 } else {
2007 unsigned dirty_lo = dirty;
2008 unsigned dirty_hi = dirty >> 32;
2009
2010 while (dirty_lo) {
2011 unsigned i = u_bit_scan(&dirty_lo);
2012 sctx->atoms.array[i].emit(sctx, i);
2013 }
2014 while (dirty_hi) {
2015 unsigned i = 32 + u_bit_scan(&dirty_hi);
2016 sctx->atoms.array[i].emit(sctx, i);
2017 }
2018 }
2019 }
2020 }
2021
2022 #define DRAW_CLEANUP do { \
2023 if (index_size && indexbuf != info->index.resource) \
2024 pipe_resource_reference(&indexbuf, NULL); \
2025 } while (0)
2026
2027 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
2028 si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED,
2029 util_popcnt POPCNT> ALWAYS_INLINE
si_draw(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,struct pipe_vertex_state * state,uint32_t partial_velem_mask)2030 static void si_draw(struct pipe_context *ctx,
2031 const struct pipe_draw_info *info,
2032 unsigned drawid_offset,
2033 const struct pipe_draw_indirect_info *indirect,
2034 const struct pipe_draw_start_count_bias *draws,
2035 unsigned num_draws,
2036 struct pipe_vertex_state *state,
2037 uint32_t partial_velem_mask)
2038 {
2039 /* Keep code that uses the least number of local variables as close to the beginning
2040 * of this function as possible to minimize register pressure.
2041 *
2042 * It doesn't matter where we return due to invalid parameters because such cases
2043 * shouldn't occur in practice.
2044 */
2045 struct si_context *sctx = (struct si_context *)ctx;
2046
2047 si_check_dirty_buffers_textures(sctx);
2048
2049 if (GFX_VERSION < GFX11)
2050 gfx6_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
2051 else if (GFX_VERSION < GFX12)
2052 gfx11_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
2053
2054 si_need_gfx_cs_space(sctx, num_draws);
2055
2056 if (u_trace_perfetto_active(&sctx->ds.trace_context))
2057 trace_si_begin_draw(&sctx->trace);
2058
2059 unsigned instance_count = info->instance_count;
2060
2061 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
2062 * no workaround for indirect draws, but we can at least skip
2063 * direct draws.
2064 * 'instance_count == 0' seems to be problematic on Renoir chips (#4866),
2065 * so simplify the condition and drop these draws for all <= GFX9 chips.
2066 */
2067 if (GFX_VERSION <= GFX9 && unlikely(!IS_DRAW_VERTEX_STATE && !indirect && !instance_count))
2068 return;
2069
2070 struct si_shader_selector *vs = sctx->shader.vs.cso;
2071 struct si_vertex_state *vstate = (struct si_vertex_state *)state;
2072 if (unlikely(!vs ||
2073 (!IS_DRAW_VERTEX_STATE && sctx->num_vertex_elements < vs->info.num_vs_inputs) ||
2074 (IS_DRAW_VERTEX_STATE && vstate->velems.count < vs->info.num_vs_inputs) ||
2075 !sctx->shader.ps.cso || (HAS_TESS != (info->mode == MESA_PRIM_PATCHES)))) {
2076 assert(0);
2077 return;
2078 }
2079
2080 enum mesa_prim prim = HAS_TESS ? MESA_PRIM_PATCHES : (enum mesa_prim)info->mode;
2081
2082 if (GFX_VERSION <= GFX9 && HAS_GS) {
2083 /* Determine whether the GS triangle strip adjacency fix should
2084 * be applied. Rotate every other triangle if triangle strips with
2085 * adjacency are fed to the GS. This doesn't work if primitive
2086 * restart occurs after an odd number of triangles.
2087 */
2088 bool gs_tri_strip_adj_fix =
2089 !HAS_TESS && prim == MESA_PRIM_TRIANGLE_STRIP_ADJACENCY;
2090
2091 if (gs_tri_strip_adj_fix != sctx->shader.gs.key.ge.mono.u.gs_tri_strip_adj_fix) {
2092 sctx->shader.gs.key.ge.mono.u.gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
2093 sctx->do_update_shaders = true;
2094 }
2095 }
2096
2097 struct pipe_resource *indexbuf = info->index.resource;
2098 unsigned index_size = info->index_size;
2099 unsigned index_offset = indirect && indirect->buffer ? draws[0].start * index_size : 0;
2100
2101 if (index_size) {
2102 /* Translate or upload, if needed. */
2103 /* 8-bit indices are supported on GFX8. */
2104 if (!IS_DRAW_VERTEX_STATE && GFX_VERSION <= GFX7 && index_size == 1) {
2105 unsigned start, count, start_offset, size;
2106
2107 si_get_draw_start_count(sctx, info, indirect, draws, num_draws, &start, &count);
2108 start_offset = start * 2;
2109 size = count * 2;
2110
2111 /* Don't use u_upload_alloc because we don't need to map the buffer for CPU access. */
2112 indexbuf = pipe_buffer_create(&sctx->screen->b, 0, PIPE_USAGE_IMMUTABLE, start_offset + size);
2113 if (unlikely(!indexbuf))
2114 return;
2115
2116 si_compute_shorten_ubyte_buffer(sctx, indexbuf, info->index.resource, start_offset,
2117 index_offset + start, count, sctx->render_cond_enabled);
2118 si_barrier_after_simple_buffer_op(sctx, 0, indexbuf, info->index.resource);
2119
2120 index_offset = 0;
2121 index_size = 2;
2122
2123 /* GFX6-7 don't read index buffers through L2. */
2124 sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME;
2125 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
2126 si_resource(indexbuf)->L2_cache_dirty = false;
2127 } else if (!IS_DRAW_VERTEX_STATE && info->has_user_indices) {
2128 unsigned start_offset;
2129
2130 assert(!indirect);
2131 assert(num_draws == 1);
2132 start_offset = draws[0].start * index_size;
2133
2134 indexbuf = NULL;
2135 u_upload_data(ctx->stream_uploader, start_offset, draws[0].count * index_size,
2136 sctx->screen->info.tcc_cache_line_size,
2137 (char *)info->index.user + start_offset, &index_offset, &indexbuf);
2138 if (unlikely(!indexbuf))
2139 return;
2140
2141 /* info->start will be added by the drawing code */
2142 index_offset -= start_offset;
2143 } else if ((GFX_VERSION <= GFX7 || GFX_VERSION == GFX12) &&
2144 si_resource(indexbuf)->L2_cache_dirty) {
2145 /* GFX8-GFX11 reads index buffers through L2, so it doesn't
2146 * need this. */
2147 sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME;
2148 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
2149 si_resource(indexbuf)->L2_cache_dirty = false;
2150 }
2151 }
2152
2153 unsigned min_direct_count = 0;
2154 unsigned total_direct_count = 0;
2155
2156 if (!IS_DRAW_VERTEX_STATE && indirect) {
2157 /* Indirect buffers use L2 on GFX9-GFX11, but not other hw. */
2158 if (GFX_VERSION <= GFX8 || GFX_VERSION == GFX12) {
2159 if (indirect->buffer && si_resource(indirect->buffer)->L2_cache_dirty) {
2160 sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME;
2161 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
2162 si_resource(indirect->buffer)->L2_cache_dirty = false;
2163 }
2164
2165 if (indirect->indirect_draw_count &&
2166 si_resource(indirect->indirect_draw_count)->L2_cache_dirty) {
2167 sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME;
2168 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
2169 si_resource(indirect->indirect_draw_count)->L2_cache_dirty = false;
2170 }
2171 }
2172 total_direct_count = INT_MAX; /* just set something other than 0 to enable shader culling */
2173 } else {
2174 total_direct_count = min_direct_count = draws[0].count;
2175
2176 for (unsigned i = 1; i < num_draws; i++) {
2177 unsigned count = draws[i].count;
2178
2179 total_direct_count += count;
2180 min_direct_count = MIN2(min_direct_count, count);
2181 }
2182 }
2183
2184 /* Set the rasterization primitive type.
2185 *
2186 * This must be done after si_decompress_textures, which can call
2187 * draw_vbo recursively, and before si_update_shaders, which uses
2188 * current_rast_prim for this draw_vbo call.
2189 */
2190 if (!HAS_GS && !HAS_TESS) {
2191 enum mesa_prim rast_prim;
2192
2193 if (util_rast_prim_is_triangles(prim)) {
2194 rast_prim = MESA_PRIM_TRIANGLES;
2195 } else {
2196 /* Only possibilities, POINTS, LINE*, RECTANGLES */
2197 rast_prim = prim;
2198 }
2199
2200 si_set_rasterized_prim(sctx, rast_prim, si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current,
2201 NGG);
2202 }
2203
2204 if (IS_DRAW_VERTEX_STATE) {
2205 /* draw_vertex_state doesn't use the current vertex buffers and vertex elements,
2206 * so disable all VS input lowering.
2207 */
2208 if (!sctx->force_trivial_vs_inputs) {
2209 sctx->force_trivial_vs_inputs = true;
2210
2211 /* Update shaders to disable VS input lowering. */
2212 if (sctx->uses_nontrivial_vs_inputs) {
2213 si_vs_key_update_inputs(sctx);
2214 sctx->do_update_shaders = true;
2215 }
2216 }
2217 } else {
2218 if (sctx->force_trivial_vs_inputs) {
2219 sctx->force_trivial_vs_inputs = false;
2220
2221 /* Update shaders to possibly enable VS input lowering. */
2222 if (sctx->uses_nontrivial_vs_inputs) {
2223 si_vs_key_update_inputs(sctx);
2224 sctx->do_update_shaders = true;
2225 }
2226 }
2227 }
2228
2229 /* Update NGG culling settings. */
2230 uint16_t old_ngg_culling = sctx->ngg_culling;
2231 if (GFX_VERSION >= GFX10) {
2232 struct si_shader_selector *hw_vs = si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->cso;
2233
2234 if (NGG &&
2235 /* Tessellation and GS set ngg_cull_vert_threshold to UINT_MAX if the prim type
2236 * is not points, so this check is only needed for VS. */
2237 (HAS_TESS || HAS_GS || util_rast_prim_is_lines_or_triangles(sctx->current_rast_prim)) &&
2238 /* Only the first draw for a shader starts with culling disabled and it's disabled
2239 * until we pass the total_direct_count check and then it stays enabled until
2240 * the shader is changed. This eliminates most culling on/off state changes. */
2241 (old_ngg_culling || total_direct_count > hw_vs->ngg_cull_vert_threshold)) {
2242 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2243
2244 /* Check that the current shader allows culling. */
2245 assert(hw_vs->ngg_cull_vert_threshold != UINT_MAX);
2246
2247 uint16_t ngg_culling;
2248
2249 if (util_prim_is_lines(sctx->current_rast_prim)) {
2250 /* Overwrite it to mask out face cull flags. */
2251 ngg_culling = rs->ngg_cull_flags_lines;
2252 } else {
2253 ngg_culling = sctx->viewport0_y_inverted ? rs->ngg_cull_flags_tris_y_inverted :
2254 rs->ngg_cull_flags_tris;
2255 assert(ngg_culling); /* rasterizer state should always set this to non-zero */
2256 }
2257
2258 if (ngg_culling != old_ngg_culling) {
2259 /* If shader compilation is not ready, this setting will be rejected. */
2260 sctx->ngg_culling = ngg_culling;
2261 sctx->do_update_shaders = true;
2262 }
2263 } else if (old_ngg_culling) {
2264 sctx->ngg_culling = 0;
2265 sctx->do_update_shaders = true;
2266 }
2267 }
2268
2269 if (unlikely(sctx->do_update_shaders)) {
2270 if (unlikely(!(si_update_shaders<GFX_VERSION, HAS_TESS, HAS_GS, NGG>(sctx)))) {
2271 DRAW_CLEANUP;
2272 return;
2273 }
2274 }
2275
2276 /* This is the optimal packet order:
2277 * Set all states first, so that all SET packets are processed in parallel with previous
2278 * draw calls. Then flush caches and wait if needed. Then draw and prefetch at the end.
2279 * It's better to draw before prefetches because we want to start fetching indices before
2280 * shaders. The idea is to minimize the time when the CUs are idle.
2281 */
2282
2283 /* Vega10/Raven scissor bug workaround. When any context register is
2284 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2285 * registers must be written too.
2286 */
2287 bool gfx9_scissor_bug = false;
2288 uint64_t masked_atoms = 0;
2289
2290 if (GFX_VERSION == GFX9 && sctx->screen->info.has_gfx9_scissor_bug) {
2291 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2292 gfx9_scissor_bug = true;
2293
2294 if ((!IS_DRAW_VERTEX_STATE && indirect && indirect->count_from_stream_output) ||
2295 sctx->dirty_atoms & si_atoms_that_always_roll_context())
2296 sctx->context_roll = true;
2297 }
2298
2299 bool primitive_restart = !IS_DRAW_VERTEX_STATE && info->primitive_restart;
2300
2301 /* Emit states. */
2302 si_emit_rasterizer_prim_state<GFX_VERSION, HAS_GS, NGG>(sctx);
2303 /* This emits states and flushes caches. */
2304 si_emit_all_states(sctx, masked_atoms);
2305 /* This can be done after si_emit_all_states because it doesn't set barrier flags. */
2306 si_emit_draw_registers<GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE>
2307 (sctx, indirect, prim, index_size, instance_count, primitive_restart,
2308 info->restart_index, min_direct_count);
2309
2310 /* <-- CUs are idle here if the barrier atom waited. */
2311
2312 /* This must be done after si_emit_all_states, which can affect this. */
2313 si_emit_vs_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE, HAS_SH_PAIRS_PACKED>
2314 (sctx, index_size);
2315
2316 /* This needs to be done after cache flushes because ACQUIRE_MEM rolls the context. */
2317 if (GFX_VERSION == GFX9 && gfx9_scissor_bug &&
2318 (sctx->context_roll || si_is_atom_dirty(sctx, &sctx->atoms.s.scissors))) {
2319 sctx->atoms.s.scissors.emit(sctx, -1);
2320 sctx->dirty_atoms &= ~si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2321 }
2322 assert(sctx->dirty_atoms == 0);
2323
2324 /* This uploads VBO descriptors, sets user SGPRs, and executes the L2 prefetch.
2325 * It should done after cache flushing.
2326 */
2327 if (unlikely((!si_upload_and_prefetch_VB_descriptors
2328 <GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE, HAS_SH_PAIRS_PACKED, POPCNT>
2329 (sctx, state, partial_velem_mask)))) {
2330 DRAW_CLEANUP;
2331 return;
2332 }
2333
2334 si_emit_draw_packets<GFX_VERSION, HAS_TESS, HAS_GS, NGG, IS_DRAW_VERTEX_STATE, HAS_SH_PAIRS_PACKED>
2335 (sctx, info, drawid_offset, indirect, draws, num_draws, indexbuf,
2336 index_size, index_offset, instance_count);
2337 /* <-- CUs start to get busy here if we waited. */
2338
2339 /* Start prefetches after the draw has been started. Both will run
2340 * in parallel, but starting the draw first is more important.
2341 */
2342 si_prefetch_shaders<GFX_VERSION, HAS_TESS, HAS_GS, NGG>(sctx);
2343
2344 /* Clear the context roll flag after the draw call.
2345 * Only used by the gfx9 scissor bug.
2346 */
2347 if (GFX_VERSION == GFX9)
2348 sctx->context_roll = false;
2349
2350 if (unlikely(sctx->current_saved_cs)) {
2351 si_trace_emit(sctx);
2352 si_log_draw_state(sctx, sctx->log);
2353 }
2354
2355 /* Workaround for a VGT hang when streamout is enabled.
2356 * It must be done after drawing. */
2357 if (((GFX_VERSION == GFX7 && sctx->family == CHIP_HAWAII) ||
2358 (GFX_VERSION == GFX8 && (sctx->family == CHIP_TONGA || sctx->family == CHIP_FIJI))) &&
2359 si_get_strmout_en(sctx)) {
2360 radeon_begin(&sctx->gfx_cs);
2361 radeon_event_write(V_028A90_VGT_STREAMOUT_SYNC);
2362 radeon_end();
2363 }
2364
2365 if (unlikely(GFX_VERSION < GFX12 && sctx->decompression_enabled)) {
2366 sctx->num_decompress_calls++;
2367 } else {
2368 sctx->num_draw_calls += num_draws;
2369 }
2370
2371 /* On Gfx12, this is only used to detect whether a depth texture is in the cleared state. */
2372 if (sctx->framebuffer.state.zsbuf) {
2373 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
2374 zstex->depth_cleared_level_mask &= ~BITFIELD_BIT(sctx->framebuffer.state.zsbuf->u.tex.level);
2375 }
2376
2377 if (u_trace_perfetto_active(&sctx->ds.trace_context)) {
2378 trace_si_end_draw(&sctx->trace, total_direct_count);
2379 }
2380
2381 DRAW_CLEANUP;
2382 }
2383
2384 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
2385 si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED>
si_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2386 static void si_draw_vbo(struct pipe_context *ctx,
2387 const struct pipe_draw_info *info,
2388 unsigned drawid_offset,
2389 const struct pipe_draw_indirect_info *indirect,
2390 const struct pipe_draw_start_count_bias *draws,
2391 unsigned num_draws)
2392 {
2393 si_draw<GFX_VERSION, HAS_TESS, HAS_GS, NGG, DRAW_VERTEX_STATE_OFF, HAS_SH_PAIRS_PACKED, POPCNT_NO>
2394 (ctx, info, drawid_offset, indirect, draws, num_draws, NULL, 0);
2395 }
2396
2397 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
2398 si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED, util_popcnt POPCNT>
si_draw_vertex_state(struct pipe_context * ctx,struct pipe_vertex_state * vstate,uint32_t partial_velem_mask,struct pipe_draw_vertex_state_info info,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2399 static void si_draw_vertex_state(struct pipe_context *ctx,
2400 struct pipe_vertex_state *vstate,
2401 uint32_t partial_velem_mask,
2402 struct pipe_draw_vertex_state_info info,
2403 const struct pipe_draw_start_count_bias *draws,
2404 unsigned num_draws)
2405 {
2406 struct si_vertex_state *state = (struct si_vertex_state *)vstate;
2407 struct pipe_draw_info dinfo = {};
2408
2409 dinfo.mode = info.mode;
2410 dinfo.index_size = 4;
2411 dinfo.instance_count = 1;
2412 dinfo.index.resource = state->b.input.indexbuf;
2413
2414 si_draw<GFX_VERSION, HAS_TESS, HAS_GS, NGG, DRAW_VERTEX_STATE_ON, HAS_SH_PAIRS_PACKED, POPCNT>
2415 (ctx, &dinfo, 0, NULL, draws, num_draws, vstate, partial_velem_mask);
2416
2417 if (info.take_vertex_state_ownership)
2418 pipe_vertex_state_reference(&vstate, NULL);
2419 }
2420
si_draw_rectangle(struct blitter_context * blitter,void * vertex_elements_cso,blitter_get_vs_func get_vs,int x1,int y1,int x2,int y2,float depth,unsigned num_instances,enum blitter_attrib_type type,const union blitter_attrib * attrib)2421 static void si_draw_rectangle(struct blitter_context *blitter, void *vertex_elements_cso,
2422 blitter_get_vs_func get_vs, int x1, int y1, int x2, int y2,
2423 float depth, unsigned num_instances, enum blitter_attrib_type type,
2424 const union blitter_attrib *attrib)
2425 {
2426 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2427 struct si_context *sctx = (struct si_context *)pipe;
2428 uint32_t attribute_ring_address_lo =
2429 sctx->gfx_level >= GFX11 ? sctx->screen->attribute_pos_prim_ring->gpu_address : 0;
2430
2431 /* Pack position coordinates as signed int16. */
2432 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) | ((uint32_t)(y1 & 0xffff) << 16);
2433 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) | ((uint32_t)(y2 & 0xffff) << 16);
2434 sctx->vs_blit_sh_data[2] = fui(depth);
2435
2436 switch (type) {
2437 case UTIL_BLITTER_ATTRIB_COLOR:
2438 memcpy(&sctx->vs_blit_sh_data[3], attrib->color, sizeof(float) * 4);
2439 sctx->vs_blit_sh_data[7] = attribute_ring_address_lo;
2440 break;
2441 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2442 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2443 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord, sizeof(attrib->texcoord));
2444 sctx->vs_blit_sh_data[9] = attribute_ring_address_lo;
2445 break;
2446 case UTIL_BLITTER_ATTRIB_NONE:;
2447 }
2448
2449 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2450
2451 struct pipe_draw_info info = {};
2452 struct pipe_draw_start_count_bias draw;
2453
2454 info.mode = SI_PRIM_RECTANGLE_LIST;
2455 info.instance_count = num_instances;
2456
2457 draw.start = 0;
2458 draw.count = 3;
2459
2460 /* Blits don't use vertex buffers. */
2461 sctx->vertex_buffers_dirty = false;
2462
2463 pipe->draw_vbo(pipe, &info, 0, NULL, &draw, 1);
2464 }
2465
2466 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
2467 util_popcnt POPCNT>
si_init_draw_vbo(struct si_context * sctx)2468 static void si_init_draw_vbo(struct si_context *sctx)
2469 {
2470 if (NGG && GFX_VERSION < GFX10)
2471 return;
2472
2473 if (!NGG && GFX_VERSION >= GFX11)
2474 return;
2475
2476 if (GFX_VERSION >= GFX11 && GFX_VERSION < GFX12 && sctx->screen->info.has_set_sh_pairs_packed) {
2477 sctx->draw_vbo[HAS_TESS][HAS_GS][NGG] =
2478 si_draw_vbo<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_ON>;
2479
2480 sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] =
2481 si_draw_vertex_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_ON, POPCNT>;
2482 } else {
2483 sctx->draw_vbo[HAS_TESS][HAS_GS][NGG] =
2484 si_draw_vbo<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_OFF>;
2485
2486 sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] =
2487 si_draw_vertex_state<GFX_VERSION, HAS_TESS, HAS_GS, NGG, HAS_SH_PAIRS_PACKED_OFF, POPCNT>;
2488 }
2489 }
2490
2491 template <amd_gfx_level GFX_VERSION>
si_init_draw_vbo_all_pipeline_options(struct si_context * sctx)2492 static void si_init_draw_vbo_all_pipeline_options(struct si_context *sctx)
2493 {
2494 if (util_get_cpu_caps()->has_popcnt) {
2495 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_OFF, NGG_OFF, POPCNT_YES>(sctx);
2496 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_ON, NGG_OFF, POPCNT_YES>(sctx);
2497 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_OFF, NGG_OFF, POPCNT_YES>(sctx);
2498 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_ON, NGG_OFF, POPCNT_YES>(sctx);
2499 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_OFF, NGG_ON, POPCNT_YES>(sctx);
2500 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_ON, NGG_ON, POPCNT_YES>(sctx);
2501 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_OFF, NGG_ON, POPCNT_YES>(sctx);
2502 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_ON, NGG_ON, POPCNT_YES>(sctx);
2503 } else {
2504 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_OFF, NGG_OFF, POPCNT_NO>(sctx);
2505 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_ON, NGG_OFF, POPCNT_NO>(sctx);
2506 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_OFF, NGG_OFF, POPCNT_NO>(sctx);
2507 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_ON, NGG_OFF, POPCNT_NO>(sctx);
2508 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_OFF, NGG_ON, POPCNT_NO>(sctx);
2509 si_init_draw_vbo<GFX_VERSION, TESS_OFF, GS_ON, NGG_ON, POPCNT_NO>(sctx);
2510 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_OFF, NGG_ON, POPCNT_NO>(sctx);
2511 si_init_draw_vbo<GFX_VERSION, TESS_ON, GS_ON, NGG_ON, POPCNT_NO>(sctx);
2512 }
2513 }
2514
si_invalid_draw_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2515 static void si_invalid_draw_vbo(struct pipe_context *pipe,
2516 const struct pipe_draw_info *info,
2517 unsigned drawid_offset,
2518 const struct pipe_draw_indirect_info *indirect,
2519 const struct pipe_draw_start_count_bias *draws,
2520 unsigned num_draws)
2521 {
2522 unreachable("vertex shader not bound");
2523 }
2524
si_invalid_draw_vertex_state(struct pipe_context * ctx,struct pipe_vertex_state * vstate,uint32_t partial_velem_mask,struct pipe_draw_vertex_state_info info,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2525 static void si_invalid_draw_vertex_state(struct pipe_context *ctx,
2526 struct pipe_vertex_state *vstate,
2527 uint32_t partial_velem_mask,
2528 struct pipe_draw_vertex_state_info info,
2529 const struct pipe_draw_start_count_bias *draws,
2530 unsigned num_draws)
2531 {
2532 unreachable("vertex shader not bound");
2533 }
2534
2535 extern "C"
GFX(si_init_draw_functions_)2536 void GFX(si_init_draw_functions_)(struct si_context *sctx)
2537 {
2538 assert(sctx->gfx_level == GFX());
2539
2540 si_init_draw_vbo_all_pipeline_options<GFX()>(sctx);
2541
2542 /* Bind a fake draw_vbo, so that draw_vbo isn't NULL, which would skip
2543 * initialization of callbacks in upper layers (such as u_threaded_context).
2544 */
2545 sctx->b.draw_vbo = si_invalid_draw_vbo;
2546 sctx->b.draw_vertex_state = si_invalid_draw_vertex_state;
2547 sctx->blitter->draw_rectangle = si_draw_rectangle;
2548
2549 si_init_ia_multi_vgt_param_table(sctx);
2550 }
2551