xref: /aosp_15_r20/external/mesa3d/src/intel/common/intel_gem.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2018 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #ifndef INTEL_GEM_H
25 #define INTEL_GEM_H
26 
27 #include <assert.h>
28 #include <time.h>
29 #include <errno.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <stdlib.h>
33 #include <unistd.h>
34 #include <sys/ioctl.h>
35 
36 #include "intel_engine.h"
37 #include "drm-uapi/drm.h"
38 #include "util/macros.h"
39 
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43 
44 #define RCS_TIMESTAMP 0x2358
45 
46 static inline uint64_t
intel_canonical_address(uint64_t v)47 intel_canonical_address(uint64_t v)
48 {
49    /* From the Broadwell PRM Vol. 2a, MI_LOAD_REGISTER_MEM::MemoryAddress:
50     *
51     *    "This field specifies the address of the memory location where the
52     *    register value specified in the DWord above will read from. The
53     *    address specifies the DWord location of the data. Range =
54     *    GraphicsVirtualAddress[63:2] for a DWord register GraphicsAddress
55     *    [63:48] are ignored by the HW and assumed to be in correct
56     *    canonical form [63:48] == [47]."
57     */
58    const int shift = 63 - 47;
59    return (int64_t)(v << shift) >> shift;
60 }
61 
62 /**
63  * This returns a 48-bit address with the high 16 bits zeroed.
64  *
65  * It's the opposite of intel_canonicalize_address.
66  */
67 static inline uint64_t
intel_48b_address(uint64_t v)68 intel_48b_address(uint64_t v)
69 {
70    const int shift = 63 - 47;
71    return (uint64_t)(v << shift) >> shift;
72 }
73 
74 /**
75  * Call ioctl, restarting if it is interrupted
76  */
77 static inline int
intel_ioctl(int fd,unsigned long request,void * arg)78 intel_ioctl(int fd, unsigned long request, void *arg)
79 {
80     int ret;
81 
82     do {
83         ret = ioctl(fd, request, arg);
84     } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
85     return ret;
86 }
87 
88 bool intel_gem_supports_syncobj_wait(int fd);
89 
90 bool
91 intel_gem_read_render_timestamp(int fd, enum intel_kmd_type kmd_type,
92                                 uint64_t *value);
93 bool
94 intel_gem_read_correlate_cpu_gpu_timestamp(int fd,
95                                            enum intel_kmd_type kmd_type,
96                                            enum intel_engine_class engine_class,
97                                            uint16_t engine_instance,
98                                            clockid_t cpu_clock_id,
99                                            uint64_t *cpu_timestamp,
100                                            uint64_t *gpu_timestamp,
101                                            uint64_t *cpu_delta);
102 bool intel_gem_can_render_on_fd(int fd, enum intel_kmd_type kmd_type);
103 
104 /* Functions only used by i915 */
105 enum intel_gem_create_context_flags {
106    INTEL_GEM_CREATE_CONTEXT_EXT_RECOVERABLE_FLAG = BITFIELD_BIT(0),
107    INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG   = BITFIELD_BIT(1),
108    INTEL_GEM_CREATE_CONTEXT_EXT_LOW_LATENCY_FLAG = BITFIELD_BIT(2),
109 };
110 
111 bool intel_gem_create_context(int fd, uint32_t *context_id);
112 bool intel_gem_destroy_context(int fd, uint32_t context_id);
113 bool
114 intel_gem_create_context_engines(int fd,
115                                  enum intel_gem_create_context_flags flags,
116                                  const struct intel_query_engine_info *info,
117                                  int num_engines, enum intel_engine_class *engine_classes,
118                                  uint32_t vm_id,
119                                  uint32_t *context_id);
120 bool
121 intel_gem_set_context_param(int fd, uint32_t context, uint32_t param,
122                             uint64_t value);
123 bool
124 intel_gem_get_context_param(int fd, uint32_t context, uint32_t param,
125                             uint64_t *value);
126 bool intel_gem_get_param(int fd, uint32_t param, int *value);
127 bool intel_gem_wait_on_get_param(int fd, uint32_t param, int target_val,
128                                  uint32_t timeout_ms);
129 
130 bool intel_gem_create_context_ext(int fd, enum intel_gem_create_context_flags flags,
131                                   uint32_t *ctx_id);
132 bool intel_gem_supports_protected_context(int fd,
133                                           enum intel_kmd_type kmd_type);
134 
135 #define DRM_IOCTL_I915_LAST             DRM_IO(DRM_COMMAND_END - 1)
136 
137 struct drm_intel_stub_devinfo {
138    uint64_t addr;
139    uint32_t size;
140 };
141 
142 #define DRM_IOCTL_INTEL_STUB_DEVINFO    DRM_IOR(DRM_IOCTL_I915_LAST, struct drm_intel_stub_devinfo)
143 
144 #ifdef __cplusplus
145 }
146 #endif
147 
148 #endif /* INTEL_GEM_H */
149