1 /*
2 * Copyright (c) 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdlib.h>
25 #include <math.h>
26
27 #include "util/macros.h"
28
29 #include "intel_l3_config.h"
30
31 struct intel_l3_list {
32 const struct intel_l3_config *configs;
33 int length;
34 };
35
36 #define DECLARE_L3_LIST(hw) \
37 struct intel_l3_list hw##_l3_list = \
38 { .configs = hw##_l3_configs, .length = ARRAY_SIZE(hw##_l3_configs) }
39
40 /**
41 * IVB/HSW validated L3 configurations. The first entry will be used as
42 * default by gfx7_restore_default_l3_config(), otherwise the ordering is
43 * unimportant.
44 */
45 static const struct intel_l3_config ivb_l3_configs[] = {
46 /* SLM URB ALL DC RO IS C T */
47 {{ 0, 32, 0, 0, 32, 0, 0, 0 }},
48 {{ 0, 32, 0, 16, 16, 0, 0, 0 }},
49 {{ 0, 32, 0, 4, 0, 8, 4, 16 }},
50 {{ 0, 28, 0, 8, 0, 8, 4, 16 }},
51 {{ 0, 28, 0, 16, 0, 8, 4, 8 }},
52 {{ 0, 28, 0, 8, 0, 16, 4, 8 }},
53 {{ 0, 28, 0, 0, 0, 16, 4, 16 }},
54 {{ 0, 32, 0, 0, 0, 16, 0, 16 }},
55 {{ 0, 28, 0, 4, 32, 0, 0, 0 }},
56 {{ 16, 16, 0, 16, 16, 0, 0, 0 }},
57 {{ 16, 16, 0, 8, 0, 8, 8, 8 }},
58 {{ 16, 16, 0, 4, 0, 8, 4, 16 }},
59 {{ 16, 16, 0, 4, 0, 16, 4, 8 }},
60 {{ 16, 16, 0, 0, 32, 0, 0, 0 }},
61 };
62 DECLARE_L3_LIST(ivb);
63
64 /**
65 * VLV validated L3 configurations. \sa ivb_l3_configs.
66 */
67 static const struct intel_l3_config vlv_l3_configs[] = {
68 /* SLM URB ALL DC RO IS C T */
69 {{ 0, 64, 0, 0, 32, 0, 0, 0 }},
70 {{ 0, 80, 0, 0, 16, 0, 0, 0 }},
71 {{ 0, 80, 0, 8, 8, 0, 0, 0 }},
72 {{ 0, 64, 0, 16, 16, 0, 0, 0 }},
73 {{ 0, 60, 0, 4, 32, 0, 0, 0 }},
74 {{ 32, 32, 0, 16, 16, 0, 0, 0 }},
75 {{ 32, 40, 0, 8, 16, 0, 0, 0 }},
76 {{ 32, 40, 0, 16, 8, 0, 0, 0 }},
77 };
78 DECLARE_L3_LIST(vlv);
79
80 /**
81 * BDW validated L3 configurations. \sa ivb_l3_configs.
82 */
83 static const struct intel_l3_config bdw_l3_configs[] = {
84 /* SLM URB ALL DC RO IS C T */
85 {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
86 {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
87 {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
88 {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
89 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
90 {{ 24, 16, 48, 0, 0, 0, 0, 0 }},
91 {{ 24, 16, 0, 16, 32, 0, 0, 0 }},
92 {{ 24, 16, 0, 32, 16, 0, 0, 0 }},
93 };
94 DECLARE_L3_LIST(bdw);
95
96 /**
97 * CHV/SKL validated L3 configurations. \sa ivb_l3_configs.
98 */
99 static const struct intel_l3_config chv_l3_configs[] = {
100 /* SLM URB ALL DC RO IS C T */
101 {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
102 {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
103 {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
104 {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
105 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
106 {{ 32, 16, 48, 0, 0, 0, 0, 0 }},
107 {{ 32, 16, 0, 16, 32, 0, 0, 0 }},
108 {{ 32, 16, 0, 32, 16, 0, 0, 0 }},
109 };
110 DECLARE_L3_LIST(chv);
111
112 /**
113 * BXT 2x6 validated L3 configurations. \sa ivb_l3_configs.
114 */
115 static const struct intel_l3_config bxt_2x6_l3_configs[] = {
116 /* SLM URB ALL DC RO IS C T */
117 {{ 0, 32, 48, 0, 0, 0, 0, 0 }},
118 {{ 0, 32, 0, 8, 40, 0, 0, 0 }},
119 {{ 0, 32, 0, 32, 16, 0, 0, 0 }},
120 {{ 16, 16, 48, 0, 0, 0, 0, 0 }},
121 {{ 16, 16, 0, 40, 8, 0, 0, 0 }},
122 {{ 16, 16, 0, 16, 32, 0, 0, 0 }},
123 };
124 DECLARE_L3_LIST(bxt_2x6);
125
126 /**
127 * ICL validated L3 configurations. \sa icl_l3_configs.
128 * Zeroth entry in below table has been commented out intentionally
129 * due to known issues with this configuration. Many other entries
130 * suggested by h/w specification aren't added here because they
131 * do under allocation of L3 cache with below partitioning.
132 */
133 static const struct intel_l3_config icl_l3_configs[] = {
134 /* SLM URB ALL DC RO IS C T */
135 /*{{ 0, 16, 80, 0, 0, 0, 0, 0 }},*/
136 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
137 };
138 DECLARE_L3_LIST(icl);
139
140 /**
141 * TGL validated L3 configurations. \sa tgl_l3_configs.
142 */
143 static const struct intel_l3_config tgl_l3_configs[] = {
144 /* SLM URB ALL DC RO IS C T */
145 {{ 0, 32, 88, 0, 0, 0, 0, 0 }},
146 {{ 0, 16, 104, 0, 0, 0, 0, 0 }},
147 };
148 DECLARE_L3_LIST(tgl);
149
150 /**
151 * Empty L3 configurations. \sa empty_l3_configs.
152 */
153 static const struct intel_l3_config empty_l3_configs[] = {
154 /* No configurations. L3FullWayAllocationEnable is always set. */
155 };
156 DECLARE_L3_LIST(empty);
157
158 /**
159 * DG2 validated L3 configurations. \sa dg2_l3_configs.
160 */
161 static const struct intel_l3_config dg2_l3_configs[] = {
162 /* SLM URB ALL DC RO IS C T TC */
163 {{ 0, 0, 128, 0, 0, 0, 0, 0, 0 }},
164 {{ 0, 0, 96, 0, 0, 0, 0, 0, 32 }},
165 {{ 0, 0, 64, 0, 0, 0, 0, 0, 64 }},
166 };
167 DECLARE_L3_LIST(dg2);
168
169 /**
170 * Return a zero-terminated array of validated L3 configurations for the
171 * specified device.
172 */
173 static const struct intel_l3_list *
get_l3_list(const struct intel_device_info * devinfo)174 get_l3_list(const struct intel_device_info *devinfo)
175 {
176 switch (devinfo->ver) {
177 case 7:
178 return (devinfo->platform == INTEL_PLATFORM_BYT ? &vlv_l3_list : &ivb_l3_list);
179
180 case 8:
181 return (devinfo->platform == INTEL_PLATFORM_CHV ? &chv_l3_list : &bdw_l3_list);
182
183 case 9:
184 if (devinfo->l3_banks == 1)
185 return &bxt_2x6_l3_list;
186 return &chv_l3_list;
187
188 case 11:
189 return &icl_l3_list;
190
191 case 12:
192 if (intel_device_info_is_dg2(devinfo) ||
193 intel_device_info_is_mtl_or_arl(devinfo)) {
194 /* XXX - Some MTL configs may need special-casing here, but
195 * we have no way to identify them right now.
196 */
197 return &dg2_l3_list;
198 } else if (devinfo->platform == INTEL_PLATFORM_DG1 || devinfo->verx10 == 125)
199 return &empty_l3_list;
200 else
201 return &tgl_l3_list;
202
203 case 20:
204 return &empty_l3_list;
205
206 default:
207 unreachable("Not implemented");
208 }
209 }
210
211 /**
212 * L1-normalize a vector of L3 partition weights.
213 */
214 static struct intel_l3_weights
norm_l3_weights(struct intel_l3_weights w)215 norm_l3_weights(struct intel_l3_weights w)
216 {
217 float sz = 0;
218
219 for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
220 sz += w.w[i];
221
222 for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
223 w.w[i] /= sz;
224
225 return w;
226 }
227
228 /**
229 * Get the relative partition weights of the specified L3 configuration.
230 */
231 struct intel_l3_weights
intel_get_l3_config_weights(const struct intel_l3_config * cfg)232 intel_get_l3_config_weights(const struct intel_l3_config *cfg)
233 {
234 if (cfg) {
235 struct intel_l3_weights w;
236
237 for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
238 w.w[i] = cfg->n[i];
239
240 return norm_l3_weights(w);
241 } else {
242 const struct intel_l3_weights w = { { 0 } };
243 return w;
244 }
245 }
246
247 /**
248 * Distance between two L3 configurations represented as vectors of weights.
249 * Usually just the L1 metric except when the two configurations are
250 * considered incompatible in which case the distance will be infinite. Note
251 * that the compatibility condition is asymmetric -- They will be considered
252 * incompatible whenever the reference configuration \p w0 requires SLM, DC,
253 * or URB but \p w1 doesn't provide it.
254 */
255 float
intel_diff_l3_weights(struct intel_l3_weights w0,struct intel_l3_weights w1)256 intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1)
257 {
258 if ((w0.w[INTEL_L3P_SLM] && !w1.w[INTEL_L3P_SLM]) ||
259 (w0.w[INTEL_L3P_DC] && !w1.w[INTEL_L3P_DC] && !w1.w[INTEL_L3P_ALL]) ||
260 (w0.w[INTEL_L3P_URB] && !w1.w[INTEL_L3P_URB])) {
261 return HUGE_VALF;
262
263 } else {
264 float dw = 0;
265
266 for (unsigned i = 0; i < INTEL_NUM_L3P; i++)
267 dw += fabsf(w0.w[i] - w1.w[i]);
268
269 return dw;
270 }
271 }
272
273 /**
274 * Return a reasonable default L3 configuration for the specified device based
275 * on whether SLM and DC are required. In the non-SLM non-DC case the result
276 * is intended to approximately resemble the hardware defaults.
277 */
278 struct intel_l3_weights
intel_get_default_l3_weights(const struct intel_device_info * devinfo,bool needs_dc,bool needs_slm)279 intel_get_default_l3_weights(const struct intel_device_info *devinfo,
280 bool needs_dc, bool needs_slm)
281 {
282 struct intel_l3_weights w = {{ 0 }};
283
284 w.w[INTEL_L3P_SLM] = devinfo->ver < 11 && needs_slm;
285 w.w[INTEL_L3P_URB] = devinfo->verx10 < 125 ? 1.0 : 0.0;
286
287 if (devinfo->ver >= 8) {
288 w.w[INTEL_L3P_ALL] = 1.0;
289 } else {
290 w.w[INTEL_L3P_DC] = needs_dc ? 0.1 : 0;
291 w.w[INTEL_L3P_RO] = devinfo->platform == INTEL_PLATFORM_BYT ? 0.5 : 1.0;
292 }
293
294 return norm_l3_weights(w);
295 }
296
297 /**
298 * Get the default L3 configuration
299 */
300 const struct intel_l3_config *
intel_get_default_l3_config(const struct intel_device_info * devinfo)301 intel_get_default_l3_config(const struct intel_device_info *devinfo)
302 {
303 /* For efficiency assume that the first entry of the array matches the
304 * default configuration.
305 */
306 const struct intel_l3_list *const list = get_l3_list(devinfo);
307 assert(list->length > 0 || devinfo->ver >= 12);
308 if (list->length > 0) {
309 const struct intel_l3_config *const cfg = &list->configs[0];
310 assert(cfg == intel_get_l3_config(devinfo,
311 intel_get_default_l3_weights(devinfo, false, false)));
312 return cfg;
313 } else {
314 return NULL;
315 }
316 }
317
318 /**
319 * Return the closest validated L3 configuration for the specified device and
320 * weight vector.
321 */
322 const struct intel_l3_config *
intel_get_l3_config(const struct intel_device_info * devinfo,struct intel_l3_weights w0)323 intel_get_l3_config(const struct intel_device_info *devinfo,
324 struct intel_l3_weights w0)
325 {
326 const struct intel_l3_list *const list = get_l3_list(devinfo);
327 const struct intel_l3_config *const cfgs = list->configs;
328 const struct intel_l3_config *cfg_best = NULL;
329 float dw_best = HUGE_VALF;
330
331 for (int i = 0; i < list->length; i++) {
332 const struct intel_l3_config *cfg = &cfgs[i];
333 const float dw = intel_diff_l3_weights(w0, intel_get_l3_config_weights(cfg));
334
335 if (dw < dw_best) {
336 cfg_best = cfg;
337 dw_best = dw;
338 }
339 }
340
341 assert(cfg_best || devinfo->ver >= 12);
342 return cfg_best;
343 }
344
345 /**
346 * Return the size of an L3 way in KB.
347 */
348 static unsigned
get_l3_way_size(const struct intel_device_info * devinfo)349 get_l3_way_size(const struct intel_device_info *devinfo)
350 {
351 /* Only MTL N/S/M have an 8KB way size, other MTL configs have 4KB
352 * ways. See BSpec 45319.
353 */
354 const unsigned way_size_per_bank =
355 devinfo->platform == INTEL_PLATFORM_MTL_U ? 8 :
356 (devinfo->ver >= 9 && devinfo->l3_banks == 1) || devinfo->ver >= 11 ? 4 :
357 2;
358
359 assert(devinfo->l3_banks);
360 return way_size_per_bank * devinfo->l3_banks;
361 }
362
363 /**
364 * Return the unit brw_context::urb::size is expressed in, in KB. \sa
365 * intel_device_info::urb::size.
366 */
367 static unsigned
get_urb_size_scale(const struct intel_device_info * devinfo)368 get_urb_size_scale(const struct intel_device_info *devinfo)
369 {
370 return (devinfo->ver >= 8 ? devinfo->num_slices : 1);
371 }
372
373 unsigned
intel_get_l3_config_urb_size(const struct intel_device_info * devinfo,const struct intel_l3_config * cfg)374 intel_get_l3_config_urb_size(const struct intel_device_info *devinfo,
375 const struct intel_l3_config *cfg)
376 {
377 unsigned urb_size;
378
379 /* We don't have to program the URB size for some platforms. It's a fixed
380 * value.
381 */
382 if (cfg == NULL) {
383 ASSERTED const struct intel_l3_list *const list = get_l3_list(devinfo);
384 assert(list->length == 0);
385 urb_size = 0;
386 } else {
387 urb_size = intel_get_l3_partition_size(devinfo, cfg, INTEL_L3P_URB);
388 }
389
390 if (urb_size == 0)
391 return devinfo->urb.size;
392
393 /* From the SKL "L3 Allocation and Programming" documentation:
394 *
395 * "URB is limited to 1008KB due to programming restrictions. This is not
396 * a restriction of the L3 implementation, but of the FF and other clients.
397 * Therefore, in a GT4 implementation it is possible for the programmed
398 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
399 * only 1008KB of this will be used."
400 */
401 const unsigned max = (devinfo->ver == 9 ? 1008 : ~0);
402 return MIN2(max, urb_size) / get_urb_size_scale(devinfo);
403 }
404
405 /**
406 * Return the size of the specified L3 partition in KB.
407 */
408 unsigned
intel_get_l3_partition_size(const struct intel_device_info * devinfo,const struct intel_l3_config * cfg,enum intel_l3_partition i)409 intel_get_l3_partition_size(const struct intel_device_info *devinfo,
410 const struct intel_l3_config *cfg,
411 enum intel_l3_partition i)
412 {
413 return cfg->n[i] * get_l3_way_size(devinfo);
414 }
415
416 /**
417 * Print out the specified L3 configuration.
418 */
419 void
intel_dump_l3_config(const struct intel_l3_config * cfg,FILE * fp)420 intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp)
421 {
422 fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
423 cfg->n[INTEL_L3P_SLM], cfg->n[INTEL_L3P_URB], cfg->n[INTEL_L3P_ALL],
424 cfg->n[INTEL_L3P_DC], cfg->n[INTEL_L3P_RO],
425 cfg->n[INTEL_L3P_IS], cfg->n[INTEL_L3P_C], cfg->n[INTEL_L3P_T]);
426 }
427