1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "intel_mem.h"
25 #include "util/u_cpu_detect.h"
26
27 #include <stdint.h>
28
29 #define CACHELINE_SIZE 64
30 #define CACHELINE_MASK 63
31
32 #ifdef SUPPORT_INTEL_INTEGRATED_GPUS
33
34 #ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT
35 void intel_clflushopt_range(void *start, size_t size);
36 #endif
37
38 static void
intel_clflush_range(void * start,size_t size)39 intel_clflush_range(void *start, size_t size)
40 {
41 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
42 void *end = start + size;
43
44 while (p < end) {
45 __builtin_ia32_clflush(p);
46 p += CACHELINE_SIZE;
47 }
48 }
49
50 void
intel_flush_range_no_fence(void * start,size_t size)51 intel_flush_range_no_fence(void *start, size_t size)
52 {
53 #ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT
54 const struct util_cpu_caps_t *cpu_caps = util_get_cpu_caps();
55 if (cpu_caps->has_clflushopt) {
56 intel_clflushopt_range(start, size);
57 return;
58 }
59 #endif
60 intel_clflush_range(start, size);
61 }
62
63 void
intel_flush_range(void * start,size_t size)64 intel_flush_range(void *start, size_t size)
65 {
66 __builtin_ia32_mfence();
67 intel_flush_range_no_fence(start, size);
68 #ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT
69 /* clflushopt doesn't include an mfence like clflush */
70 if (util_get_cpu_caps()->has_clflushopt)
71 __builtin_ia32_mfence();
72 #endif
73 }
74
75 void
intel_invalidate_range(void * start,size_t size)76 intel_invalidate_range(void *start, size_t size)
77 {
78 if (size == 0)
79 return;
80
81 intel_flush_range_no_fence(start, size);
82
83 /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
84 * where mfence is not a sufficient synchronization barrier. We must
85 * double clflush the last cacheline. This guarantees it will be ordered
86 * after the preceding clflushes, and then the mfence guards against
87 * prefetches crossing the clflush boundary.
88 *
89 * See kernel commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e
90 * ("drm: Restore double clflush on the last partial cacheline")
91 * and https://bugs.freedesktop.org/show_bug.cgi?id=92845.
92 */
93 #ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT
94 /* clflushopt doesn't include an mfence like clflush */
95 if (util_get_cpu_caps()->has_clflushopt) {
96 __builtin_ia32_mfence();
97 intel_clflushopt_range(start + size - 1, 1);
98 __builtin_ia32_mfence();
99 return;
100 }
101 #endif
102 __builtin_ia32_clflush(start + size - 1);
103 __builtin_ia32_mfence();
104 }
105 #endif /* SUPPORT_INTEL_INTEGRATED_GPUS */
106