1 /*
2 * Copyright (c) 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdlib.h>
25 #include <math.h>
26
27 #include "util/u_debug.h"
28 #include "util/macros.h"
29 #include "util/u_math.h"
30 #include "compiler/shader_enums.h"
31
32 #include "intel_l3_config.h"
33
34 /**
35 * The following diagram shows how we partition the URB:
36 *
37 * 16kb or 32kb Rest of the URB space
38 * __________-__________ _________________-_________________
39 * / \ / \
40 * +-------------------------------------------------------------+
41 * | VS/HS/DS/GS/FS Push | VS/HS/DS/GS URB |
42 * | Constants | Entries |
43 * +-------------------------------------------------------------+
44 *
45 * Push constants must be stored at the beginning of the URB space,
46 * while URB entries can be stored anywhere. We choose to lay them
47 * out in pipeline order (VS -> HS -> DS -> GS).
48 */
49
50 /**
51 * Decide how to partition the URB among the various stages.
52 *
53 * \param[in] push_constant_bytes - space allocate for push constants.
54 * \param[in] urb_size_bytes - total size of the URB (from L3 config).
55 * \param[in] tess_present - are tessellation shaders active?
56 * \param[in] gs_present - are geometry shaders active?
57 * \param[in] entry_size - the URB entry size (from the shader compiler)
58 * \param[out] entries - the number of URB entries for each stage
59 * \param[out] start - the starting offset for each stage
60 * \param[out] deref_block_size - deref block size for 3DSTATE_SF
61 * \param[out] constrained - true if we wanted more space than we had
62 */
63 void
intel_get_urb_config(const struct intel_device_info * devinfo,const struct intel_l3_config * l3_cfg,bool tess_present,bool gs_present,struct intel_urb_config * urb_cfg,enum intel_urb_deref_block_size * deref_block_size,bool * constrained)64 intel_get_urb_config(const struct intel_device_info *devinfo,
65 const struct intel_l3_config *l3_cfg,
66 bool tess_present, bool gs_present,
67 struct intel_urb_config *urb_cfg,
68 enum intel_urb_deref_block_size *deref_block_size,
69 bool *constrained)
70 {
71 unsigned urb_size_kB = intel_get_l3_config_urb_size(devinfo, l3_cfg);
72
73 /* RCU_MODE register for Gfx12LP in BSpec says:
74 *
75 * "HW reserves 4KB of URB space per bank for Compute Engine out of the
76 * total storage available in L3. SW must consider that 4KB of storage
77 * per bank will be reduced from what is programmed for the URB space
78 * in L3 for Render Engine executed workloads.
79 *
80 * Example: When URB space programmed is 64KB (per bank) for Render
81 * Engine, the actual URB space available for operation is only 60KB
82 * (per bank). Similarly when URB space programmed is 128KB (per bank)
83 * for render engine, the actual URB space available for operation is
84 * only 124KB (per bank). More detailed description available in "L3
85 * Cache" section of the B-Spec."
86 */
87 if (devinfo->verx10 == 120 && devinfo->has_compute_engine) {
88 assert(devinfo->num_slices == 1);
89 urb_size_kB -= 4 * devinfo->l3_banks;
90 }
91
92 const unsigned push_constant_kB = devinfo->max_constant_urb_size_kb;
93
94 const bool active[4] = { true, tess_present, tess_present, gs_present };
95
96 /* URB allocations must be done in 8k chunks. */
97 const unsigned chunk_size_kB = 8;
98 const unsigned chunk_size_bytes = chunk_size_kB * 1024;
99
100 const unsigned push_constant_chunks = push_constant_kB / chunk_size_kB;
101 const unsigned urb_chunks = urb_size_kB / chunk_size_kB;
102
103 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
104 *
105 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
106 * Allocation Size is less than 9 512-bit URB entries.
107 *
108 * Similar text exists for HS, DS and GS.
109 */
110 unsigned granularity[4];
111 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
112 granularity[i] = (urb_cfg->size[i] < 9) ? 8 : 1;
113 }
114
115 unsigned min_entries[4] = {
116 /* VS has a lower limit on the number of URB entries.
117 *
118 * From the Broadwell PRM, 3DSTATE_URB_VS instruction:
119 * "When tessellation is enabled, the VS Number of URB Entries must be
120 * greater than or equal to 192."
121 */
122 [MESA_SHADER_VERTEX] = tess_present && devinfo->ver == 8 ?
123 192 : devinfo->urb.min_entries[MESA_SHADER_VERTEX],
124
125 /* There are two constraints on the minimum amount of URB space we can
126 * allocate:
127 *
128 * (1) We need room for at least 2 URB entries, since we always operate
129 * the GS in DUAL_OBJECT mode.
130 *
131 * (2) We can't allocate less than nr_gs_entries_granularity.
132 */
133 [MESA_SHADER_GEOMETRY] = gs_present ? 2 : 0,
134
135 [MESA_SHADER_TESS_CTRL] = tess_present ? 1 : 0,
136
137 [MESA_SHADER_TESS_EVAL] = tess_present ?
138 devinfo->urb.min_entries[MESA_SHADER_TESS_EVAL] : 0,
139 };
140
141 /* Min VS Entries isn't a multiple of 8 on Cherryview/Broxton; round up.
142 * Round them all up.
143 */
144 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
145 min_entries[i] = ALIGN(min_entries[i], granularity[i]);
146 }
147
148 unsigned entry_size_bytes[4];
149 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
150 entry_size_bytes[i] = 64 * urb_cfg->size[i];
151 }
152
153 /* Initially, assign each stage the minimum amount of URB space it needs,
154 * and make a note of how much additional space it "wants" (the amount of
155 * additional space it could actually make use of).
156 */
157 unsigned chunks[4];
158 unsigned wants[4];
159 unsigned total_needs = push_constant_chunks;
160 unsigned total_wants = 0;
161
162 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
163 if (active[i]) {
164 chunks[i] = DIV_ROUND_UP(min_entries[i] * entry_size_bytes[i],
165 chunk_size_bytes);
166
167 wants[i] =
168 DIV_ROUND_UP(devinfo->urb.max_entries[i] * entry_size_bytes[i],
169 chunk_size_bytes) - chunks[i];
170 } else {
171 chunks[i] = 0;
172 wants[i] = 0;
173 }
174
175 total_needs += chunks[i];
176 total_wants += wants[i];
177 }
178
179 assert(total_needs <= urb_chunks);
180
181 *constrained = total_needs + total_wants > urb_chunks;
182
183 /* Mete out remaining space (if any) in proportion to "wants". */
184 unsigned remaining_space = MIN2(urb_chunks - total_needs, total_wants);
185
186 if (remaining_space > 0) {
187 for (int i = MESA_SHADER_VERTEX;
188 total_wants > 0 && i <= MESA_SHADER_TESS_EVAL; i++) {
189 unsigned additional = (unsigned)
190 roundf(wants[i] * (((float) remaining_space) / total_wants));
191 chunks[i] += additional;
192 remaining_space -= additional;
193 total_wants -= wants[i];
194 }
195
196 chunks[MESA_SHADER_GEOMETRY] += remaining_space;
197 }
198
199 /* Sanity check that we haven't over-allocated. */
200 unsigned total_chunks = push_constant_chunks;
201 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
202 total_chunks += chunks[i];
203 }
204 assert(total_chunks <= urb_chunks);
205
206 /* Finally, compute the number of entries that can fit in the space
207 * allocated to each stage.
208 */
209 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
210 urb_cfg->entries[i] = chunks[i] * chunk_size_bytes / entry_size_bytes[i];
211
212 /* Since we rounded up when computing wants[], this may be slightly
213 * more than the maximum allowed amount, so correct for that.
214 */
215 urb_cfg->entries[i] = MIN2(urb_cfg->entries[i],
216 devinfo->urb.max_entries[i]);
217
218 /* Ensure that we program a multiple of the granularity. */
219 urb_cfg->entries[i] = ROUND_DOWN_TO(urb_cfg->entries[i], granularity[i]);
220
221 /* Finally, sanity check to make sure we have at least the minimum
222 * number of entries needed for each stage.
223 */
224 assert(urb_cfg->entries[i] >= min_entries[i]);
225 }
226
227 /* Lay out the URB in pipeline order: push constants, VS, HS, DS, GS. */
228 int first_urb = push_constant_chunks;
229
230 /* From the BDW PRM: for 3DSTATE_URB_*: VS URB Starting Address
231 *
232 * "Value: [4,48] Device [SliceCount] GT 1"
233 *
234 * From the ICL PRMs and above :
235 *
236 * "If CTXT_SR_CTL::POSH_Enable is clear and Push Constants are required
237 * or Device[SliceCount] GT 1, the lower limit is 4."
238 *
239 * "If Push Constants are not required andDevice[SliceCount] == 1, the
240 * lower limit is 0."
241 */
242 if ((devinfo->ver == 8 && devinfo->num_slices == 1) ||
243 (devinfo->ver >= 11 && push_constant_chunks > 0 && devinfo->num_slices == 1))
244 first_urb = MAX2(first_urb, 4);
245
246 int next_urb = first_urb;
247 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
248 if (urb_cfg->entries[i]) {
249 urb_cfg->start[i] = next_urb;
250 next_urb += chunks[i];
251 } else {
252 /* Put disabled stages at the beginning of the valid range */
253 urb_cfg->start[i] = first_urb;
254 }
255 }
256
257 if (deref_block_size) {
258 if (devinfo->ver >= 12) {
259 /* From the Gfx12 BSpec:
260 *
261 * "Deref Block size depends on the last enabled shader and number
262 * of handles programmed for that shader
263 *
264 * 1) For GS last shader enabled cases, the deref block is
265 * always set to a per poly(within hardware)
266 *
267 * If the last enabled shader is VS or DS.
268 *
269 * 1) If DS is last enabled shader then if the number of DS
270 * handles is less than 324, need to set per poly deref.
271 *
272 * 2) If VS is last enabled shader then if the number of VS
273 * handles is less than 192, need to set per poly deref"
274 *
275 * The default is 32 so we assume that's the right choice if we're
276 * not in one of the explicit cases listed above.
277 */
278 if (gs_present) {
279 *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
280 } else if (tess_present) {
281 if (urb_cfg->entries[MESA_SHADER_TESS_EVAL] < 324)
282 *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
283 else
284 *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_32;
285 } else {
286 if (urb_cfg->entries[MESA_SHADER_VERTEX] < 192)
287 *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
288 else
289 *deref_block_size = INTEL_URB_DEREF_BLOCK_SIZE_32;
290 }
291 } else {
292 *deref_block_size = 0;
293 }
294 }
295 }
296
297 struct intel_mesh_urb_allocation
intel_get_mesh_urb_config(const struct intel_device_info * devinfo,const struct intel_l3_config * l3_cfg,unsigned tue_size_dw,unsigned mue_size_dw)298 intel_get_mesh_urb_config(const struct intel_device_info *devinfo,
299 const struct intel_l3_config *l3_cfg,
300 unsigned tue_size_dw, unsigned mue_size_dw)
301 {
302 struct intel_mesh_urb_allocation r = {0};
303
304 /* Allocation Size must be aligned to 64B. */
305 r.task_entry_size_64b = DIV_ROUND_UP(tue_size_dw * 4, 64);
306 r.mesh_entry_size_64b = DIV_ROUND_UP(mue_size_dw * 4, 64);
307
308 assert(r.task_entry_size_64b <= 1024);
309 assert(r.mesh_entry_size_64b <= 1024);
310
311 /* Per-slice URB size. */
312 unsigned total_urb_kb = intel_get_l3_config_urb_size(devinfo, l3_cfg);
313
314 /* Programming Note in bspec requires all the slice to have the same number
315 * of entries, so we need to discount the space for constants for all of
316 * them. See 3DSTATE_URB_ALLOC_MESH and 3DSTATE_URB_ALLOC_TASK.
317 */
318 unsigned push_constant_kb = devinfo->mesh_max_constant_urb_size_kb;
319 /* 3DSTATE_URB_ALLOC_MESH_BODY says
320 *
321 * MESH URB Starting Address SliceN
322 * This field specifies the offset (from the start of the URB memory
323 * in slices beyond Slice0) of the MESH URB allocation, specified in
324 * multiples of 8 KB.
325 */
326 push_constant_kb = ALIGN(push_constant_kb, 8);
327 total_urb_kb -= push_constant_kb;
328 const unsigned total_urb_avail_mesh_task_kb = total_urb_kb;
329
330 /* TODO(mesh): Take push constant size as parameter instead of considering always
331 * the max? */
332
333 float task_urb_share = 0.0f;
334 if (r.task_entry_size_64b > 0) {
335 /* By default, split memory between TASK and MESH proportionally to
336 * their entry sizes. Environment variable allow us to tweak it.
337 *
338 * TODO(mesh): Re-evaluate if this is a good default once there are more
339 * workloads.
340 */
341 static int task_urb_share_percentage = -1;
342 if (task_urb_share_percentage == -1) {
343 task_urb_share_percentage =
344 MIN2(debug_get_num_option("INTEL_MESH_TASK_URB_SHARE", -2), 100);
345 }
346
347 if (task_urb_share_percentage >= 0) {
348 task_urb_share = task_urb_share_percentage / 100.0f;
349 } else {
350 task_urb_share = (float)r.task_entry_size_64b / (r.task_entry_size_64b + r.mesh_entry_size_64b);
351 }
352 }
353
354 /* 3DSTATE_URB_ALLOC_MESH_BODY and 3DSTATE_URB_ALLOC_TASK_BODY says
355 *
356 * MESH Number of URB Entries must be divisible by 8 if the MESH/TASK URB
357 * Entry Allocation Size is less than 9 512-bit URB entries.
358 */
359 const unsigned min_mesh_entries = r.mesh_entry_size_64b < 9 ? 8 : 1;
360 const unsigned min_task_entries = r.task_entry_size_64b < 9 ? 8 : 1;
361 const unsigned min_mesh_urb_kb = ALIGN(r.mesh_entry_size_64b * min_mesh_entries * 64, 1024) / 1024;
362 const unsigned min_task_urb_kb = ALIGN(r.task_entry_size_64b * min_task_entries * 64, 1024) / 1024;
363
364 total_urb_kb -= (min_mesh_urb_kb + min_task_urb_kb);
365
366 /* split the remaining urb_kbs */
367 unsigned task_urb_kb = total_urb_kb * task_urb_share;
368 unsigned mesh_urb_kb = total_urb_kb - task_urb_kb;
369
370 /* sum minimum + split urb_kbs */
371 mesh_urb_kb += min_mesh_urb_kb;
372
373 /* 3DSTATE_URB_ALLOC_TASK_BODY says
374 * MESH Number of URB Entries SliceN
375 * This field specifies the offset (from the start of the URB memory
376 * in slices beyond Slice0) of the TASK URB allocation, specified in
377 * multiples of 8 KB.
378 */
379 if ((total_urb_avail_mesh_task_kb - ALIGN(mesh_urb_kb, 8)) >= min_task_entries) {
380 mesh_urb_kb = ALIGN(mesh_urb_kb, 8);
381 } else {
382 mesh_urb_kb = ROUND_DOWN_TO(mesh_urb_kb, 8);
383 }
384
385 /* TODO(mesh): Could we avoid allocating URB for Mesh if rasterization is
386 * disabled? */
387
388 unsigned next_address_8kb = push_constant_kb / 8;
389 assert(push_constant_kb % 8 == 0);
390
391 r.mesh_starting_address_8kb = next_address_8kb;
392 r.mesh_entries = MIN2((mesh_urb_kb * 16) / r.mesh_entry_size_64b, 1548);
393 r.mesh_entries = r.mesh_entry_size_64b < 9 ? ROUND_DOWN_TO(r.mesh_entries, 8) : r.mesh_entries;
394
395 next_address_8kb += mesh_urb_kb / 8;
396 assert(mesh_urb_kb % 8 == 0);
397
398 r.task_starting_address_8kb = next_address_8kb;
399 task_urb_kb = total_urb_avail_mesh_task_kb - mesh_urb_kb;
400 if (r.task_entry_size_64b > 0) {
401 r.task_entries = MIN2((task_urb_kb * 16) / r.task_entry_size_64b, 1548);
402 r.task_entries = r.task_entry_size_64b < 9 ? ROUND_DOWN_TO(r.task_entries, 8) : r.task_entries;
403 }
404
405 r.deref_block_size = r.mesh_entries > 32 ?
406 INTEL_URB_DEREF_BLOCK_SIZE_MESH :
407 INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY;
408
409 assert(mesh_urb_kb + task_urb_kb <= total_urb_avail_mesh_task_kb);
410 assert(mesh_urb_kb >= min_mesh_urb_kb);
411 assert(task_urb_kb >= min_task_urb_kb);
412
413 return r;
414 }
415