1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdarg.h>
26 #include <stdio.h>
27 #include <inttypes.h>
28
29 #include "dev/intel_debug.h"
30 #include "genxml/genX_bits.h"
31 #include "util/log.h"
32
33 #include "isl.h"
34 #include "isl_gfx4.h"
35 #include "isl_gfx6.h"
36 #include "isl_gfx7.h"
37 #include "isl_gfx8.h"
38 #include "isl_gfx9.h"
39 #include "isl_gfx12.h"
40 #include "isl_gfx20.h"
41 #include "isl_priv.h"
42
43 isl_genX_declare_get_func(surf_fill_state_s)
isl_genX_declare_get_func(buffer_fill_state_s)44 isl_genX_declare_get_func(buffer_fill_state_s)
45 isl_genX_declare_get_func(emit_depth_stencil_hiz_s)
46 isl_genX_declare_get_func(null_fill_state_s)
47 isl_genX_declare_get_func(emit_cpb_control_s)
48
49 void
50 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
51 uint32_t yt1, uint32_t yt2,
52 char *dst, const char *src,
53 uint32_t dst_pitch, int32_t src_pitch,
54 bool has_swizzling,
55 enum isl_tiling tiling,
56 isl_memcpy_type copy_type)
57 {
58 #ifdef USE_SSE41
59 if (copy_type == ISL_MEMCPY_STREAMING_LOAD) {
60 _isl_memcpy_linear_to_tiled_sse41(
61 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
62 tiling, copy_type);
63 return;
64 }
65 #endif
66
67 _isl_memcpy_linear_to_tiled(
68 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
69 tiling, copy_type);
70 }
71
72 void
isl_memcpy_tiled_to_linear(uint32_t xt1,uint32_t xt2,uint32_t yt1,uint32_t yt2,char * dst,const char * src,int32_t dst_pitch,uint32_t src_pitch,bool has_swizzling,enum isl_tiling tiling,isl_memcpy_type copy_type)73 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
74 uint32_t yt1, uint32_t yt2,
75 char *dst, const char *src,
76 int32_t dst_pitch, uint32_t src_pitch,
77 bool has_swizzling,
78 enum isl_tiling tiling,
79 isl_memcpy_type copy_type)
80 {
81 #ifdef USE_SSE41
82 if (copy_type == ISL_MEMCPY_STREAMING_LOAD) {
83 _isl_memcpy_tiled_to_linear_sse41(
84 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
85 tiling, copy_type);
86 return;
87 }
88 #endif
89
90 _isl_memcpy_tiled_to_linear(
91 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
92 tiling, copy_type);
93 }
94
95 void PRINTFLIKE(3, 4) UNUSED
__isl_finishme(const char * file,int line,const char * fmt,...)96 __isl_finishme(const char *file, int line, const char *fmt, ...)
97 {
98 va_list ap;
99 char buf[512];
100
101 va_start(ap, fmt);
102 vsnprintf(buf, sizeof(buf), fmt, ap);
103 va_end(ap);
104
105 fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf);
106 }
107
108 static void
isl_device_setup_mocs(struct isl_device * dev)109 isl_device_setup_mocs(struct isl_device *dev)
110 {
111 dev->mocs.protected_mask = 0;
112
113 if (dev->info->ver >= 20) {
114 /* L3+L4=WB; BSpec: 71582 */
115 dev->mocs.internal = 1 << 1;
116 dev->mocs.external = 1 << 1;
117 dev->mocs.protected_mask = 1 << 0;
118 /* TODO: Setting to uncached
119 * WA 14018443005:
120 * Ensure that any compression-enabled resource from gfx memory subject
121 * to app recycling (e.g. OGL sparse resource backing memory or
122 * Vulkan heaps) is never PAT/MOCS'ed as L3:UC.
123 */
124 dev->mocs.blitter_dst = 1 << 1;
125 dev->mocs.blitter_src = 1 << 1;
126 } else if (dev->info->ver >= 12) {
127 if (intel_device_info_is_mtl_or_arl(dev->info)) {
128 /* Cached L3+L4; BSpec: 45101 */
129 dev->mocs.internal = 1 << 1;
130 /* Displayables cached to L3+L4:WT */
131 dev->mocs.external = 14 << 1;
132 /* Uncached - GO:Mem */
133 dev->mocs.uncached = 5 << 1;
134 /* TODO: XY_BLOCK_COPY_BLT don't mention what should be the L4 cache
135 * mode so for now it is setting L4 as uncached following what is
136 * asked for L3
137 */
138 dev->mocs.blitter_dst = 9 << 1;
139 dev->mocs.blitter_src = 9 << 1;
140 } else if (intel_device_info_is_dg2(dev->info)) {
141 /* L3CC=WB; BSpec: 45101 */
142 dev->mocs.internal = 3 << 1;
143 dev->mocs.external = 3 << 1;
144 /* UC - Coherent; GO:Memory */
145 dev->mocs.uncached = 1 << 1;
146
147 /* XY_BLOCK_COPY_BLT MOCS fields have programming notes which say:
148 *
149 * "Destination MOCS value, which is used to program MOCS index
150 * for writing to memory, should select a MOCS register having
151 * "L3 Cacheability Control" programmed as uncacheable(UC) and
152 * "Global GO" parameter set as GOMemory (pushes GO point to
153 * memory). The MOCS Register may have L3 Lookup programmed as
154 * UCL3LKDIS for better efficiency."
155 *
156 * The GO:Memory setting requires us to use MOCS 1 or 2. MOCS 2
157 * has LKUP set to 0 and is marked "Non-Coherent", which we assume
158 * is probably the "better efficiency" they mention...
159 *
160 * "Source MOCS value, which is used to program MOCS index for
161 * reading from memory, should select a MOCS register having
162 * "L3 Cacheability Control" programmed as uncacheable(UC).
163 * The MOCS Register may have L3 Lookup programmed as UCL3LKDIS
164 * for better efficiency."
165 *
166 * Any MOCS except 3 should work. We use MOCS 2...
167 */
168 dev->mocs.blitter_dst = 2 << 1;
169 dev->mocs.blitter_src = 2 << 1;
170 } else if (dev->info->platform == INTEL_PLATFORM_DG1) {
171 /* L3CC=WB */
172 dev->mocs.internal = 5 << 1;
173 /* Displayables on DG1 are free to cache in L3 since L3 is transient
174 * and flushed at bottom of each submission.
175 */
176 dev->mocs.external = 5 << 1;
177 /* UC */
178 dev->mocs.uncached = 1 << 1;
179 dev->mocs.blitter_dst = 1 << 1;
180 dev->mocs.blitter_src = 1 << 1;
181 } else {
182 /* TC=1/LLC Only, LeCC=1/UC, LRUM=0, L3CC=3/WB */
183 dev->mocs.external = 61 << 1;
184 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
185 dev->mocs.internal = 2 << 1;
186 /* Uncached */
187 dev->mocs.uncached = 3 << 1;
188
189 /* L1 - HDC:L1 + L3 + LLC */
190 dev->mocs.l1_hdc_l3_llc = 48 << 1;
191
192 /* Uncached */
193 dev->mocs.blitter_dst = 3 << 1;
194 dev->mocs.blitter_src = 3 << 1;
195 }
196 /* Protected is just an additional flag. */
197 dev->mocs.protected_mask = 1 << 0;
198 } else if (dev->info->ver >= 9) {
199 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
200 dev->mocs.external = 1 << 1;
201 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
202 dev->mocs.internal = 2 << 1;
203 /* Uncached */
204 dev->mocs.uncached = (dev->info->ver >= 11 ? 3 : 0) << 1;
205 } else if (dev->info->ver >= 8) {
206 /* MEMORY_OBJECT_CONTROL_STATE:
207 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
208 * .TargetCache = L3DefertoPATforLLCeLLCselection,
209 * .AgeforQUADLRU = 0
210 */
211 dev->mocs.external = 0x18;
212 /* MEMORY_OBJECT_CONTROL_STATE:
213 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
214 * .TargetCache = L3DefertoPATforLLCeLLCselection,
215 * .AgeforQUADLRU = 0
216 */
217 dev->mocs.internal = 0x78;
218 if (dev->info->platform == INTEL_PLATFORM_CHV) {
219 /* MEMORY_OBJECT_CONTROL_STATE:
220 * .MemoryType = UC,
221 * .TargetCache = NoCaching,
222 */
223 dev->mocs.uncached = 0;
224 } else {
225 /* MEMORY_OBJECT_CONTROL_STATE:
226 * .MemoryTypeLLCeLLCCacheabilityControl = UCUncacheable,
227 * .TargetCache = eLLCOnlywheneDRAMispresentelsegetsallocatedinLLC,
228 * .AgeforQUADLRU = 0
229 */
230 dev->mocs.uncached = 0x20;
231 }
232 } else if (dev->info->ver >= 7) {
233 if (dev->info->platform == INTEL_PLATFORM_HSW) {
234 /* MEMORY_OBJECT_CONTROL_STATE:
235 * .LLCeLLCCacheabilityControlLLCCC = 0,
236 * .L3CacheabilityControlL3CC = 1,
237 */
238 dev->mocs.internal = 1;
239 dev->mocs.external = 1;
240 /* MEMORY_OBJECT_CONTROL_STATE:
241 * .LLCeLLCCacheabilityControlLLCCC = 1,
242 * .L3CacheabilityControlL3CC = 0,
243 */
244 dev->mocs.uncached = 2;
245 } else {
246 /* MEMORY_OBJECT_CONTROL_STATE:
247 * .GraphicsDataTypeGFDT = 0,
248 * .LLCCacheabilityControlLLCCC = 0,
249 * .L3CacheabilityControlL3CC = 1,
250 */
251 dev->mocs.internal = 1;
252 dev->mocs.external = 1;
253 /* MEMORY_OBJECT_CONTROL_STATE:
254 * .GraphicsDataTypeGFDT = 0,
255 * .LLCCacheabilityControlLLCCC = 0,
256 * .L3CacheabilityControlL3CC = 0,
257 */
258 dev->mocs.uncached = 0;
259 }
260 } else {
261 dev->mocs.internal = 0;
262 dev->mocs.external = 0;
263 dev->mocs.uncached = 0;
264 }
265 }
266
267 /**
268 * Return an appropriate MOCS entry for the given usage flags.
269 */
270 uint32_t
isl_mocs(const struct isl_device * dev,isl_surf_usage_flags_t usage,bool external)271 isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
272 bool external)
273 {
274 uint32_t mask = (usage & ISL_SURF_USAGE_PROTECTED_BIT) ?
275 dev->mocs.protected_mask : 0;
276
277 if (usage & ISL_SURF_USAGE_BLITTER_SRC_BIT)
278 return dev->mocs.blitter_src | mask;
279
280 if (usage & ISL_SURF_USAGE_BLITTER_DST_BIT)
281 return dev->mocs.blitter_dst | mask;
282
283 if (external)
284 return dev->mocs.external | mask;
285
286 if (intel_device_info_is_mtl_or_arl(dev->info) &&
287 (usage & ISL_SURF_USAGE_STREAM_OUT_BIT))
288 return dev->mocs.uncached | mask;
289
290 if (dev->info->verx10 == 120 && dev->info->platform != INTEL_PLATFORM_DG1) {
291 if (usage & ISL_SURF_USAGE_STAGING_BIT)
292 return dev->mocs.internal | mask;
293
294 if (usage & ISL_SURF_USAGE_CPB_BIT)
295 return dev->mocs.internal | mask;
296
297 /* Using L1:HDC for storage buffers breaks Vulkan memory model
298 * tests that use shader atomics. This isn't likely to work out,
299 * and we can't know a priori whether they'll be used. So just
300 * continue with ordinary internal MOCS for now.
301 */
302 if (usage & ISL_SURF_USAGE_STORAGE_BIT)
303 return dev->mocs.internal | mask;
304
305 if (usage & (ISL_SURF_USAGE_CONSTANT_BUFFER_BIT |
306 ISL_SURF_USAGE_RENDER_TARGET_BIT |
307 ISL_SURF_USAGE_TEXTURE_BIT))
308 return dev->mocs.l1_hdc_l3_llc | mask;
309 }
310
311 return dev->mocs.internal | mask;
312 }
313
314 void
isl_device_init(struct isl_device * dev,const struct intel_device_info * info)315 isl_device_init(struct isl_device *dev,
316 const struct intel_device_info *info)
317 {
318 /* Gfx8+ don't have bit6 swizzling, ensure callsite is not confused. */
319 assert(!(info->has_bit6_swizzle && info->ver >= 8));
320
321 dev->info = info;
322 dev->use_separate_stencil = ISL_GFX_VER(dev) >= 6;
323 dev->has_bit6_swizzling = info->has_bit6_swizzle;
324 dev->buffer_length_in_aux_addr = false;
325 dev->sampler_route_to_lsc = false;
326
327 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
328 * device properties at buildtime. Verify that the macros with the device
329 * properties chosen during runtime.
330 */
331 ISL_GFX_VER_SANITIZE(dev);
332 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev);
333
334 /* Did we break hiz or stencil? */
335 if (ISL_DEV_USE_SEPARATE_STENCIL(dev))
336 assert(info->has_hiz_and_separate_stencil);
337 if (info->must_use_separate_stencil)
338 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
339
340 dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
341 dev->ss.align = isl_align(dev->ss.size, 32);
342
343 dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
344 dev->ss.clear_color_state_offset =
345 RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;
346
347 dev->ss.clear_value_size =
348 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
349 RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
350 RENDER_SURFACE_STATE_BlueClearColor_bits(info) +
351 RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32) / 8;
352
353 dev->ss.clear_value_offset =
354 RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4;
355
356 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
357 dev->ss.addr_offset =
358 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
359
360 /* The "Auxiliary Surface Base Address" field starts a bit higher up
361 * because the bottom 12 bits are used for other things. Round down to
362 * the nearest dword before.
363 */
364 dev->ss.aux_addr_offset =
365 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
366
367 dev->ds.size = _3DSTATE_DEPTH_BUFFER_length(info) * 4;
368 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
369 dev->ds.depth_offset =
370 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
371
372 if (dev->use_separate_stencil) {
373 dev->ds.size += _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
374 _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
375 _3DSTATE_CLEAR_PARAMS_length(info) * 4;
376
377 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
378 dev->ds.stencil_offset =
379 _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
380 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) / 8;
381
382 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
383 dev->ds.hiz_offset =
384 _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
385 _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
386 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
387 } else {
388 dev->ds.stencil_offset = 0;
389 dev->ds.hiz_offset = 0;
390 }
391
392 /* From the IVB PRM, SURFACE_STATE::Height,
393 *
394 * For typed buffer and structured buffer surfaces, the number
395 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
396 * surfaces, the number of entries in the buffer is the number of bytes
397 * which can range from 1 to 2^30.
398 *
399 * From the SKL PRM, SURFACE_STATE::Width/Height/Depth for RAW buffers,
400 *
401 * Width : bits [6:0]
402 * Height : bits [20:7]
403 * Depth : bits [31:21]
404 *
405 * So we can address 4Gb
406 *
407 * This limit is only concerned with raw buffers.
408 */
409 if (ISL_GFX_VER(dev) >= 9) {
410 dev->max_buffer_size = 1ull << 32;
411 } else if (ISL_GFX_VER(dev) >= 7) {
412 dev->max_buffer_size = 1ull << 30;
413 } else {
414 dev->max_buffer_size = 1ull << 27;
415 }
416
417 dev->cpb.size = _3DSTATE_CPSIZE_CONTROL_BUFFER_length(info) * 4;
418 dev->cpb.offset =
419 _3DSTATE_CPSIZE_CONTROL_BUFFER_SurfaceBaseAddress_start(info) / 8;
420
421 isl_device_setup_mocs(dev);
422
423 dev->surf_fill_state_s = isl_surf_fill_state_s_get_func(dev);
424 dev->buffer_fill_state_s = isl_buffer_fill_state_s_get_func(dev);
425 dev->emit_depth_stencil_hiz_s = isl_emit_depth_stencil_hiz_s_get_func(dev);
426 dev->null_fill_state_s = isl_null_fill_state_s_get_func(dev);
427 dev->emit_cpb_control_s = isl_emit_cpb_control_s_get_func(dev);
428 }
429
430 /**
431 * @brief Query the set of multisamples supported by the device.
432 *
433 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
434 * supported.
435 */
436 isl_sample_count_mask_t ATTRIBUTE_CONST
isl_device_get_sample_counts(const struct isl_device * dev)437 isl_device_get_sample_counts(const struct isl_device *dev)
438 {
439 if (ISL_GFX_VER(dev) >= 9) {
440 return ISL_SAMPLE_COUNT_1_BIT |
441 ISL_SAMPLE_COUNT_2_BIT |
442 ISL_SAMPLE_COUNT_4_BIT |
443 ISL_SAMPLE_COUNT_8_BIT |
444 ISL_SAMPLE_COUNT_16_BIT;
445 } else if (ISL_GFX_VER(dev) >= 8) {
446 return ISL_SAMPLE_COUNT_1_BIT |
447 ISL_SAMPLE_COUNT_2_BIT |
448 ISL_SAMPLE_COUNT_4_BIT |
449 ISL_SAMPLE_COUNT_8_BIT;
450 } else if (ISL_GFX_VER(dev) >= 7) {
451 return ISL_SAMPLE_COUNT_1_BIT |
452 ISL_SAMPLE_COUNT_4_BIT |
453 ISL_SAMPLE_COUNT_8_BIT;
454 } else if (ISL_GFX_VER(dev) >= 6) {
455 return ISL_SAMPLE_COUNT_1_BIT |
456 ISL_SAMPLE_COUNT_4_BIT;
457 } else {
458 return ISL_SAMPLE_COUNT_1_BIT;
459 }
460 }
461
462 uint64_t
isl_get_sampler_clear_field_offset(const struct intel_device_info * devinfo,enum isl_format format)463 isl_get_sampler_clear_field_offset(const struct intel_device_info *devinfo,
464 enum isl_format format)
465 {
466 assert(devinfo->ver == 11 || devinfo->ver == 12);
467
468 /* For 32bpc formats, the sampler fetches the raw clear color dwords
469 * used for rendering instead of the converted pixel dwords typically
470 * used for sampling. The CLEAR_COLOR struct page documents this for
471 * 128bpp formats, but not for 32bpp and 64bpp formats.
472 *
473 * Note that although the sampler doesn't use the converted clear color
474 * field with 32bpc formats, the hardware will still convert the clear
475 * color to a pixel when the surface format size is less than 128bpp.
476 */
477 if (isl_format_get_layout(format)->channels.r.bits == 32)
478 return 0;
479
480 /* According to Wa_2201730850, the gfx120 sampler reads the
481 * U24_X8-formatted pixel from the first raw clear color dword.
482 */
483 if (devinfo->verx10 == 120 && format == ISL_FORMAT_R24_UNORM_X8_TYPELESS)
484 return 0;
485
486 return 16;
487 }
488
489 static uint32_t
isl_get_miptail_base_row(enum isl_tiling tiling)490 isl_get_miptail_base_row(enum isl_tiling tiling)
491 {
492 /* Miptails base levels can depend on the number of samples, but since we
493 * don't support levels > 1 with multisampling, the base miptail level is
494 * really simple :
495 */
496 if (tiling == ISL_TILING_SKL_Yf ||
497 tiling == ISL_TILING_ICL_Yf)
498 return 4;
499 else
500 return 0;
501 }
502
503 static const uint8_t skl_std_y_2d_miptail_offset_el[][5][2] = {
504 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
505 { {32, 0}, {64, 0}, {64, 0}, {128, 0}, {128, 0} },
506 { { 0, 32}, { 0, 32}, { 0, 64}, { 0, 64}, { 0,128} },
507 { {16, 0}, {32, 0}, {32, 0}, { 64, 0}, { 64, 0} },
508 { { 0, 16}, { 0, 16}, { 0, 32}, { 0, 32}, { 0, 64} },
509 { { 8, 0}, {16, 0}, {16, 0}, { 32, 0}, { 32, 0} },
510 { { 4, 8}, { 8, 8}, { 8, 16}, { 16, 16}, { 16, 32} },
511 { { 0, 12}, { 0, 12}, { 0, 24}, { 0, 24}, { 0, 48} },
512 { { 0, 8}, { 0, 8}, { 0, 16}, { 0, 16}, { 0, 32} },
513 { { 4, 4}, { 8, 4}, { 8, 8}, { 16, 8}, { 16, 16} },
514 { { 4, 0}, { 8, 0}, { 8, 0}, { 16, 0}, { 16, 0} },
515 { { 0, 4}, { 0, 4}, { 0, 8}, { 0, 8}, { 0, 16} },
516 { { 3, 0}, { 6, 0}, { 4, 4}, { 8, 4}, { 0, 12} },
517 { { 2, 0}, { 4, 0}, { 4, 0}, { 8, 0}, { 0, 8} },
518 { { 1, 0}, { 2, 0}, { 0, 4}, { 0, 4}, { 0, 4} },
519 { { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0} },
520 };
521
522 static const uint8_t icl_std_y_2d_miptail_offset_el[][5][2] = {
523 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
524 { {32, 0}, {64, 0}, {64, 0}, {128, 0}, {128, 0} },
525 { { 0, 32}, { 0, 32}, { 0, 64}, { 0, 64}, { 0, 128} },
526 { {16, 0}, {32, 0}, {32, 0}, { 64, 0}, { 64, 0} },
527 { { 0, 16}, { 0, 16}, { 0, 32}, { 0, 32}, { 0, 64} },
528 { { 8, 0}, {16, 0}, {16, 0}, { 32, 0}, { 32, 0} },
529 { { 4, 8}, { 8, 8}, { 8, 16}, { 16, 16}, { 16, 32} },
530 { { 0, 12}, { 0, 12}, { 0, 24}, { 0, 24}, { 0, 48} },
531 { { 0, 8}, { 0, 8}, { 0, 16}, { 0, 16}, { 0, 32} },
532 { { 4, 4}, { 8, 4}, { 8, 8}, { 16, 8}, { 16, 16} },
533 { { 4, 0}, { 8, 0}, { 8, 0}, { 16, 0}, { 16, 0} },
534 { { 0, 4}, { 0, 4}, { 0, 8}, { 0, 8}, { 0, 16} },
535 { { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0} },
536 { { 1, 0}, { 2, 0}, { 0, 4}, { 0, 4}, { 0, 4} },
537 { { 2, 0}, { 4, 0}, { 4, 0}, { 8, 0}, { 0, 8} },
538 { { 3, 0}, { 6, 0}, { 4, 4}, { 8, 4}, { 0, 12} },
539 };
540
541 static const uint8_t skl_std_y_3d_miptail_offset_el[][5][3] = {
542 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
543 { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0} },
544 { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0} },
545 { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16} },
546 { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0} },
547 { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0} },
548 { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8} },
549 { {3, 0, 0}, { 6, 0, 0}, { 4, 4, 0}, { 0, 4, 4}, { 0, 4, 4} },
550 { {2, 0, 0}, { 4, 0, 0}, { 0, 4, 0}, { 0, 4, 0}, { 0, 4, 0} },
551 { {1, 0, 3}, { 2, 0, 3}, { 4, 0, 3}, { 0, 0, 7}, { 0, 0, 7} },
552 { {1, 0, 2}, { 2, 0, 2}, { 4, 0, 2}, { 0, 0, 6}, { 0, 0, 6} },
553 { {1, 0, 1}, { 2, 0, 1}, { 4, 0, 1}, { 0, 0, 5}, { 0, 0, 5} },
554 { {1, 0, 0}, { 2, 0, 0}, { 4, 0, 0}, { 0, 0, 4}, { 0, 0, 4} },
555 { {0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3} },
556 { {0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2} },
557 { {0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1} },
558 { {0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0} },
559 };
560
561 static const uint8_t icl_std_y_3d_miptail_offset_el[][5][3] = {
562 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
563 { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0} },
564 { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0} },
565 { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16} },
566 { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0} },
567 { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0} },
568 { {2, 0, 4}, { 4, 0, 4}, { 4, 0, 4}, { 4, 0, 8}, { 8, 0, 8} },
569 { {0, 2, 4}, { 0, 2, 4}, { 0, 4, 4}, { 0, 4, 8}, { 0, 4, 8} },
570 { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8} },
571 { {2, 2, 0}, { 4, 2, 0}, { 4, 4, 0}, { 4, 4, 0}, { 8, 4, 0} },
572 { {2, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 8, 0, 0} },
573 { {0, 2, 0}, { 0, 2, 0}, { 0, 4, 0}, { 0, 4, 0}, { 0, 4, 0} },
574 { {1, 0, 2}, { 2, 0, 2}, { 2, 0, 2}, { 2, 0, 4}, { 4, 0, 4} },
575 { {0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 4}, { 0, 0, 4} },
576 { {1, 0, 0}, { 2, 0, 0}, { 2, 0, 0}, { 2, 0, 0}, { 4, 0, 0} },
577 { {0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0} },
578 };
579
580 static const uint8_t acm_tile64_3d_miptail_offset_el[][5][3] = {
581 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
582 { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0}, },
583 { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0}, },
584 { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16}, },
585 { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0}, },
586 { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, },
587 { {2, 0, 4}, { 4, 0, 4}, { 4, 0, 4}, { 0, 4, 8}, { 0, 4, 8}, },
588 { {1, 0, 4}, { 2, 0, 4}, { 0, 4, 4}, { 0, 0, 12}, { 0, 0, 12}, },
589 { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8}, },
590 { {3, 0, 0}, { 6, 0, 0}, { 4, 4, 0}, { 0, 4, 4}, { 0, 4, 4}, },
591 { {2, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 0, 4, 0}, { 0, 4, 0}, },
592 { {1, 0, 0}, { 2, 0, 0}, { 0, 4, 0}, { 0, 0, 4}, { 0, 0, 4}, },
593 { {0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, },
594 { {0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, },
595 { {0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, },
596 { {0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, },
597 };
598
599 static uint32_t
tiling_max_mip_tail(enum isl_tiling tiling,enum isl_surf_dim dim,uint32_t samples)600 tiling_max_mip_tail(enum isl_tiling tiling,
601 enum isl_surf_dim dim,
602 uint32_t samples)
603 {
604 /* In theory, miptails work for multisampled images, but we don't support
605 * mipmapped multisampling.
606 *
607 * BSpec 58770: Xe2 does not support miptails on multisampled images.
608 */
609 if (samples > 1)
610 return 0;
611
612 int num_2d_table_rows;
613 int num_3d_table_rows;
614
615 switch (tiling) {
616 case ISL_TILING_LINEAR:
617 case ISL_TILING_X:
618 case ISL_TILING_Y0:
619 case ISL_TILING_4:
620 case ISL_TILING_W:
621 case ISL_TILING_HIZ:
622 case ISL_TILING_CCS:
623 /* There is no miptail for those tilings */
624 return 0;
625
626 case ISL_TILING_SKL_Yf:
627 case ISL_TILING_SKL_Ys:
628 /* SKL PRMs, Volume 5: Memory Views :
629 *
630 * Given by the last row of the table in the following sections:
631 *
632 * - Tiling and Mip Tail for 1D Surfaces
633 * - Tiling and Mip Tail for 2D Surfaces
634 * - Tiling and Mip Tail for 3D Surfaces
635 */
636 num_2d_table_rows = ARRAY_SIZE(skl_std_y_2d_miptail_offset_el);
637 num_3d_table_rows = ARRAY_SIZE(skl_std_y_3d_miptail_offset_el);
638 break;
639
640 case ISL_TILING_ICL_Yf:
641 case ISL_TILING_ICL_Ys:
642 /* ICL PRMs, Volume 5: Memory Views :
643 *
644 * - Tiling and Mip Tail for 1D Surfaces :
645 * "There is no MIP Tail allowed for 1D surfaces because they are
646 * not allowed to be tiled. They must be declared as linear."
647 * - Tiling and Mip Tail for 2D Surfaces
648 * - Tiling and Mip Tail for 3D Surfaces
649 */
650 num_2d_table_rows = ARRAY_SIZE(icl_std_y_2d_miptail_offset_el);
651 num_3d_table_rows = ARRAY_SIZE(icl_std_y_3d_miptail_offset_el);
652 break;
653
654 case ISL_TILING_64:
655 case ISL_TILING_64_XE2:
656 /* ATS-M PRMS, Volume 5: Memory Data Formats :
657 *
658 * - Tiling and Mip Tail for 1D Surfaces :
659 * "There is no MIP Tail allowed for 1D surfaces because they are
660 * not allowed to be tiled. They must be declared as linear."
661 * - Tiling and Mip Tail for 2D Surfaces
662 * - Tiling and Mip Tail for 3D Surfaces
663 */
664 num_2d_table_rows = ARRAY_SIZE(icl_std_y_2d_miptail_offset_el);
665 num_3d_table_rows = ARRAY_SIZE(acm_tile64_3d_miptail_offset_el);
666 break;
667
668 default:
669 unreachable("Invalid tiling");
670 }
671
672 assert(dim != ISL_SURF_DIM_1D);
673 const int num_rows = dim == ISL_SURF_DIM_2D ? num_2d_table_rows :
674 num_3d_table_rows;
675 return num_rows - isl_get_miptail_base_row(tiling);
676 }
677
678 /**
679 * Returns an isl_tile_info representation of the given isl_tiling when
680 * combined when used in the given configuration.
681 *
682 * :param tiling: |in| The tiling format to introspect
683 * :param dim: |in| The dimensionality of the surface being tiled
684 * :param msaa_layout: |in| The layout of samples in the surface being tiled
685 * :param format_bpb: |in| The number of bits per surface element (block) for
686 * the surface being tiled
687 * :param samples: |in| The samples in the surface being tiled
688 * :param tile_info: |out| Return parameter for the tiling information
689 */
690 void
isl_tiling_get_info(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,uint32_t format_bpb,uint32_t samples,struct isl_tile_info * tile_info)691 isl_tiling_get_info(enum isl_tiling tiling,
692 enum isl_surf_dim dim,
693 enum isl_msaa_layout msaa_layout,
694 uint32_t format_bpb,
695 uint32_t samples,
696 struct isl_tile_info *tile_info)
697 {
698 const uint32_t bs = format_bpb / 8;
699 struct isl_extent4d logical_el;
700 struct isl_extent2d phys_B;
701
702 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) {
703 /* It is possible to have non-power-of-two formats in a tiled buffer.
704 * The easiest way to handle this is to treat the tile as if it is three
705 * times as wide. This way no pixel will ever cross a tile boundary.
706 * This really only works on a subset of tiling formats.
707 */
708 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0 ||
709 tiling == ISL_TILING_4);
710 assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
711 isl_tiling_get_info(tiling, dim, msaa_layout, format_bpb / 3, samples,
712 tile_info);
713 return;
714 }
715
716 switch (tiling) {
717 case ISL_TILING_LINEAR:
718 assert(bs > 0);
719 logical_el = isl_extent4d(1, 1, 1, 1);
720 phys_B = isl_extent2d(bs, 1);
721 break;
722
723 case ISL_TILING_X:
724 assert(bs > 0);
725 logical_el = isl_extent4d(512 / bs, 8, 1, 1);
726 phys_B = isl_extent2d(512, 8);
727 break;
728
729 case ISL_TILING_Y0:
730 case ISL_TILING_4:
731 assert(bs > 0);
732 logical_el = isl_extent4d(128 / bs, 32, 1, 1);
733 phys_B = isl_extent2d(128, 32);
734 break;
735
736 case ISL_TILING_W:
737 assert(bs == 1);
738 logical_el = isl_extent4d(64, 64, 1, 1);
739 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
740 *
741 * "If the surface is a stencil buffer (and thus has Tile Mode set
742 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
743 * computed based on width, as the stencil buffer is stored with two
744 * rows interleaved."
745 *
746 * This, together with the fact that stencil buffers are referred to as
747 * being Y-tiled in the PRMs for older hardware implies that the
748 * physical size of a W-tile is actually the same as for a Y-tile.
749 */
750 phys_B = isl_extent2d(128, 32);
751 break;
752
753 case ISL_TILING_SKL_Yf:
754 case ISL_TILING_SKL_Ys:
755 case ISL_TILING_ICL_Yf:
756 case ISL_TILING_ICL_Ys: {
757 bool is_Ys = tiling == ISL_TILING_SKL_Ys ||
758 tiling == ISL_TILING_ICL_Ys;
759 assert(format_bpb >= 8);
760
761 switch (dim) {
762 case ISL_SURF_DIM_2D:
763 /* See the BSpec Memory Data Formats » Common Surface Formats »
764 * Surface Layout and Tiling [SKL+] » 2D Surfaces SKL+ » 2D/CUBE
765 * Alignment Requirement [SKL+]
766 *
767 * Or, look in the SKL PRM under Memory Views > Common Surface
768 * Formats > Surface Layout and Tiling > 2D Surfaces > 2D/CUBE
769 * Alignment Requirements.
770 */
771 logical_el = (struct isl_extent4d) {
772 .w = 1 << (6 - ((ffs(format_bpb) - 4) / 2) + (2 * is_Ys)),
773 .h = 1 << (6 - ((ffs(format_bpb) - 3) / 2) + (2 * is_Ys)),
774 .d = 1,
775 .a = 1,
776 };
777
778 if (samples > 1 && tiling != ISL_TILING_SKL_Yf) {
779 /* SKL PRMs, Volume 5: Memory Views, 2D/CUBE Alignment
780 * Requirement:
781 *
782 * "For MSFMT_MSS type multi-sampled TileYS surfaces, the
783 * alignments given above must be divided by the appropriate
784 * value from the table below."
785 *
786 * The formulas below reproduce those values.
787 */
788 if (msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
789 logical_el.w >>= (ffs(samples) - 0) / 2;
790 logical_el.h >>= (ffs(samples) - 1) / 2;
791 logical_el.a = samples;
792 }
793 }
794 break;
795
796 case ISL_SURF_DIM_3D:
797 /* See the BSpec Memory Data Formats » Common Surface Formats »
798 * Surface Layout and Tiling [SKL+] » 3D Surfaces SKL+ » 3D Alignment
799 * Requirements [SKL+]
800 *
801 * Or, look in the SKL PRM under Memory Views > Common Surface
802 * Formats > Surface Layout and Tiling > 3D Surfaces > 3D Alignment
803 * Requirements.
804 */
805 logical_el = (struct isl_extent4d) {
806 .w = 1 << (4 - ((ffs(format_bpb) - 2) / 3) + (2 * is_Ys)),
807 .h = 1 << (4 - ((ffs(format_bpb) - 4) / 3) + (1 * is_Ys)),
808 .d = 1 << (4 - ((ffs(format_bpb) - 3) / 3) + (1 * is_Ys)),
809 .a = 1,
810 };
811 break;
812 default:
813 unreachable("Invalid dimension");
814 }
815
816 uint32_t tile_size_B = is_Ys ? (1 << 16) : (1 << 12);
817
818 phys_B.w = logical_el.width * bs;
819 phys_B.h = tile_size_B / phys_B.w;
820 break;
821 }
822 case ISL_TILING_64:
823 /* The tables below are taken from the "2D Surfaces" & "3D Surfaces"
824 * pages in the Bspec which are formulated in terms of the Cv and Cu
825 * constants. This is different from the tables in the "Tile64 Format"
826 * page which should be equivalent but are usually in terms of pixels.
827 * Also note that Cv and Cu are HxW order to match the Bspec table, not
828 * WxH order like you might expect.
829 *
830 * From the Bspec's or ATS-M PRMs Volume 5: Memory Data Formats, "Tile64
831 * Format" :
832 *
833 * MSAA Depth/Stencil surface use IMS (Interleaved Multi Samples)
834 * which means:
835 *
836 * - Use the 1X MSAA (non-MSRT) version of the Tile64 equations and
837 * let the client unit do the swizzling internally
838 *
839 * Surfaces using the IMS layout will use the mapping for 1x MSAA.
840 */
841 #define tile_extent2d(bs, cv, cu, a) \
842 isl_extent4d((1 << cu) / bs, 1 << cv, 1, a)
843 #define tile_extent3d(bs, cr, cv, cu) \
844 isl_extent4d((1 << cu) / bs, 1 << cv, 1 << cr, 1)
845
846 if (dim == ISL_SURF_DIM_3D) {
847 switch (format_bpb) {
848 case 128: logical_el = tile_extent3d(bs, 4, 4, 8); break;
849 case 64: logical_el = tile_extent3d(bs, 4, 4, 8); break;
850 case 32: logical_el = tile_extent3d(bs, 4, 5, 7); break;
851 case 16: logical_el = tile_extent3d(bs, 5, 5, 6); break;
852 case 8: logical_el = tile_extent3d(bs, 5, 5, 6); break;
853 default: unreachable("Unsupported format size for 3D");
854 }
855 } else {
856 if (samples == 1 || msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
857 switch (format_bpb) {
858 case 128: logical_el = tile_extent2d(bs, 6, 10, 1); break;
859 case 64: logical_el = tile_extent2d(bs, 6, 10, 1); break;
860 case 32: logical_el = tile_extent2d(bs, 7, 9, 1); break;
861 case 16: logical_el = tile_extent2d(bs, 7, 9, 1); break;
862 case 8: logical_el = tile_extent2d(bs, 8, 8, 1); break;
863 default: unreachable("Unsupported format size.");
864 }
865 } else if (samples == 2) {
866 switch (format_bpb) {
867 case 128: logical_el = tile_extent2d(bs, 6, 9, 2); break;
868 case 64: logical_el = tile_extent2d(bs, 6, 9, 2); break;
869 case 32: logical_el = tile_extent2d(bs, 7, 8, 2); break;
870 case 16: logical_el = tile_extent2d(bs, 7, 8, 2); break;
871 case 8: logical_el = tile_extent2d(bs, 8, 7, 2); break;
872 default: unreachable("Unsupported format size.");
873 }
874 } else {
875 switch (format_bpb) {
876 case 128: logical_el = tile_extent2d(bs, 5, 9, 4); break;
877 case 64: logical_el = tile_extent2d(bs, 5, 9, 4); break;
878 case 32: logical_el = tile_extent2d(bs, 6, 8, 4); break;
879 case 16: logical_el = tile_extent2d(bs, 6, 8, 4); break;
880 case 8: logical_el = tile_extent2d(bs, 7, 7, 4); break;
881 default: unreachable("Unsupported format size.");
882 }
883 }
884 }
885
886 #undef tile_extent2d
887 #undef tile_extent3d
888
889 phys_B.w = logical_el.w * bs;
890 phys_B.h = 64 * 1024 / phys_B.w;
891 break;
892
893 case ISL_TILING_64_XE2:
894 /* The tables below are taken from BSpec 58767 which are formulated in
895 * terms of the Cv and Cu constants. This is different from the tables in
896 * the "Tile64 Format" page which should be equivalent but are usually in
897 * terms of pixels.
898 *
899 * Also note that Cv and Cu are HxW order to match the Bspec table, not
900 * WxH order like you might expect.
901 */
902 #define tile_extent2d(bs, cv, cu, a) \
903 isl_extent4d((1 << cu) / bs, 1 << cv, 1, a)
904 #define tile_extent3d(bs, cr, cv, cu) \
905 isl_extent4d((1 << cu) / bs, 1 << cv, 1 << cr, 1)
906
907 if (dim == ISL_SURF_DIM_3D) {
908 switch (format_bpb) {
909 case 128: logical_el = tile_extent3d(bs, 4, 4, 8); break;
910 case 64: logical_el = tile_extent3d(bs, 4, 4, 8); break;
911 case 32: logical_el = tile_extent3d(bs, 4, 5, 7); break;
912 case 16: logical_el = tile_extent3d(bs, 5, 5, 6); break;
913 case 8: logical_el = tile_extent3d(bs, 5, 5, 6); break;
914 default: unreachable("Unsupported format size for 3D");
915 }
916 } else {
917 if (samples == 1 || msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
918 switch (format_bpb) {
919 case 128: logical_el = tile_extent2d(bs, 6, 10, 1); break;
920 case 64: logical_el = tile_extent2d(bs, 6, 10, 1); break;
921 case 32: logical_el = tile_extent2d(bs, 7, 9, 1); break;
922 case 16: logical_el = tile_extent2d(bs, 7, 9, 1); break;
923 case 8: logical_el = tile_extent2d(bs, 8, 8, 1); break;
924 default: unreachable("Unsupported format size.");
925 }
926 } else if (samples == 2) {
927 switch (format_bpb) {
928 case 128: logical_el = tile_extent2d(bs, 5, 10, 2); break;
929 case 64: logical_el = tile_extent2d(bs, 6, 9, 2); break;
930 case 32: logical_el = tile_extent2d(bs, 7, 8, 2); break;
931 case 16: logical_el = tile_extent2d(bs, 7, 8, 2); break;
932 case 8: logical_el = tile_extent2d(bs, 8, 7, 2); break;
933 default: unreachable("Unsupported format size.");
934 }
935 } else if (samples == 4) {
936 switch (format_bpb) {
937 case 128: logical_el = tile_extent2d(bs, 5, 9, 4); break;
938 case 64: logical_el = tile_extent2d(bs, 5, 9, 4); break;
939 case 32: logical_el = tile_extent2d(bs, 6, 8, 4); break;
940 case 16: logical_el = tile_extent2d(bs, 6, 8, 4); break;
941 case 8: logical_el = tile_extent2d(bs, 7, 7, 4); break;
942 default: unreachable("Unsupported format size.");
943 }
944 } else if (samples == 8) {
945 switch (format_bpb) {
946 case 128: logical_el = tile_extent2d(bs, 5, 8, 8); break;
947 case 64: logical_el = tile_extent2d(bs, 5, 8, 8); break;
948 case 32: logical_el = tile_extent2d(bs, 5, 8, 8); break;
949 case 16: logical_el = tile_extent2d(bs, 6, 7, 8); break;
950 case 8: logical_el = tile_extent2d(bs, 6, 7, 8); break;
951 default: unreachable("Unsupported format size.");
952 }
953 } else if (samples == 16) {
954 switch (format_bpb) {
955 case 128: logical_el = tile_extent2d(bs, 4, 8, 16); break;
956 case 64: logical_el = tile_extent2d(bs, 5, 7, 16); break;
957 case 32: logical_el = tile_extent2d(bs, 5, 7, 16); break;
958 case 16: logical_el = tile_extent2d(bs, 5, 7, 16); break;
959 case 8: logical_el = tile_extent2d(bs, 6, 6, 16); break;
960 default: unreachable("Unsupported format size.");
961 }
962 }
963 }
964
965 #undef tile_extent2d
966 #undef tile_extent3d
967
968 phys_B.w = logical_el.w * bs;
969 phys_B.h = 64 * 1024 / phys_B.w;
970 break;
971
972 case ISL_TILING_HIZ:
973 /* HiZ buffers are required to have a 128bpb HiZ format. The tiling has
974 * the same physical dimensions as Y-tiling but actually has two HiZ
975 * columns per Y-tiled column.
976 */
977 assert(bs == 16);
978 logical_el = isl_extent4d(16, 16, 1, 1);
979 phys_B = isl_extent2d(128, 32);
980 break;
981
982 case ISL_TILING_CCS:
983 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
984 * have a block size of 1 or 2 bits per block and each CCS element
985 * corresponds to one cache-line pair in the main surface. From the Sky
986 * Lake PRM Vol. 12 in the section on planes:
987 *
988 * "The Color Control Surface (CCS) contains the compression status
989 * of the cache-line pairs. The compression state of the cache-line
990 * pair is specified by 2 bits in the CCS. Each CCS cache-line
991 * represents an area on the main surface of 16x16 sets of 128 byte
992 * Y-tiled cache-line-pairs. CCS is always Y tiled."
993 *
994 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
995 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
996 * that yields total tile area of 128x128 cache-line pairs or CCS
997 * elements. On older hardware, each CCS element is 1 bit and the tile
998 * is 128x256 elements.
999 */
1000 assert(format_bpb == 1 || format_bpb == 2);
1001 logical_el = isl_extent4d(128, 256 / format_bpb, 1, 1);
1002 phys_B = isl_extent2d(128, 32);
1003 break;
1004
1005 default:
1006 unreachable("not reached");
1007 } /* end switch */
1008
1009 *tile_info = (struct isl_tile_info) {
1010 .tiling = tiling,
1011 .format_bpb = format_bpb,
1012 .logical_extent_el = logical_el,
1013 .phys_extent_B = phys_B,
1014 .max_miptail_levels = tiling_max_mip_tail(tiling, dim, samples),
1015 };
1016 }
1017
1018 bool
isl_color_value_is_zero(union isl_color_value value,enum isl_format format)1019 isl_color_value_is_zero(union isl_color_value value,
1020 enum isl_format format)
1021 {
1022 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
1023
1024 #define RETURN_FALSE_IF_NOT_0(c, i) \
1025 if (fmtl->channels.c.bits && value.u32[i] != 0) \
1026 return false
1027
1028 RETURN_FALSE_IF_NOT_0(r, 0);
1029 RETURN_FALSE_IF_NOT_0(g, 1);
1030 RETURN_FALSE_IF_NOT_0(b, 2);
1031 RETURN_FALSE_IF_NOT_0(a, 3);
1032
1033 #undef RETURN_FALSE_IF_NOT_0
1034
1035 return true;
1036 }
1037
1038 bool
isl_color_value_is_zero_one(union isl_color_value value,enum isl_format format)1039 isl_color_value_is_zero_one(union isl_color_value value,
1040 enum isl_format format)
1041 {
1042 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
1043
1044 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
1045 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
1046 return false
1047
1048 if (isl_format_has_int_channel(format)) {
1049 RETURN_FALSE_IF_NOT_0_1(r, 0, u32);
1050 RETURN_FALSE_IF_NOT_0_1(g, 1, u32);
1051 RETURN_FALSE_IF_NOT_0_1(b, 2, u32);
1052 RETURN_FALSE_IF_NOT_0_1(a, 3, u32);
1053 } else {
1054 RETURN_FALSE_IF_NOT_0_1(r, 0, f32);
1055 RETURN_FALSE_IF_NOT_0_1(g, 1, f32);
1056 RETURN_FALSE_IF_NOT_0_1(b, 2, f32);
1057 RETURN_FALSE_IF_NOT_0_1(a, 3, f32);
1058 }
1059
1060 #undef RETURN_FALSE_IF_NOT_0_1
1061
1062 return true;
1063 }
1064
1065 /**
1066 * @param[out] tiling is set only on success
1067 */
1068 static bool
isl_surf_choose_tiling(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling * tiling)1069 isl_surf_choose_tiling(const struct isl_device *dev,
1070 const struct isl_surf_init_info *restrict info,
1071 enum isl_tiling *tiling)
1072 {
1073 isl_tiling_flags_t tiling_flags = info->tiling_flags;
1074
1075 /* HiZ surfaces always use the HiZ tiling */
1076 if (info->usage & ISL_SURF_USAGE_HIZ_BIT) {
1077 assert(isl_format_is_hiz(info->format));
1078 assert(tiling_flags == ISL_TILING_HIZ_BIT);
1079 *tiling = isl_tiling_flag_to_enum(tiling_flags);
1080 return true;
1081 }
1082
1083 /* CCS surfaces always use the CCS tiling */
1084 if (info->usage & ISL_SURF_USAGE_CCS_BIT) {
1085 assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS);
1086 assert(tiling_flags == ISL_TILING_CCS_BIT);
1087 *tiling = isl_tiling_flag_to_enum(tiling_flags);
1088 return true;
1089 }
1090
1091 if (ISL_GFX_VERX10(dev) >= 200) {
1092 isl_gfx20_filter_tiling(dev, info, &tiling_flags);
1093 } else if (ISL_GFX_VERX10(dev) >= 125) {
1094 isl_gfx125_filter_tiling(dev, info, &tiling_flags);
1095 } else if (ISL_GFX_VER(dev) >= 6) {
1096 isl_gfx6_filter_tiling(dev, info, &tiling_flags);
1097 } else {
1098 isl_gfx4_filter_tiling(dev, info, &tiling_flags);
1099 }
1100
1101 #define CHOOSE(__tiling) \
1102 do { \
1103 if (tiling_flags & (1u << (__tiling))) { \
1104 *tiling = (__tiling); \
1105 return true; \
1106 } \
1107 } while (0)
1108
1109 /* Of the tiling modes remaining, choose the one that offers the best
1110 * performance.
1111 */
1112
1113 if (info->dim == ISL_SURF_DIM_1D) {
1114 /* Prefer linear for 1D surfaces because they do not benefit from
1115 * tiling. To the contrary, tiling leads to wasted memory and poor
1116 * memory locality due to the swizzling and alignment restrictions
1117 * required in tiled surfaces.
1118 */
1119 CHOOSE(ISL_TILING_LINEAR);
1120 }
1121
1122 if (intel_needs_workaround(dev->info, 22015614752) &&
1123 _isl_surf_info_supports_ccs(dev, info->format, info->usage) &&
1124 (info->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
1125 (info->levels > 1 || info->depth > 1 || info->array_len > 1)) {
1126 /* There are issues with multiple engines accessing the same CCS
1127 * cacheline in parallel. This can happen if this image has multiple
1128 * subresources. If possible, avoid such conflicts by picking a tiling
1129 * that will increase the subresource alignment to 64k. If we can't use
1130 * such a tiling, we'll prevent CCS from being enabled later on via
1131 * isl_surf_supports_ccs.
1132 */
1133 CHOOSE(ISL_TILING_64);
1134 }
1135
1136 /* For sparse images, prefer the formats that use the standard block
1137 * shapes.
1138 */
1139 if (info->usage & ISL_SURF_USAGE_SPARSE_BIT) {
1140 CHOOSE(ISL_TILING_64_XE2);
1141 CHOOSE(ISL_TILING_64);
1142 CHOOSE(ISL_TILING_ICL_Ys);
1143 CHOOSE(ISL_TILING_SKL_Ys);
1144 }
1145
1146 /* Choose suggested 4K tilings first, then 64K tilings:
1147 *
1148 * Then following quotes can be found in the SKL PRMs,
1149 * Volume 5: Memory Views, Address Tiling Function Introduction
1150 * and from the ATS-M PRMs,
1151 * Volume 5: Memory Data Formats, Address Tiling Function Introduction
1152 *
1153 * "TileY: Used for most tiled surfaces when TR_MODE=TR_NONE."
1154 * "Tile4: 4KB tiling mode based on previously-supported TileY"
1155 * "TileYF: 4KB tiling mode based on TileY"
1156 * "TileYS: 64KB tiling mode based on TileY"
1157 * "Tile64: 64KB tiling mode which support standard-tiling including
1158 * Mip Tails"
1159 *
1160 * When TileYF and TileYS are used TR_MODE != TR_NONE.
1161 */
1162 CHOOSE(ISL_TILING_Y0);
1163 CHOOSE(ISL_TILING_4);
1164 CHOOSE(ISL_TILING_SKL_Yf);
1165 CHOOSE(ISL_TILING_ICL_Yf);
1166 CHOOSE(ISL_TILING_SKL_Ys);
1167 CHOOSE(ISL_TILING_ICL_Ys);
1168 CHOOSE(ISL_TILING_64);
1169 CHOOSE(ISL_TILING_64_XE2);
1170
1171 CHOOSE(ISL_TILING_X);
1172 CHOOSE(ISL_TILING_W);
1173 CHOOSE(ISL_TILING_LINEAR);
1174
1175 #undef CHOOSE
1176
1177 /* No tiling mode accommodates the inputs. */
1178 assert(tiling_flags == 0);
1179 return notify_failure(info, "no supported tiling");
1180 }
1181
1182 static bool
isl_choose_msaa_layout(const struct isl_device * dev,const struct isl_surf_init_info * info,enum isl_tiling tiling,enum isl_msaa_layout * msaa_layout)1183 isl_choose_msaa_layout(const struct isl_device *dev,
1184 const struct isl_surf_init_info *info,
1185 enum isl_tiling tiling,
1186 enum isl_msaa_layout *msaa_layout)
1187 {
1188 if (ISL_GFX_VER(dev) >= 8) {
1189 return isl_gfx8_choose_msaa_layout(dev, info, tiling, msaa_layout);
1190 } else if (ISL_GFX_VER(dev) >= 7) {
1191 return isl_gfx7_choose_msaa_layout(dev, info, tiling, msaa_layout);
1192 } else if (ISL_GFX_VER(dev) >= 6) {
1193 return isl_gfx6_choose_msaa_layout(dev, info, tiling, msaa_layout);
1194 } else {
1195 return isl_gfx4_choose_msaa_layout(dev, info, tiling, msaa_layout);
1196 }
1197 }
1198
1199 struct isl_extent2d
isl_get_interleaved_msaa_px_size_sa(uint32_t samples)1200 isl_get_interleaved_msaa_px_size_sa(uint32_t samples)
1201 {
1202 assert(isl_is_pow2(samples));
1203
1204 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
1205 * Sizes (p133):
1206 *
1207 * If the surface is multisampled and it is a depth or stencil surface
1208 * or Multisampled Surface StorageFormat in SURFACE_STATE is
1209 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
1210 * proceeding: [...]
1211 */
1212 return (struct isl_extent2d) {
1213 .width = 1 << ((ffs(samples) - 0) / 2),
1214 .height = 1 << ((ffs(samples) - 1) / 2),
1215 };
1216 }
1217
1218 static void
isl_msaa_interleaved_scale_px_to_sa(uint32_t samples,uint32_t * width,uint32_t * height)1219 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples,
1220 uint32_t *width, uint32_t *height)
1221 {
1222 const struct isl_extent2d px_size_sa =
1223 isl_get_interleaved_msaa_px_size_sa(samples);
1224
1225 if (width)
1226 *width = isl_align(*width, 2) * px_size_sa.width;
1227 if (height)
1228 *height = isl_align(*height, 2) * px_size_sa.height;
1229 }
1230
1231 static enum isl_array_pitch_span
isl_choose_array_pitch_span(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_dim_layout dim_layout,const struct isl_extent4d * phys_level0_sa)1232 isl_choose_array_pitch_span(const struct isl_device *dev,
1233 const struct isl_surf_init_info *restrict info,
1234 enum isl_dim_layout dim_layout,
1235 const struct isl_extent4d *phys_level0_sa)
1236 {
1237 switch (dim_layout) {
1238 case ISL_DIM_LAYOUT_GFX9_1D:
1239 case ISL_DIM_LAYOUT_GFX4_2D:
1240 if (ISL_GFX_VER(dev) >= 8) {
1241 /* QPitch becomes programmable in Broadwell. So choose the
1242 * most compact QPitch possible in order to conserve memory.
1243 *
1244 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
1245 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
1246 *
1247 * - Software must ensure that this field is set to a value
1248 * sufficiently large such that the array slices in the surface
1249 * do not overlap. Refer to the Memory Data Formats section for
1250 * information on how surfaces are stored in memory.
1251 *
1252 * - This field specifies the distance in rows between array
1253 * slices. It is used only in the following cases:
1254 *
1255 * - Surface Array is enabled OR
1256 * - Number of Mulitsamples is not NUMSAMPLES_1 and
1257 * Multisampled Surface Storage Format set to MSFMT_MSS OR
1258 * - Surface Type is SURFTYPE_CUBE
1259 */
1260 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1261 } else if (ISL_GFX_VER(dev) >= 7) {
1262 /* Note that Ivybridge introduces
1263 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
1264 * driver more control over the QPitch.
1265 */
1266
1267 if (phys_level0_sa->array_len == 1) {
1268 /* The hardware will never use the QPitch. So choose the most
1269 * compact QPitch possible in order to conserve memory.
1270 */
1271 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1272 }
1273
1274 if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
1275 (info->usage & ISL_SURF_USAGE_HIZ_BIT)) {
1276 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
1277 * Section 6.18.4.7: Surface Arrays (p112):
1278 *
1279 * If Surface Array Spacing is set to ARYSPC_FULL (note that
1280 * the depth buffer and stencil buffer have an implied value of
1281 * ARYSPC_FULL):
1282 */
1283 return ISL_ARRAY_PITCH_SPAN_FULL;
1284 }
1285
1286 if (info->levels == 1) {
1287 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
1288 * to ARYSPC_LOD0.
1289 */
1290 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1291 }
1292
1293 return ISL_ARRAY_PITCH_SPAN_FULL;
1294 } else if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
1295 ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
1296 isl_surf_usage_is_stencil(info->usage)) {
1297 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1298 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
1299 *
1300 * The separate stencil buffer does not support mip mapping, thus
1301 * the storage for LODs other than LOD 0 is not needed.
1302 */
1303 assert(info->levels == 1);
1304 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1305 } else {
1306 if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
1307 ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
1308 isl_surf_usage_is_stencil(info->usage)) {
1309 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1310 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
1311 *
1312 * The separate stencil buffer does not support mip mapping,
1313 * thus the storage for LODs other than LOD 0 is not needed.
1314 */
1315 assert(info->levels == 1);
1316 assert(phys_level0_sa->array_len == 1);
1317 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1318 }
1319
1320 if (phys_level0_sa->array_len == 1) {
1321 /* The hardware will never use the QPitch. So choose the most
1322 * compact QPitch possible in order to conserve memory.
1323 */
1324 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1325 }
1326
1327 return ISL_ARRAY_PITCH_SPAN_FULL;
1328 }
1329
1330 case ISL_DIM_LAYOUT_GFX4_3D:
1331 /* The hardware will never use the QPitch. So choose the most
1332 * compact QPitch possible in order to conserve memory.
1333 */
1334 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1335
1336 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1337 /* Each array image in the gfx6 stencil of HiZ surface is compact in the
1338 * sense that every LOD is a compact array of the same size as LOD0.
1339 */
1340 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1341 }
1342
1343 unreachable("bad isl_dim_layout");
1344 return ISL_ARRAY_PITCH_SPAN_FULL;
1345 }
1346
1347 static void
isl_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)1348 isl_choose_image_alignment_el(const struct isl_device *dev,
1349 const struct isl_surf_init_info *restrict info,
1350 const struct isl_tile_info *tile_info,
1351 enum isl_dim_layout dim_layout,
1352 enum isl_msaa_layout msaa_layout,
1353 struct isl_extent3d *image_align_el)
1354 {
1355 enum isl_tiling tiling = tile_info->tiling;
1356 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1357 if (fmtl->txc == ISL_TXC_MCS) {
1358 /*
1359 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1360 *
1361 * Height, width, and layout of MCS buffer in this case must match with
1362 * Render Target height, width, and layout. MCS buffer is tiledY.
1363 *
1364 * Pick a vertical and horizontal alignment that matches the main render
1365 * target. Vertical alignment is important for properly spacing an array
1366 * of MCS images. Horizontal alignment is not expected to matter because
1367 * MCS is not mipmapped. Regardless, we pick a valid value here.
1368 */
1369 if (ISL_GFX_VERX10(dev) >= 125) {
1370 *image_align_el = isl_extent3d(128 * 8 / fmtl->bpb, 4, 1);
1371 } else if (ISL_GFX_VER(dev) >= 8) {
1372 *image_align_el = isl_extent3d(16, 4, 1);
1373 } else {
1374 *image_align_el = isl_extent3d(4, 4, 1);
1375 }
1376 return;
1377 } else if (fmtl->txc == ISL_TXC_HIZ) {
1378 assert(ISL_GFX_VER(dev) >= 6);
1379 if (ISL_GFX_VER(dev) == 6) {
1380 /* HiZ surfaces on Sandy Bridge are packed tightly. */
1381 *image_align_el = isl_extent3d(1, 1, 1);
1382 } else if (ISL_GFX_VER(dev) < 12) {
1383 /* On gfx7+, HiZ surfaces are always aligned to 16x8 pixels in the
1384 * primary surface which works out to 2x2 HiZ elements.
1385 */
1386 *image_align_el = isl_extent3d(2, 2, 1);
1387 } else {
1388 /* We choose the alignments based on the docs and what we've seen on
1389 * prior platforms. From the TGL PRM Vol. 9, "Hierarchical Depth
1390 * Buffer":
1391 *
1392 * The height and width of the hierarchical depth buffer that must
1393 * be allocated are computed by the following formulas, where HZ
1394 * is the hierarchical depth buffer and Z is the depth buffer. The
1395 * Z_Height, Z_Width, and Z_Depth values given in these formulas
1396 * are those present in 3DSTATE_DEPTH_BUFFER incremented by one.
1397 *
1398 * The note about 3DSTATE_DEPTH_BUFFER tells us that the dimensions
1399 * in the following formula refers to the base level. The key formula
1400 * for the horizontal alignment is:
1401 *
1402 * HZ_Width (bytes) [=]
1403 * ceiling(Z_Width / 16) * 16
1404 *
1405 * This type of formula is used when sizing compression blocks. So,
1406 * the docs seem to say that the HiZ format has a block width of 16,
1407 * and thus, the surface has a minimum horizontal alignment of 16
1408 * pixels. This formula hasn't changed from prior platforms (where
1409 * we've chosen a horizontal alignment of 16), so we should be on the
1410 * right track. As for the vertical alignment, we're told:
1411 *
1412 * To compute the minimum QPitch for the HZ surface, the height of
1413 * each LOD in pixels is determined using the equations for hL in
1414 * the GPU Overview volume, using a vertical alignment j=16.
1415 *
1416 * We're not calculating the QPitch right now, but the vertical
1417 * alignment is plainly given as 16 rows in the depth buffer.
1418 *
1419 * As a result, we believe that HiZ surfaces are aligned to 16x16
1420 * pixels in the primary surface. We divide this area by the HiZ
1421 * block dimensions to get the alignment in terms of HiZ blocks.
1422 */
1423 *image_align_el = isl_extent3d(16 / fmtl->bw, 16 / fmtl->bh, 1);
1424 }
1425 return;
1426 }
1427
1428 if (ISL_GFX_VERX10(dev) >= 200) {
1429 isl_gfx20_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1430 msaa_layout, image_align_el);
1431 } else if (ISL_GFX_VERX10(dev) >= 125) {
1432 isl_gfx125_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1433 msaa_layout, image_align_el);
1434 } else if (ISL_GFX_VER(dev) >= 12) {
1435 isl_gfx12_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1436 msaa_layout, image_align_el);
1437 } else if (ISL_GFX_VER(dev) >= 9) {
1438 isl_gfx9_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1439 msaa_layout, image_align_el);
1440 } else if (ISL_GFX_VER(dev) >= 8) {
1441 isl_gfx8_choose_image_alignment_el(dev, info, tiling, dim_layout,
1442 msaa_layout, image_align_el);
1443 } else if (ISL_GFX_VER(dev) >= 7) {
1444 isl_gfx7_choose_image_alignment_el(dev, info, tiling, dim_layout,
1445 msaa_layout, image_align_el);
1446 } else if (ISL_GFX_VER(dev) >= 6) {
1447 isl_gfx6_choose_image_alignment_el(dev, info, tiling, dim_layout,
1448 msaa_layout, image_align_el);
1449 } else {
1450 isl_gfx4_choose_image_alignment_el(dev, info, tiling, dim_layout,
1451 msaa_layout, image_align_el);
1452 }
1453 }
1454
1455 static enum isl_dim_layout
isl_surf_choose_dim_layout(const struct isl_device * dev,enum isl_surf_dim logical_dim,enum isl_tiling tiling,isl_surf_usage_flags_t usage)1456 isl_surf_choose_dim_layout(const struct isl_device *dev,
1457 enum isl_surf_dim logical_dim,
1458 enum isl_tiling tiling,
1459 isl_surf_usage_flags_t usage)
1460 {
1461 /* Sandy bridge needs a special layout for HiZ and stencil. */
1462 if (ISL_GFX_VER(dev) == 6 &&
1463 (tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ))
1464 return ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ;
1465
1466 if (ISL_GFX_VER(dev) >= 9) {
1467 switch (logical_dim) {
1468 case ISL_SURF_DIM_1D:
1469 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
1470 *
1471 * One-dimensional surfaces use a tiling mode of linear.
1472 * Technically, they are not tiled resources, but the Tiled
1473 * Resource Mode field in RENDER_SURFACE_STATE is still used to
1474 * indicate the alignment requirements for this linear surface
1475 * (See 1D Alignment requirements for how 4K and 64KB Tiled
1476 * Resource Modes impact alignment). Alternatively, a 1D surface
1477 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
1478 * a height of 0.
1479 *
1480 * In other words, ISL_DIM_LAYOUT_GFX9_1D is only used for linear
1481 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GFX4_2D is used.
1482 */
1483 if (tiling == ISL_TILING_LINEAR)
1484 return ISL_DIM_LAYOUT_GFX9_1D;
1485 else
1486 return ISL_DIM_LAYOUT_GFX4_2D;
1487 case ISL_SURF_DIM_2D:
1488 case ISL_SURF_DIM_3D:
1489 return ISL_DIM_LAYOUT_GFX4_2D;
1490 }
1491 } else {
1492 switch (logical_dim) {
1493 case ISL_SURF_DIM_1D:
1494 case ISL_SURF_DIM_2D:
1495 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1496 *
1497 * The cube face textures are stored in the same way as 3D surfaces
1498 * are stored (see section 6.17.5 for details). For cube surfaces,
1499 * however, the depth is equal to the number of faces (always 6) and
1500 * is not reduced for each MIP.
1501 */
1502 if (ISL_GFX_VER(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
1503 return ISL_DIM_LAYOUT_GFX4_3D;
1504
1505 return ISL_DIM_LAYOUT_GFX4_2D;
1506 case ISL_SURF_DIM_3D:
1507 return ISL_DIM_LAYOUT_GFX4_3D;
1508 }
1509 }
1510
1511 unreachable("bad isl_surf_dim");
1512 return ISL_DIM_LAYOUT_GFX4_2D;
1513 }
1514
1515 /**
1516 * Calculate the physical extent of the surface's first level, in units of
1517 * surface samples.
1518 */
1519 static void
isl_calc_phys_level0_extent_sa(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_dim_layout dim_layout,enum isl_tiling tiling,enum isl_msaa_layout msaa_layout,struct isl_extent4d * phys_level0_sa)1520 isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
1521 const struct isl_surf_init_info *restrict info,
1522 enum isl_dim_layout dim_layout,
1523 enum isl_tiling tiling,
1524 enum isl_msaa_layout msaa_layout,
1525 struct isl_extent4d *phys_level0_sa)
1526 {
1527 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1528
1529 if (isl_format_is_planar(info->format))
1530 unreachable("Planar formats unsupported");
1531
1532 switch (info->dim) {
1533 case ISL_SURF_DIM_1D:
1534 assert(info->height == 1);
1535 assert(info->depth == 1);
1536 assert(info->samples == 1);
1537
1538 switch (dim_layout) {
1539 case ISL_DIM_LAYOUT_GFX4_3D:
1540 unreachable("bad isl_dim_layout");
1541
1542 case ISL_DIM_LAYOUT_GFX9_1D:
1543 case ISL_DIM_LAYOUT_GFX4_2D:
1544 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1545 *phys_level0_sa = (struct isl_extent4d) {
1546 .w = info->width,
1547 .h = 1,
1548 .d = 1,
1549 .a = info->array_len,
1550 };
1551 break;
1552 }
1553 break;
1554
1555 case ISL_SURF_DIM_2D:
1556 if (ISL_GFX_VER(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
1557 assert(dim_layout == ISL_DIM_LAYOUT_GFX4_3D);
1558 else
1559 assert(dim_layout == ISL_DIM_LAYOUT_GFX4_2D ||
1560 dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
1561
1562 switch (msaa_layout) {
1563 case ISL_MSAA_LAYOUT_NONE:
1564 assert(info->depth == 1);
1565 assert(info->samples == 1);
1566
1567 *phys_level0_sa = (struct isl_extent4d) {
1568 .w = info->width,
1569 .h = info->height,
1570 .d = 1,
1571 .a = info->array_len,
1572 };
1573 break;
1574
1575 case ISL_MSAA_LAYOUT_ARRAY:
1576 assert(info->depth == 1);
1577 assert(info->levels == 1);
1578 assert(isl_format_supports_multisampling(dev->info, info->format));
1579 assert(fmtl->bw == 1 && fmtl->bh == 1);
1580
1581 *phys_level0_sa = (struct isl_extent4d) {
1582 .w = info->width,
1583 .h = info->height,
1584 .d = 1,
1585 .a = info->array_len * info->samples,
1586 };
1587 break;
1588
1589 case ISL_MSAA_LAYOUT_INTERLEAVED:
1590 assert(info->depth == 1);
1591 assert(info->levels == 1);
1592 assert(isl_format_supports_multisampling(dev->info, info->format));
1593
1594 *phys_level0_sa = (struct isl_extent4d) {
1595 .w = info->width,
1596 .h = info->height,
1597 .d = 1,
1598 .a = info->array_len,
1599 };
1600
1601 isl_msaa_interleaved_scale_px_to_sa(info->samples,
1602 &phys_level0_sa->w,
1603 &phys_level0_sa->h);
1604 break;
1605 }
1606 break;
1607
1608 case ISL_SURF_DIM_3D:
1609 assert(info->array_len == 1);
1610 assert(info->samples == 1);
1611
1612 if (fmtl->bd > 1) {
1613 isl_finishme("%s:%s: compression block with depth > 1",
1614 __FILE__, __func__);
1615 }
1616
1617 switch (dim_layout) {
1618 case ISL_DIM_LAYOUT_GFX9_1D:
1619 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1620 unreachable("bad isl_dim_layout");
1621
1622 case ISL_DIM_LAYOUT_GFX4_2D:
1623 case ISL_DIM_LAYOUT_GFX4_3D:
1624 *phys_level0_sa = (struct isl_extent4d) {
1625 .w = info->width,
1626 .h = info->height,
1627 .d = info->depth,
1628 .a = 1,
1629 };
1630 break;
1631 }
1632 break;
1633 }
1634 }
1635
1636 static void
isl_get_miptail_level_offset_el(enum isl_tiling tiling,enum isl_surf_dim dim,uint32_t format_bpb,uint32_t level,uint32_t * x_offset_el,uint32_t * y_offset_el,uint32_t * z_offset_el)1637 isl_get_miptail_level_offset_el(enum isl_tiling tiling,
1638 enum isl_surf_dim dim,
1639 uint32_t format_bpb,
1640 uint32_t level,
1641 uint32_t *x_offset_el,
1642 uint32_t *y_offset_el,
1643 uint32_t *z_offset_el)
1644 {
1645 uint32_t row = isl_get_miptail_base_row(tiling) + level;
1646 uint32_t col = 8 - ffs(format_bpb);
1647
1648 switch (dim) {
1649 case ISL_SURF_DIM_2D:
1650 switch (tiling) {
1651 case ISL_TILING_64:
1652 case ISL_TILING_64_XE2:
1653 case ISL_TILING_ICL_Yf:
1654 case ISL_TILING_ICL_Ys:
1655 assert(row < ARRAY_SIZE(icl_std_y_2d_miptail_offset_el));
1656 assert(col < ARRAY_SIZE(icl_std_y_2d_miptail_offset_el[0]));
1657 *x_offset_el = icl_std_y_2d_miptail_offset_el[row][col][0];
1658 *y_offset_el = icl_std_y_2d_miptail_offset_el[row][col][1];
1659 break;
1660 case ISL_TILING_SKL_Yf:
1661 case ISL_TILING_SKL_Ys:
1662 assert(row < ARRAY_SIZE(skl_std_y_2d_miptail_offset_el));
1663 assert(col < ARRAY_SIZE(skl_std_y_2d_miptail_offset_el[0]));
1664 *x_offset_el = skl_std_y_2d_miptail_offset_el[row][col][0];
1665 *y_offset_el = skl_std_y_2d_miptail_offset_el[row][col][1];
1666 break;
1667 default:
1668 unreachable("invalid tiling");
1669 }
1670 *z_offset_el = 0;
1671 break;
1672
1673 case ISL_SURF_DIM_3D:
1674 switch (tiling) {
1675 case ISL_TILING_64:
1676 case ISL_TILING_64_XE2:
1677 assert(row < ARRAY_SIZE(acm_tile64_3d_miptail_offset_el));
1678 assert(col < ARRAY_SIZE(acm_tile64_3d_miptail_offset_el[0]));
1679 *x_offset_el = acm_tile64_3d_miptail_offset_el[row][col][0];
1680 *y_offset_el = acm_tile64_3d_miptail_offset_el[row][col][1];
1681 *z_offset_el = acm_tile64_3d_miptail_offset_el[row][col][2];
1682 break;
1683 case ISL_TILING_ICL_Yf:
1684 case ISL_TILING_ICL_Ys:
1685 assert(row < ARRAY_SIZE(icl_std_y_3d_miptail_offset_el));
1686 assert(col < ARRAY_SIZE(icl_std_y_3d_miptail_offset_el[0]));
1687 *x_offset_el = icl_std_y_3d_miptail_offset_el[row][col][0];
1688 *y_offset_el = icl_std_y_3d_miptail_offset_el[row][col][1];
1689 *z_offset_el = icl_std_y_3d_miptail_offset_el[row][col][2];
1690 break;
1691 case ISL_TILING_SKL_Yf:
1692 case ISL_TILING_SKL_Ys:
1693 assert(row < ARRAY_SIZE(skl_std_y_3d_miptail_offset_el));
1694 assert(col < ARRAY_SIZE(skl_std_y_3d_miptail_offset_el[0]));
1695 *x_offset_el = skl_std_y_3d_miptail_offset_el[row][col][0];
1696 *y_offset_el = skl_std_y_3d_miptail_offset_el[row][col][1];
1697 *z_offset_el = skl_std_y_3d_miptail_offset_el[row][col][2];
1698 break;
1699 default:
1700 unreachable("invalid tiling");
1701 }
1702 break;
1703
1704 case ISL_SURF_DIM_1D:
1705 unreachable("invalid dimension");
1706 }
1707 }
1708
1709 static uint32_t
isl_choose_miptail_start_level(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info)1710 isl_choose_miptail_start_level(const struct isl_device *dev,
1711 const struct isl_surf_init_info *restrict info,
1712 const struct isl_tile_info *tile_info)
1713 {
1714 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1715
1716 if (tile_info->max_miptail_levels == 0)
1717 return info->levels;
1718
1719 /* SKL PRMs, Volume 5: Memory Views, YUV 4:2:0 Format Memory Organization :
1720 *
1721 * "Planar YUV does not support MIP Tails as part of Standard Tiling.
1722 * The MIP Tail Start field in RENDER_SURFACE_STATE must be programmed
1723 * to 15."
1724 */
1725 if (isl_format_is_planar(info->format))
1726 return 15;
1727
1728 /* TODO: figure out why having YUV formats in the miptail on Gfx12 does not
1729 * work.
1730 */
1731 if (ISL_GFX_VER(dev) == 12 && isl_format_is_yuv(info->format))
1732 return 15;
1733
1734 if (intel_needs_workaround(dev->info, 22015614752) &&
1735 (info->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
1736 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1737 /* There are issues with multiple engines accessing the same CCS
1738 * cacheline in parallel. If we're here, Tile64 is use, providing enough
1739 * spacing between each miplevel. We must disable miptails to maintain
1740 * the necessary alignment between miplevels.
1741 */
1742 assert(tile_info->tiling == ISL_TILING_64);
1743 return 15;
1744 }
1745
1746 if (info->dim == ISL_SURF_DIM_3D &&
1747 isl_tiling_is_std_y(tile_info->tiling) &&
1748 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1749 /* From the workarounds section in the SKL PRM:
1750 *
1751 * "RCC cacheline is composed of X-adjacent 64B fragments instead of
1752 * memory adjacent. This causes a single 128B cacheline to straddle
1753 * multiple LODs inside the TYF MIPtail for 3D surfaces (beyond a
1754 * certain slot number), leading to corruption when CCS is enabled
1755 * for these LODs and RT is later bound as texture. WA: If
1756 * RENDER_SURFACE_STATE.Surface Type = 3D and
1757 * RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE and
1758 * RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS, Set the
1759 * value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip that
1760 * larger than those present in the surface (i.e. 15)"
1761 *
1762 * Referred to as Wa_1207137018 on ICL+. Disable miptails as suggested.
1763 */
1764 return 15;
1765 }
1766
1767 assert(isl_tiling_is_64(tile_info->tiling) ||
1768 isl_tiling_is_std_y(tile_info->tiling));
1769 assert(info->samples == 1);
1770
1771 uint32_t max_miptail_levels = tile_info->max_miptail_levels;
1772
1773 if (max_miptail_levels > 11 &&
1774 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1775 /* SKL PRMs, Volume 5: Memory Views, Tiling and Mip Tails for 2D
1776 * Surfaces:
1777 *
1778 * "Lossless compression must not be used on surfaces which have MIP
1779 * Tail which contains MIPs for Slots greater than 11."
1780 *
1781 * Reduce the slot consumption to keep compression enabled.
1782 */
1783 max_miptail_levels = 11;
1784 }
1785
1786 /* Start with the minimum number of levels that will fit in the tile */
1787 uint32_t min_miptail_start =
1788 info->levels > max_miptail_levels ? info->levels - max_miptail_levels : 0;
1789
1790 /* Account for the specified minimum */
1791 min_miptail_start = MAX(min_miptail_start, info->min_miptail_start_level);
1792
1793 struct isl_extent3d level0_extent_el = {
1794 .w = isl_align_div_npot(info->width, fmtl->bw),
1795 .h = isl_align_div_npot(info->height, fmtl->bh),
1796 .d = isl_align_div_npot(info->depth, fmtl->bd),
1797 };
1798
1799 /* The first miptail slot takes up the entire right side of the tile. So,
1800 * the extent is just the distance from the offset of the first level to
1801 * the corner of the tile.
1802 */
1803 uint32_t level0_x_offset_el, level0_y_offset_el, level0_z_offset_el;
1804 isl_get_miptail_level_offset_el(tile_info->tiling, info->dim,
1805 fmtl->bpb, 0, /* level */
1806 &level0_x_offset_el,
1807 &level0_y_offset_el,
1808 &level0_z_offset_el);
1809 struct isl_extent3d miptail_level0_extent_el = {
1810 .w = tile_info->logical_extent_el.w - level0_x_offset_el,
1811 .h = tile_info->logical_extent_el.h - level0_y_offset_el,
1812 .d = tile_info->logical_extent_el.d - level0_z_offset_el,
1813 };
1814
1815 /* Now find the first level that fits the maximum miptail size requirement.
1816 */
1817 for (uint32_t s = min_miptail_start; s < info->levels; s++) {
1818 if (isl_minify(level0_extent_el.w, s) <= miptail_level0_extent_el.w &&
1819 isl_minify(level0_extent_el.h, s) <= miptail_level0_extent_el.h &&
1820 isl_minify(level0_extent_el.d, s) <= miptail_level0_extent_el.d)
1821 return s;
1822 }
1823
1824 return info->levels;
1825 }
1826
1827 /**
1828 * Calculate the pitch between physical array slices, in units of rows of
1829 * surface elements.
1830 */
1831 static uint32_t
isl_calc_array_pitch_el_rows_gfx4_2d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,enum isl_array_pitch_span array_pitch_span,const struct isl_extent2d * phys_slice0_sa)1832 isl_calc_array_pitch_el_rows_gfx4_2d(
1833 const struct isl_device *dev,
1834 const struct isl_surf_init_info *restrict info,
1835 const struct isl_tile_info *tile_info,
1836 const struct isl_extent3d *image_align_sa,
1837 const struct isl_extent4d *phys_level0_sa,
1838 enum isl_array_pitch_span array_pitch_span,
1839 const struct isl_extent2d *phys_slice0_sa)
1840 {
1841 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1842 uint32_t pitch_sa_rows = 0;
1843
1844 switch (array_pitch_span) {
1845 case ISL_ARRAY_PITCH_SPAN_COMPACT:
1846 pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
1847 break;
1848 case ISL_ARRAY_PITCH_SPAN_FULL: {
1849 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
1850 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
1851 * Surfaces >> Surface Arrays.
1852 */
1853 uint32_t H0_sa = phys_level0_sa->h;
1854 uint32_t H1_sa = isl_minify(H0_sa, 1);
1855
1856 uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
1857 uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
1858
1859 uint32_t m;
1860 if (ISL_GFX_VER(dev) >= 7) {
1861 /* The QPitch equation changed slightly in Ivybridge. */
1862 m = 12;
1863 } else {
1864 m = 11;
1865 }
1866
1867 pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
1868
1869 if (ISL_GFX_VER(dev) == 6 && info->samples > 1 &&
1870 (info->height % 4 == 1)) {
1871 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1872 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
1873 *
1874 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
1875 * the value calculated in the equation above , for every
1876 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
1877 *
1878 * XXX(chadv): Is the errata natural corollary of the physical
1879 * layout of interleaved samples?
1880 */
1881 pitch_sa_rows += 4;
1882 }
1883
1884 pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
1885 } /* end case */
1886 break;
1887 }
1888
1889 assert(pitch_sa_rows % fmtl->bh == 0);
1890 uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
1891
1892 if (ISL_GFX_VER(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
1893 /*
1894 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
1895 *
1896 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
1897 * layout with these alignments in the RT space: Horizontal
1898 * Alignment = 128 and Vertical Alignment = 64."
1899 *
1900 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
1901 *
1902 * "For non-multisampled render target's CCS auxiliary surface,
1903 * QPitch must be computed with Horizontal Alignment = 128 and
1904 * Surface Vertical Alignment = 256. These alignments are only for
1905 * CCS buffer and not for associated render target."
1906 *
1907 * The first restriction is already handled by isl_choose_image_alignment_el
1908 * but the second restriction, which is an extension of the first, only
1909 * applies to qpitch and must be applied here.
1910 */
1911 assert(fmtl->bh == 4);
1912 pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
1913 }
1914
1915 if (ISL_GFX_VER(dev) >= 9 &&
1916 info->dim == ISL_SURF_DIM_3D &&
1917 tile_info->tiling != ISL_TILING_LINEAR) {
1918 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
1919 *
1920 * Tile Mode != Linear: This field must be set to an integer multiple
1921 * of the tile height
1922 */
1923 pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
1924 }
1925
1926 if (isl_surf_usage_is_depth(info->usage) &&
1927 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1928 /* From the TGL PRM, Vol 9, "Compressed Depth Buffers" (under the
1929 * "Texture performant" and "ZCS" columns):
1930 *
1931 * Update with clear at either 16x8 or 8x4 granularity, based on
1932 * fs_clr or otherwise.
1933 *
1934 * When fast-clearing, hardware behaves in unexpected ways if the clear
1935 * rectangle, aligned to 16x8, could cover neighboring LODs. Align the
1936 * array pitch to 8 in order to increase the number of aligned LODs.
1937 */
1938 pitch_el_rows = isl_align(pitch_el_rows, 8);
1939 }
1940
1941 return pitch_el_rows;
1942 }
1943
1944 /**
1945 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1946 * ISL_DIM_LAYOUT_GFX4_2D.
1947 */
1948 static void
isl_calc_phys_slice0_extent_sa_gfx4_2d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_msaa_layout msaa_layout,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t miptail_start_level,struct isl_extent2d * phys_slice0_sa)1949 isl_calc_phys_slice0_extent_sa_gfx4_2d(
1950 const struct isl_device *dev,
1951 const struct isl_surf_init_info *restrict info,
1952 const struct isl_tile_info *tile_info,
1953 enum isl_msaa_layout msaa_layout,
1954 const struct isl_extent3d *image_align_sa,
1955 const struct isl_extent4d *phys_level0_sa,
1956 uint32_t miptail_start_level,
1957 struct isl_extent2d *phys_slice0_sa)
1958 {
1959 ASSERTED const struct isl_format_layout *fmtl =
1960 isl_format_get_layout(info->format);
1961
1962 if (info->levels == 1 && miptail_start_level > 0) {
1963 /* Do not pad the surface to the image alignment.
1964 *
1965 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
1966 * cycles on the below mipmap layout caluclations. Reducing the
1967 * alignment here is safe because we later align the row pitch and array
1968 * pitch to the tile boundary. It is safe even for
1969 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
1970 * to accommodate the interleaved samples.
1971 *
1972 * For linear surfaces, reducing the alignment here permits us to later
1973 * choose an arbitrary, non-aligned row pitch. If the surface backs
1974 * a VkBuffer, then an arbitrary pitch may be needed to accommodate
1975 * VkBufferImageCopy::bufferRowLength.
1976 */
1977 *phys_slice0_sa = (struct isl_extent2d) {
1978 .w = phys_level0_sa->w,
1979 .h = phys_level0_sa->h,
1980 };
1981 return;
1982 }
1983
1984 uint32_t slice_top_w = 0;
1985 uint32_t slice_bottom_w = 0;
1986 uint32_t slice_left_h = 0;
1987 uint32_t slice_right_h = 0;
1988
1989 uint32_t W0 = phys_level0_sa->w;
1990 uint32_t H0 = phys_level0_sa->h;
1991
1992 for (uint32_t l = 0; l < info->levels; ++l) {
1993 uint32_t W = isl_minify(W0, l);
1994 uint32_t H = isl_minify(H0, l);
1995
1996 uint32_t w = isl_align_npot(W, image_align_sa->w);
1997 uint32_t h = isl_align_npot(H, image_align_sa->h);
1998
1999 if (l == 0) {
2000 slice_top_w = w;
2001 slice_left_h = h;
2002 slice_right_h = h;
2003 } else if (l == 1) {
2004 slice_bottom_w = w;
2005 slice_left_h += h;
2006 } else if (l == 2) {
2007 slice_bottom_w += w;
2008 slice_right_h += h;
2009 } else {
2010 slice_right_h += h;
2011 }
2012
2013 if (l >= miptail_start_level) {
2014 assert(l == miptail_start_level);
2015 assert(isl_tiling_is_64(tile_info->tiling) ||
2016 isl_tiling_is_std_y(tile_info->tiling));
2017 assert(w == tile_info->logical_extent_el.w * fmtl->bw);
2018 assert(h == tile_info->logical_extent_el.h * fmtl->bh);
2019 /* If we've gone into the miptail, we're done. All higher miplevels
2020 * will be tucked into the same tile as this one.
2021 */
2022 break;
2023 }
2024 }
2025
2026 *phys_slice0_sa = (struct isl_extent2d) {
2027 .w = MAX(slice_top_w, slice_bottom_w),
2028 .h = MAX(slice_left_h, slice_right_h),
2029 };
2030 }
2031
2032 static void
isl_calc_phys_total_extent_el_gfx4_2d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_msaa_layout msaa_layout,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,enum isl_array_pitch_span array_pitch_span,uint32_t miptail_start_level,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2033 isl_calc_phys_total_extent_el_gfx4_2d(
2034 const struct isl_device *dev,
2035 const struct isl_surf_init_info *restrict info,
2036 const struct isl_tile_info *tile_info,
2037 enum isl_msaa_layout msaa_layout,
2038 const struct isl_extent3d *image_align_sa,
2039 const struct isl_extent4d *phys_level0_sa,
2040 enum isl_array_pitch_span array_pitch_span,
2041 uint32_t miptail_start_level,
2042 uint32_t *array_pitch_el_rows,
2043 struct isl_extent4d *phys_total_el)
2044 {
2045 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2046
2047 struct isl_extent2d phys_slice0_sa;
2048 isl_calc_phys_slice0_extent_sa_gfx4_2d(dev, info, tile_info, msaa_layout,
2049 image_align_sa, phys_level0_sa,
2050 miptail_start_level,
2051 &phys_slice0_sa);
2052 *array_pitch_el_rows =
2053 isl_calc_array_pitch_el_rows_gfx4_2d(dev, info, tile_info,
2054 image_align_sa, phys_level0_sa,
2055 array_pitch_span,
2056 &phys_slice0_sa);
2057
2058 if (isl_tiling_is_64(tile_info->tiling) ||
2059 isl_tiling_is_std_y(tile_info->tiling)) {
2060 *phys_total_el = (struct isl_extent4d) {
2061 .w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw),
2062 .h = isl_align_div_npot(phys_slice0_sa.h, fmtl->bh),
2063 .d = isl_align_div_npot(phys_level0_sa->d, fmtl->bd),
2064 .a = phys_level0_sa->array_len,
2065 };
2066 } else {
2067 uint32_t array_len = MAX(phys_level0_sa->d, phys_level0_sa->a);
2068 *phys_total_el = (struct isl_extent4d) {
2069 .w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw),
2070 .h = *array_pitch_el_rows * (array_len - 1) +
2071 isl_align_div_npot(phys_slice0_sa.h, fmtl->bh),
2072 .d = 1,
2073 .a = 1,
2074 };
2075 }
2076 }
2077
2078 /**
2079 * A variant of isl_calc_phys_slice0_extent_sa() specific to
2080 * ISL_DIM_LAYOUT_GFX4_3D.
2081 */
2082 static void
isl_calc_phys_total_extent_el_gfx4_3d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2083 isl_calc_phys_total_extent_el_gfx4_3d(
2084 const struct isl_device *dev,
2085 const struct isl_surf_init_info *restrict info,
2086 const struct isl_extent3d *image_align_sa,
2087 const struct isl_extent4d *phys_level0_sa,
2088 uint32_t *array_pitch_el_rows,
2089 struct isl_extent4d *phys_total_el)
2090 {
2091 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2092
2093 assert(info->samples == 1);
2094
2095 if (info->dim != ISL_SURF_DIM_3D) {
2096 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
2097 *
2098 * The cube face textures are stored in the same way as 3D surfaces
2099 * are stored (see section 6.17.5 for details). For cube surfaces,
2100 * however, the depth is equal to the number of faces (always 6) and
2101 * is not reduced for each MIP.
2102 */
2103 assert(ISL_GFX_VER(dev) == 4);
2104 assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);
2105 assert(phys_level0_sa->array_len == 6);
2106 } else {
2107 assert(phys_level0_sa->array_len == 1);
2108 }
2109
2110 uint32_t total_w = 0;
2111 uint32_t total_h = 0;
2112
2113 uint32_t W0 = phys_level0_sa->w;
2114 uint32_t H0 = phys_level0_sa->h;
2115 uint32_t D0 = phys_level0_sa->d;
2116 uint32_t A0 = phys_level0_sa->a;
2117
2118 for (uint32_t l = 0; l < info->levels; ++l) {
2119 uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w);
2120 uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h);
2121 uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0;
2122
2123 uint32_t max_layers_horiz = MIN(level_d, 1u << l);
2124 uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
2125
2126 total_w = MAX(total_w, level_w * max_layers_horiz);
2127 total_h += level_h * max_layers_vert;
2128 }
2129
2130 /* GFX4_3D layouts don't really have an array pitch since each LOD has a
2131 * different number of horizontal and vertical layers. We have to set it
2132 * to something, so at least make it true for LOD0.
2133 */
2134 *array_pitch_el_rows =
2135 isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw;
2136 *phys_total_el = (struct isl_extent4d) {
2137 .w = isl_assert_div(total_w, fmtl->bw),
2138 .h = isl_assert_div(total_h, fmtl->bh),
2139 .d = 1,
2140 .a = 1,
2141 };
2142 }
2143
2144 /**
2145 * A variant of isl_calc_phys_slice0_extent_sa() specific to
2146 * ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ.
2147 */
2148 static void
isl_calc_phys_total_extent_el_gfx6_stencil_hiz(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2149 isl_calc_phys_total_extent_el_gfx6_stencil_hiz(
2150 const struct isl_device *dev,
2151 const struct isl_surf_init_info *restrict info,
2152 const struct isl_tile_info *tile_info,
2153 const struct isl_extent3d *image_align_sa,
2154 const struct isl_extent4d *phys_level0_sa,
2155 uint32_t *array_pitch_el_rows,
2156 struct isl_extent4d *phys_total_el)
2157 {
2158 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2159
2160 const struct isl_extent2d tile_extent_sa = {
2161 .w = tile_info->logical_extent_el.w * fmtl->bw,
2162 .h = tile_info->logical_extent_el.h * fmtl->bh,
2163 };
2164 /* Tile size is a multiple of image alignment */
2165 assert(tile_extent_sa.w % image_align_sa->w == 0);
2166 assert(tile_extent_sa.h % image_align_sa->h == 0);
2167
2168 const uint32_t W0 = phys_level0_sa->w;
2169 const uint32_t H0 = phys_level0_sa->h;
2170
2171 /* Each image has the same height as LOD0 because the hardware thinks
2172 * everything is LOD0
2173 */
2174 const uint32_t H = isl_align(H0, image_align_sa->h) * phys_level0_sa->a;
2175
2176 uint32_t total_top_w = 0;
2177 uint32_t total_bottom_w = 0;
2178 uint32_t total_h = 0;
2179
2180 for (uint32_t l = 0; l < info->levels; ++l) {
2181 const uint32_t W = isl_minify(W0, l);
2182
2183 const uint32_t w = isl_align(W, tile_extent_sa.w);
2184 const uint32_t h = isl_align(H, tile_extent_sa.h);
2185
2186 if (l == 0) {
2187 total_top_w = w;
2188 total_h = h;
2189 } else if (l == 1) {
2190 total_bottom_w = w;
2191 total_h += h;
2192 } else {
2193 total_bottom_w += w;
2194 }
2195 }
2196
2197 *array_pitch_el_rows =
2198 isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh);
2199 *phys_total_el = (struct isl_extent4d) {
2200 .w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw),
2201 .h = isl_assert_div(total_h, fmtl->bh),
2202 .d = 1,
2203 .a = 1,
2204 };
2205 }
2206
2207 /**
2208 * A variant of isl_calc_phys_slice0_extent_sa() specific to
2209 * ISL_DIM_LAYOUT_GFX9_1D.
2210 */
2211 static void
isl_calc_phys_total_extent_el_gfx9_1d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2212 isl_calc_phys_total_extent_el_gfx9_1d(
2213 const struct isl_device *dev,
2214 const struct isl_surf_init_info *restrict info,
2215 const struct isl_extent3d *image_align_sa,
2216 const struct isl_extent4d *phys_level0_sa,
2217 uint32_t *array_pitch_el_rows,
2218 struct isl_extent4d *phys_total_el)
2219 {
2220 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2221
2222 assert(phys_level0_sa->height == 1);
2223 assert(phys_level0_sa->depth == 1);
2224 assert(info->samples == 1);
2225 assert(image_align_sa->w >= fmtl->bw);
2226
2227 uint32_t slice_w = 0;
2228 const uint32_t W0 = phys_level0_sa->w;
2229
2230 for (uint32_t l = 0; l < info->levels; ++l) {
2231 uint32_t W = isl_minify(W0, l);
2232 uint32_t w = isl_align_npot(W, image_align_sa->w);
2233
2234 slice_w += w;
2235 }
2236
2237 *array_pitch_el_rows = 1;
2238 *phys_total_el = (struct isl_extent4d) {
2239 .w = isl_assert_div(slice_w, fmtl->bw),
2240 .h = phys_level0_sa->array_len,
2241 .d = 1,
2242 .a = 1,
2243 };
2244 }
2245
2246 /**
2247 * Calculate the two-dimensional total physical extent of the surface, in
2248 * units of surface elements.
2249 */
2250 static void
isl_calc_phys_total_extent_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,enum isl_array_pitch_span array_pitch_span,uint32_t miptail_start_level,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2251 isl_calc_phys_total_extent_el(const struct isl_device *dev,
2252 const struct isl_surf_init_info *restrict info,
2253 const struct isl_tile_info *tile_info,
2254 enum isl_dim_layout dim_layout,
2255 enum isl_msaa_layout msaa_layout,
2256 const struct isl_extent3d *image_align_sa,
2257 const struct isl_extent4d *phys_level0_sa,
2258 enum isl_array_pitch_span array_pitch_span,
2259 uint32_t miptail_start_level,
2260 uint32_t *array_pitch_el_rows,
2261 struct isl_extent4d *phys_total_el)
2262 {
2263 switch (dim_layout) {
2264 case ISL_DIM_LAYOUT_GFX9_1D:
2265 assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
2266 isl_calc_phys_total_extent_el_gfx9_1d(dev, info,
2267 image_align_sa, phys_level0_sa,
2268 array_pitch_el_rows,
2269 phys_total_el);
2270 return;
2271 case ISL_DIM_LAYOUT_GFX4_2D:
2272 isl_calc_phys_total_extent_el_gfx4_2d(dev, info, tile_info, msaa_layout,
2273 image_align_sa, phys_level0_sa,
2274 array_pitch_span,
2275 miptail_start_level,
2276 array_pitch_el_rows,
2277 phys_total_el);
2278 return;
2279 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
2280 assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
2281 isl_calc_phys_total_extent_el_gfx6_stencil_hiz(dev, info, tile_info,
2282 image_align_sa,
2283 phys_level0_sa,
2284 array_pitch_el_rows,
2285 phys_total_el);
2286 return;
2287 case ISL_DIM_LAYOUT_GFX4_3D:
2288 assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
2289 isl_calc_phys_total_extent_el_gfx4_3d(dev, info,
2290 image_align_sa, phys_level0_sa,
2291 array_pitch_el_rows,
2292 phys_total_el);
2293 return;
2294 }
2295
2296 unreachable("invalid value for dim_layout");
2297 }
2298
2299 static uint32_t
isl_calc_row_pitch_alignment(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info)2300 isl_calc_row_pitch_alignment(const struct isl_device *dev,
2301 const struct isl_surf_init_info *surf_info,
2302 const struct isl_tile_info *tile_info)
2303 {
2304 if (tile_info->tiling != ISL_TILING_LINEAR) {
2305
2306 /* On gfx12, aligning to 512B may be wanted or needed for CCS_E. */
2307 if (ISL_GFX_VER(dev) == 12 && surf_info->samples == 1 &&
2308 !isl_surf_usage_is_depth_or_stencil(surf_info->usage) &&
2309 _isl_surf_info_supports_ccs(dev, surf_info->format,
2310 surf_info->usage) &&
2311 tile_info->tiling != ISL_TILING_X &&
2312 surf_info->row_pitch_B == 0) {
2313
2314 /* From Bspec 49252, Render Decompression:
2315 *
2316 * "Compressed displayable surfaces must be 16KB aligned and have
2317 * pitches padded to multiple of 4 tiles."
2318 *
2319 * Only consider padding the pitch when the caller has specified no
2320 * pitch. isl_surf_supports_ccs() will confirm that the main surface
2321 * pitch matches CCS expectations.
2322 */
2323 if (isl_surf_usage_is_display(surf_info->usage)) {
2324 assert(tile_info->phys_extent_B.width == 128);
2325 return 512;
2326 }
2327
2328 /* On gfx12.0, CCS fast clears don't seem to cover the correct
2329 * portion of the aux buffer when the pitch is not 512B-aligned. Pad
2330 * the pitch unless Wa_18020603990 applies (slow clear surfaces up
2331 * to 256x256, 32bpp). isl_surf_supports_ccs() won't confirm this
2332 * alignment, so drivers must fall back to slow clears as needed.
2333 */
2334 if (ISL_GFX_VERX10(dev) == 120) {
2335 assert(intel_needs_workaround(dev->info, 18020603990));
2336 if (tile_info->format_bpb > 32 ||
2337 surf_info->width > 256 ||
2338 surf_info->height > 256) {
2339 assert(tile_info->phys_extent_B.width == 128);
2340 return 512;
2341 }
2342 }
2343 }
2344
2345 return tile_info->phys_extent_B.width;
2346 }
2347
2348 /* We only support tiled fragment shading rate buffers. */
2349 assert((surf_info->usage & ISL_SURF_USAGE_CPB_BIT) == 0);
2350
2351 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
2352 * RENDER_SURFACE_STATE Surface Pitch (p349):
2353 *
2354 * - For linear render target surfaces and surfaces accessed with the
2355 * typed data port messages, the pitch must be a multiple of the
2356 * element size for non-YUV surface formats. Pitch must be
2357 * a multiple of 2 * element size for YUV surface formats.
2358 *
2359 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
2360 * ignore because isl doesn't do buffers.]
2361 *
2362 * - For other linear surfaces, the pitch can be any multiple of
2363 * bytes.
2364 */
2365 const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
2366 const uint32_t bs = fmtl->bpb / 8;
2367 uint32_t alignment;
2368
2369 if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
2370 if (isl_format_is_yuv(surf_info->format)) {
2371 alignment = 2 * bs;
2372 } else {
2373 alignment = bs;
2374 }
2375 } else {
2376 alignment = 1;
2377 }
2378
2379 /* From the Broadwell PRM >> Volume 2c: Command Reference: Registers >>
2380 * PRI_STRIDE Stride (p1254):
2381 *
2382 * "When using linear memory, this must be at least 64 byte aligned."
2383 *
2384 * However, when displaying on NVIDIA and recent AMD GPUs via PRIME,
2385 * we need a larger pitch of 256 bytes.
2386 *
2387 * If the ISL caller didn't specify a row_pitch_B, then we should assume
2388 * the NVIDIA/AMD requirements. Otherwise, if we have a specified
2389 * row_pitch_B, this is probably because the caller is trying to import a
2390 * buffer. In that case we limit the minimum row pitch to the Intel HW
2391 * requirement.
2392 */
2393 if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
2394 if (surf_info->row_pitch_B == 0)
2395 alignment = isl_align(alignment, 256);
2396 else
2397 alignment = isl_align(alignment, 64);
2398 }
2399
2400 return alignment;
2401 }
2402
2403 static uint32_t
isl_calc_linear_min_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * info,const struct isl_extent4d * phys_total_el,uint32_t alignment_B)2404 isl_calc_linear_min_row_pitch(const struct isl_device *dev,
2405 const struct isl_surf_init_info *info,
2406 const struct isl_extent4d *phys_total_el,
2407 uint32_t alignment_B)
2408 {
2409 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2410 const uint32_t bs = fmtl->bpb / 8;
2411
2412 return isl_align_npot(bs * phys_total_el->w, alignment_B);
2413 }
2414
2415 static uint32_t
isl_calc_tiled_min_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info,const struct isl_extent4d * phys_total_el,uint32_t alignment_B)2416 isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
2417 const struct isl_surf_init_info *surf_info,
2418 const struct isl_tile_info *tile_info,
2419 const struct isl_extent4d *phys_total_el,
2420 uint32_t alignment_B)
2421 {
2422 const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
2423
2424 assert(fmtl->bpb % tile_info->format_bpb == 0);
2425
2426 const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb;
2427 const uint32_t total_w_tl =
2428 isl_align_div(phys_total_el->w * tile_el_scale,
2429 tile_info->logical_extent_el.width);
2430
2431 /* In some cases the alignment of the pitch might be > to the tile size
2432 * (for example Gfx12 CCS requires 512B alignment while the tile's width
2433 * can be 128B), so align the row pitch to the alignment.
2434 */
2435 assert(alignment_B >= tile_info->phys_extent_B.width);
2436 return isl_align(total_w_tl * tile_info->phys_extent_B.width, alignment_B);
2437 }
2438
2439 static uint32_t
isl_calc_min_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info,const struct isl_extent4d * phys_total_el,uint32_t alignment_B)2440 isl_calc_min_row_pitch(const struct isl_device *dev,
2441 const struct isl_surf_init_info *surf_info,
2442 const struct isl_tile_info *tile_info,
2443 const struct isl_extent4d *phys_total_el,
2444 uint32_t alignment_B)
2445 {
2446 if (tile_info->tiling == ISL_TILING_LINEAR) {
2447 return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el,
2448 alignment_B);
2449 } else {
2450 return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info,
2451 phys_total_el, alignment_B);
2452 }
2453 }
2454
2455 /**
2456 * Is ``pitch`` in the valid range for a hardware bitfield, if the bitfield's
2457 * size is ``bits`` bits?
2458 *
2459 * Hardware pitch fields are offset by 1. For example, if the size of
2460 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
2461 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
2462 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
2463 */
2464 static bool
pitch_in_range(uint32_t n,uint32_t bits)2465 pitch_in_range(uint32_t n, uint32_t bits)
2466 {
2467 assert(n != 0);
2468 return likely(bits != 0 && 1 <= n && n <= (1 << bits));
2469 }
2470
2471 void PRINTFLIKE(4, 5)
_isl_notify_failure(const struct isl_surf_init_info * surf_info,const char * file,int line,const char * fmt,...)2472 _isl_notify_failure(const struct isl_surf_init_info *surf_info,
2473 const char *file, int line, const char *fmt, ...)
2474 {
2475 if (!INTEL_DEBUG(DEBUG_ISL))
2476 return;
2477
2478 char msg[512];
2479 va_list ap;
2480 va_start(ap, fmt);
2481 int ret = vsnprintf(msg, sizeof(msg), fmt, ap);
2482 assert(ret < sizeof(msg));
2483 va_end(ap);
2484
2485 #define PRINT_USAGE(bit, str) \
2486 (surf_info->usage & ISL_SURF_USAGE_##bit##_BIT) ? ("+"str) : ""
2487 #define PRINT_TILING(bit, str) \
2488 (surf_info->tiling_flags & ISL_TILING_##bit##_BIT) ? ("+"str) : ""
2489
2490 snprintf(msg + ret, sizeof(msg) - ret,
2491 " extent=%ux%ux%u dim=%s msaa=%ux levels=%u rpitch=%u fmt=%s "
2492 "usages=%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s "
2493 "tiling_flags=%s%s%s%s%s%s%s%s%s%s%s%s",
2494 surf_info->width, surf_info->height,
2495 surf_info->dim == ISL_SURF_DIM_3D ?
2496 surf_info->depth : surf_info->array_len,
2497 surf_info->dim == ISL_SURF_DIM_1D ? "1d" :
2498 surf_info->dim == ISL_SURF_DIM_2D ? "2d" : "3d",
2499 surf_info->samples, surf_info->levels,
2500 surf_info->row_pitch_B,
2501 isl_format_get_name(surf_info->format) + strlen("ISL_FORMAT_"),
2502
2503 PRINT_USAGE(RENDER_TARGET, "rt"),
2504 PRINT_USAGE(DEPTH, "depth"),
2505 PRINT_USAGE(STENCIL, "stenc"),
2506 PRINT_USAGE(TEXTURE, "tex"),
2507 PRINT_USAGE(CUBE, "cube"),
2508 PRINT_USAGE(DISABLE_AUX, "noaux"),
2509 PRINT_USAGE(DISPLAY, "disp"),
2510 PRINT_USAGE(HIZ, "hiz"),
2511 PRINT_USAGE(MCS, "mcs"),
2512 PRINT_USAGE(CCS, "ccs"),
2513 PRINT_USAGE(VERTEX_BUFFER, "vb"),
2514 PRINT_USAGE(INDEX_BUFFER, "ib"),
2515 PRINT_USAGE(CONSTANT_BUFFER, "const"),
2516 PRINT_USAGE(STAGING, "stage"),
2517 PRINT_USAGE(SPARSE, "sparse"),
2518 PRINT_USAGE(NO_AUX_TT_ALIGNMENT, "no-aux-align"),
2519
2520 PRINT_TILING(LINEAR, "linear"),
2521 PRINT_TILING(W, "W"),
2522 PRINT_TILING(X, "X"),
2523 PRINT_TILING(Y0, "Y0"),
2524 PRINT_TILING(SKL_Yf, "skl-Yf"),
2525 PRINT_TILING(SKL_Ys, "skl-Ys"),
2526 PRINT_TILING(ICL_Yf, "icl-Yf"),
2527 PRINT_TILING(ICL_Ys, "icl-Ys"),
2528 PRINT_TILING(4, "4"),
2529 PRINT_TILING(64, "64"),
2530 PRINT_TILING(HIZ, "hiz"),
2531 PRINT_TILING(CCS, "ccs"));
2532
2533 #undef PRINT_USAGE
2534 #undef PRINT_TILING
2535
2536 mesa_logd("%s:%i: %s", file, line, msg);
2537 }
2538
2539 static bool
isl_calc_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info,enum isl_dim_layout dim_layout,const struct isl_extent4d * phys_total_el,uint32_t * out_row_pitch_B)2540 isl_calc_row_pitch(const struct isl_device *dev,
2541 const struct isl_surf_init_info *surf_info,
2542 const struct isl_tile_info *tile_info,
2543 enum isl_dim_layout dim_layout,
2544 const struct isl_extent4d *phys_total_el,
2545 uint32_t *out_row_pitch_B)
2546 {
2547 uint32_t alignment_B =
2548 isl_calc_row_pitch_alignment(dev, surf_info, tile_info);
2549
2550 const uint32_t min_row_pitch_B =
2551 isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
2552 alignment_B);
2553
2554 if (surf_info->row_pitch_B != 0) {
2555 if (surf_info->row_pitch_B < min_row_pitch_B) {
2556 return notify_failure(surf_info,
2557 "requested row pitch (%uB) less than minimum "
2558 "allowed (%uB)",
2559 surf_info->row_pitch_B, min_row_pitch_B);
2560 }
2561
2562 if (surf_info->row_pitch_B % alignment_B != 0) {
2563 return notify_failure(surf_info,
2564 "requested row pitch (%uB) doesn't satisfy the "
2565 "minimum alignment requirement (%uB)",
2566 surf_info->row_pitch_B, alignment_B);
2567 }
2568 }
2569
2570 const uint32_t row_pitch_B =
2571 surf_info->row_pitch_B != 0 ? surf_info->row_pitch_B : min_row_pitch_B;
2572
2573 const uint32_t row_pitch_tl = row_pitch_B / tile_info->phys_extent_B.width;
2574
2575 if (row_pitch_B == 0)
2576 return notify_failure(surf_info, "calculated row pitch is zero");
2577
2578 if (dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
2579 /* SurfacePitch is ignored for this layout. */
2580 goto done;
2581 }
2582
2583 if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
2584 ISL_SURF_USAGE_TEXTURE_BIT |
2585 ISL_SURF_USAGE_STORAGE_BIT)) &&
2586 !pitch_in_range(row_pitch_B, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info))) {
2587 return notify_failure(surf_info,
2588 "row pitch (%uB) not in range of "
2589 "RENDER_SURFACE_STATE::SurfacePitch",
2590 row_pitch_B);
2591 }
2592
2593 if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT |
2594 ISL_SURF_USAGE_MCS_BIT)) &&
2595 !pitch_in_range(row_pitch_tl, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info))) {
2596 return notify_failure(surf_info,
2597 "row_pitch_tl=%u not in range of "
2598 "RENDER_SURFACE_STATE::AuxiliarySurfacePitch",
2599 row_pitch_tl);
2600 }
2601
2602 if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2603 !pitch_in_range(row_pitch_B, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) {
2604 return notify_failure(surf_info,
2605 "row pitch (%uB) not in range of "
2606 "3DSTATE_DEPTH_BUFFER::SurfacePitch",
2607 row_pitch_B);
2608 }
2609
2610 if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) &&
2611 !pitch_in_range(row_pitch_B, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) {
2612 return notify_failure(surf_info,
2613 "row pitch (%uB) not in range of "
2614 "3DSTATE_HIER_DEPTH_BUFFER::SurfacePitch",
2615 row_pitch_B);
2616 }
2617
2618 const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
2619 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
2620 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
2621
2622 if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
2623 !pitch_in_range(row_pitch_B, stencil_pitch_bits)) {
2624 return notify_failure(surf_info,
2625 "row pitch (%uB) not in range of "
2626 "3DSTATE_STENCIL_BUFFER/3DSTATE_DEPTH_BUFFER::SurfacePitch",
2627 row_pitch_B);
2628 }
2629
2630 if ((surf_info->usage & ISL_SURF_USAGE_CPB_BIT) &&
2631 !pitch_in_range(row_pitch_B, _3DSTATE_CPSIZE_CONTROL_BUFFER_SurfacePitch_bits(dev->info)))
2632 return false;
2633
2634 done:
2635 *out_row_pitch_B = row_pitch_B;
2636 return true;
2637 }
2638
2639 static bool
isl_calc_size(const struct isl_device * dev,const struct isl_surf_init_info * info,const struct isl_tile_info * tile_info,const struct isl_extent4d * phys_total_el,uint32_t array_pitch_el_rows,uint32_t row_pitch_B,uint64_t * out_size_B)2640 isl_calc_size(const struct isl_device *dev,
2641 const struct isl_surf_init_info *info,
2642 const struct isl_tile_info *tile_info,
2643 const struct isl_extent4d *phys_total_el,
2644 uint32_t array_pitch_el_rows,
2645 uint32_t row_pitch_B,
2646 uint64_t *out_size_B)
2647 {
2648 uint64_t size_B;
2649 if (tile_info->tiling == ISL_TILING_LINEAR) {
2650 /* LINEAR tiling has no concept of intra-tile arrays */
2651 assert(phys_total_el->d == 1 && phys_total_el->a == 1);
2652
2653 size_B = (uint64_t) row_pitch_B * phys_total_el->h;
2654
2655 } else {
2656 /* Pitches must make sense with the tiling */
2657 assert(row_pitch_B % tile_info->phys_extent_B.width == 0);
2658
2659 uint32_t array_slices, array_pitch_tl_rows;
2660 if (phys_total_el->d > 1) {
2661 assert(phys_total_el->a == 1);
2662 array_pitch_tl_rows = isl_assert_div(array_pitch_el_rows,
2663 tile_info->logical_extent_el.h);
2664 array_slices = isl_align_div(phys_total_el->d,
2665 tile_info->logical_extent_el.d);
2666 } else if (phys_total_el->a > 1) {
2667 assert(phys_total_el->d == 1);
2668 array_pitch_tl_rows = isl_assert_div(array_pitch_el_rows,
2669 tile_info->logical_extent_el.h);
2670 array_slices = isl_align_div(phys_total_el->a,
2671 tile_info->logical_extent_el.a);
2672 } else {
2673 assert(phys_total_el->d == 1 && phys_total_el->a == 1);
2674 array_pitch_tl_rows = 0;
2675 array_slices = 1;
2676 }
2677
2678 const uint32_t total_h_tl =
2679 (array_slices - 1) * array_pitch_tl_rows +
2680 isl_align_div(phys_total_el->h, tile_info->logical_extent_el.height);
2681
2682 size_B = (uint64_t) total_h_tl * tile_info->phys_extent_B.height *
2683 row_pitch_B;
2684
2685 /* Bspec 57340 (r59562):
2686 *
2687 * When allocating memory, MCS buffer size is extended by 4KB over
2688 * its original calculated size. First 4KB page of the MCS is
2689 * reserved for internal HW usage.
2690 *
2691 * Allocate an extra 4KB page reserved for hardware at the beginning of
2692 * MCS buffer on Xe2. The start address of MCS is the head of the 4KB
2693 * page. Any manipulation on the content of MCS should start after 4KB
2694 * from the start address.
2695 */
2696 if (dev->info->ver >= 20 && info->usage & ISL_SURF_USAGE_MCS_BIT)
2697 size_B += 4096;
2698 }
2699
2700 /* If for some reason we can't support the appropriate tiling format and
2701 * end up falling to linear or some other format, make sure the image size
2702 * and alignment are aligned to the expected block size so we can at least
2703 * do opaque binds.
2704 */
2705 if (info->usage & ISL_SURF_USAGE_SPARSE_BIT)
2706 size_B = isl_align(size_B, 64 * 1024);
2707
2708 /* Pre-gfx9: from the Broadwell PRM Vol 5, Surface Layout:
2709 * "In addition to restrictions on maximum height, width, and depth,
2710 * surfaces are also restricted to a maximum size in bytes. This
2711 * maximum is 2 GB for all products and all surface types."
2712 *
2713 * gfx9-10: from the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
2714 * "In addition to restrictions on maximum height, width, and depth,
2715 * surfaces are also restricted to a maximum size of 2^38 bytes.
2716 * All pixels within the surface must be contained within 2^38 bytes
2717 * of the base address."
2718 *
2719 * gfx11+ platforms raised this limit to 2^44 bytes.
2720 */
2721 uint64_t max_surface_B = 1ull << (ISL_GFX_VER(dev) >= 11 ? 44 :
2722 ISL_GFX_VER(dev) >= 9 ? 38 : 31);
2723 if (size_B > max_surface_B) {
2724 return notify_failure(
2725 info,
2726 "calculated size (%"PRIu64"B) exceeds platform limit of %"PRIu64"B",
2727 size_B, max_surface_B);
2728 }
2729
2730 *out_size_B = size_B;
2731 return true;
2732 }
2733
2734 static uint32_t
isl_calc_base_alignment(const struct isl_device * dev,const struct isl_surf_init_info * info,const struct isl_tile_info * tile_info)2735 isl_calc_base_alignment(const struct isl_device *dev,
2736 const struct isl_surf_init_info *info,
2737 const struct isl_tile_info *tile_info)
2738 {
2739 uint32_t base_alignment_B;
2740 if (tile_info->tiling == ISL_TILING_LINEAR) {
2741 /* From the Broadwell PRM Vol 2d,
2742 * RENDER_SURFACE_STATE::SurfaceBaseAddress:
2743 *
2744 * "The Base Address for linear render target surfaces and surfaces
2745 * accessed with the typed surface read/write data port messages must
2746 * be element-size aligned, for non-YUV surface formats, or a
2747 * multiple of 2 element-sizes for YUV surface formats. Other linear
2748 * surfaces have no alignment requirements (byte alignment is
2749 * sufficient.)"
2750 */
2751 base_alignment_B = MAX(1, info->min_alignment_B);
2752 if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
2753 if (isl_format_is_yuv(info->format)) {
2754 base_alignment_B =
2755 MAX(base_alignment_B, tile_info->format_bpb / 4);
2756 } else {
2757 base_alignment_B =
2758 MAX(base_alignment_B, tile_info->format_bpb / 8);
2759 }
2760 }
2761 base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B);
2762
2763 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
2764 *
2765 * "For Linear memory, this field specifies the stride in chunks of
2766 * 64 bytes (1 cache line)."
2767 */
2768 if (isl_surf_usage_is_display(info->usage))
2769 base_alignment_B = MAX(base_alignment_B, 64);
2770 } else {
2771 const uint32_t tile_size_B = tile_info->phys_extent_B.width *
2772 tile_info->phys_extent_B.height;
2773 assert(isl_is_pow2(info->min_alignment_B) && isl_is_pow2(tile_size_B));
2774 base_alignment_B = MAX(info->min_alignment_B, tile_size_B);
2775
2776 if (_isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
2777 /* Wa_22015614752:
2778 *
2779 * Due to L3 cache being tagged with (engineID, vaID) and the CCS
2780 * block/cacheline being 256 bytes, 2 engines accessing a 64Kb range
2781 * with compression will generate 2 different CCS cacheline entries
2782 * in L3, this will lead to corruptions. To avoid this, we need to
2783 * ensure 2 images do not share a 256 bytes CCS cacheline. With a
2784 * ratio of compression of 1/256, this is 64Kb alignment (even for
2785 * Tile4...)
2786 *
2787 * ATS-M PRMS, Vol 2a: Command Reference: Instructions,
2788 * XY_CTRL_SURF_COPY_BLT, "Size of Control Surface Copy" field, the
2789 * CCS blocks are 256 bytes :
2790 *
2791 * "This field indicates size of the Control Surface or CCS copy.
2792 * It is expressed in terms of number of 256B block of CCS, where
2793 * each 256B block of CCS corresponds to 64KB of main surface."
2794 */
2795 if (intel_needs_workaround(dev->info, 22015614752) &&
2796 (info->usage & (ISL_SURF_USAGE_MULTI_ENGINE_SEQ_BIT |
2797 ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT))) {
2798 base_alignment_B = MAX(base_alignment_B,
2799 256 /* cacheline */ * 256 /* AUX ratio */);
2800 }
2801
2802 /* Platforms using an aux map require that images be
2803 * granularity-aligned if they're going to used with CCS. This is
2804 * because the Aux translation table maps main surface addresses to
2805 * aux addresses at a granularity in the main surface. Because we
2806 * don't know for sure in ISL if a surface will use CCS, we have to
2807 * guess based on the DISABLE_AUX usage bit. The one thing we do know
2808 * is that we haven't enable CCS on linear images yet so we can avoid
2809 * the extra alignment there.
2810 */
2811 if (dev->info->has_aux_map &&
2812 !(info->usage & ISL_SURF_USAGE_NO_AUX_TT_ALIGNMENT_BIT)) {
2813 base_alignment_B = MAX(base_alignment_B, dev->info->verx10 >= 125 ?
2814 1024 * 1024 : 64 * 1024);
2815 }
2816 }
2817 }
2818
2819 /* If for some reason we can't support the appropriate tiling format and
2820 * end up falling to linear or some other format, make sure the image size
2821 * and alignment are aligned to the expected block size so we can at least
2822 * do opaque binds.
2823 */
2824 if (info->usage & ISL_SURF_USAGE_SPARSE_BIT)
2825 base_alignment_B = MAX(base_alignment_B, 64 * 1024);
2826
2827 return base_alignment_B;
2828 }
2829
2830 bool
isl_surf_init_s(const struct isl_device * dev,struct isl_surf * surf,const struct isl_surf_init_info * restrict info)2831 isl_surf_init_s(const struct isl_device *dev,
2832 struct isl_surf *surf,
2833 const struct isl_surf_init_info *restrict info)
2834 {
2835 /* Some sanity checks */
2836 assert(!(info->usage & ISL_SURF_USAGE_CPB_BIT) ||
2837 dev->info->has_coarse_pixel_primitive_and_cb);
2838
2839 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2840
2841 const struct isl_extent4d logical_level0_px = {
2842 .w = info->width,
2843 .h = info->height,
2844 .d = info->depth,
2845 .a = info->array_len,
2846 };
2847
2848 enum isl_tiling tiling;
2849 if (!isl_surf_choose_tiling(dev, info, &tiling))
2850 return false;
2851
2852 const enum isl_dim_layout dim_layout =
2853 isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
2854
2855 enum isl_msaa_layout msaa_layout;
2856 if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))
2857 return false;
2858
2859 struct isl_tile_info tile_info;
2860 isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb,
2861 info->samples, &tile_info);
2862
2863 struct isl_extent3d image_align_el;
2864 isl_choose_image_alignment_el(dev, info, &tile_info, dim_layout,
2865 msaa_layout, &image_align_el);
2866
2867 struct isl_extent3d image_align_sa =
2868 isl_extent3d_el_to_sa(info->format, image_align_el);
2869
2870 struct isl_extent4d phys_level0_sa;
2871 isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout,
2872 &phys_level0_sa);
2873
2874 enum isl_array_pitch_span array_pitch_span =
2875 isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
2876
2877 uint32_t miptail_start_level =
2878 isl_choose_miptail_start_level(dev, info, &tile_info);
2879
2880 uint32_t array_pitch_el_rows;
2881 struct isl_extent4d phys_total_el;
2882 isl_calc_phys_total_extent_el(dev, info, &tile_info,
2883 dim_layout, msaa_layout,
2884 &image_align_sa, &phys_level0_sa,
2885 array_pitch_span, miptail_start_level,
2886 &array_pitch_el_rows,
2887 &phys_total_el);
2888
2889 uint32_t row_pitch_B;
2890 if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout,
2891 &phys_total_el, &row_pitch_B))
2892 return false;
2893
2894 uint64_t size_B;
2895 if (!isl_calc_size(dev, info, &tile_info, &phys_total_el,
2896 array_pitch_el_rows, row_pitch_B, &size_B))
2897 return false;
2898
2899 const uint32_t base_alignment_B =
2900 isl_calc_base_alignment(dev, info, &tile_info);
2901
2902 *surf = (struct isl_surf) {
2903 .dim = info->dim,
2904 .dim_layout = dim_layout,
2905 .msaa_layout = msaa_layout,
2906 .tiling = tiling,
2907 .format = info->format,
2908
2909 .levels = info->levels,
2910 .samples = info->samples,
2911
2912 .image_alignment_el = image_align_el,
2913 .logical_level0_px = logical_level0_px,
2914 .phys_level0_sa = phys_level0_sa,
2915
2916 .size_B = size_B,
2917 .alignment_B = base_alignment_B,
2918 .row_pitch_B = row_pitch_B,
2919 .array_pitch_el_rows = array_pitch_el_rows,
2920 .array_pitch_span = array_pitch_span,
2921 .miptail_start_level = miptail_start_level,
2922
2923 .usage = info->usage,
2924 };
2925
2926 return true;
2927 }
2928
2929 void
isl_surf_get_tile_info(const struct isl_surf * surf,struct isl_tile_info * tile_info)2930 isl_surf_get_tile_info(const struct isl_surf *surf,
2931 struct isl_tile_info *tile_info)
2932 {
2933 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2934 isl_tiling_get_info(surf->tiling, surf->dim, surf->msaa_layout, fmtl->bpb,
2935 surf->samples, tile_info);
2936 }
2937
2938 bool
isl_surf_get_hiz_surf(const struct isl_device * dev,const struct isl_surf * surf,struct isl_surf * hiz_surf)2939 isl_surf_get_hiz_surf(const struct isl_device *dev,
2940 const struct isl_surf *surf,
2941 struct isl_surf *hiz_surf)
2942 {
2943 if (INTEL_DEBUG(DEBUG_NO_HIZ))
2944 return false;
2945
2946 /* HiZ support does not exist prior to Gfx5 */
2947 if (ISL_GFX_VER(dev) < 5)
2948 return false;
2949
2950 if (!isl_surf_usage_is_depth(surf->usage))
2951 return false;
2952
2953 /* From the Sandy Bridge PRM, Vol 2 Part 1,
2954 * 3DSTATE_DEPTH_BUFFER::Hierarchical Depth Buffer Enable,
2955 *
2956 * If this field is enabled, the Surface Format of the depth buffer
2957 * cannot be D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT. Use of stencil
2958 * requires the separate stencil buffer.
2959 *
2960 * On SNB+, HiZ can't be used with combined depth-stencil buffers.
2961 */
2962 if (isl_surf_usage_is_stencil(surf->usage))
2963 return false;
2964
2965 /* Multisampled depth is always interleaved */
2966 assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE ||
2967 surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
2968
2969 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
2970 *
2971 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
2972 * Target View Extent, and Depth Coordinate Offset X/Y of the
2973 * hierarchical depth buffer are inherited from the depth buffer. The
2974 * height and width of the hierarchical depth buffer that must be
2975 * allocated are computed by the following formulas, where HZ is the
2976 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
2977 * Z_Width, and Z_Depth values given in these formulas are those present
2978 * in 3DSTATE_DEPTH_BUFFER incremented by one.
2979 *
2980 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
2981 * being applied to the table below if Number of Multisamples is set to
2982 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
2983 * Z_Width must be multiplied by 4 before being applied to the table
2984 * below if Number of Multisamples is set to NUMSAMPLES_8."
2985 *
2986 * In the Sky Lake PRM, the second paragraph is gone. This means that,
2987 * from Sandy Bridge through Broadwell, HiZ compresses samples in the
2988 * primary depth surface. On Sky Lake and onward, HiZ compresses pixels.
2989 *
2990 * There are a number of different ways that this discrepancy could be
2991 * handled. The way we have chosen is to simply make MSAA HiZ have the
2992 * same number of samples as the parent surface pre-Sky Lake and always be
2993 * single-sampled on Sky Lake and above. Since the block sizes of
2994 * compressed formats are given in samples, this neatly handles everything
2995 * without the need for additional HiZ formats with different block sizes
2996 * on SKL+.
2997 */
2998 const unsigned samples = ISL_GFX_VER(dev) >= 9 ? 1 : surf->samples;
2999
3000 const enum isl_format format =
3001 ISL_GFX_VERX10(dev) >= 125 ? ISL_FORMAT_GFX125_HIZ : ISL_FORMAT_HIZ;
3002
3003 return isl_surf_init(dev, hiz_surf,
3004 .dim = surf->dim,
3005 .format = format,
3006 .width = surf->logical_level0_px.width,
3007 .height = surf->logical_level0_px.height,
3008 .depth = surf->logical_level0_px.depth,
3009 .levels = surf->levels,
3010 .array_len = surf->logical_level0_px.array_len,
3011 .samples = samples,
3012 .usage = ISL_SURF_USAGE_HIZ_BIT,
3013 .tiling_flags = ISL_TILING_HIZ_BIT);
3014 }
3015
3016 bool
isl_surf_get_mcs_surf(const struct isl_device * dev,const struct isl_surf * surf,struct isl_surf * mcs_surf)3017 isl_surf_get_mcs_surf(const struct isl_device *dev,
3018 const struct isl_surf *surf,
3019 struct isl_surf *mcs_surf)
3020 {
3021 /* It must be multisampled with an array layout */
3022 if (surf->msaa_layout != ISL_MSAA_LAYOUT_ARRAY)
3023 return false;
3024
3025 /* On Gfx12+ this format is not listed in TGL PRMs, Volume 2b: Command
3026 * Reference: Enumerations, RenderCompressionFormat
3027 */
3028 if (ISL_GFX_VER(dev) >= 12 &&
3029 surf->format == ISL_FORMAT_R9G9B9E5_SHAREDEXP)
3030 return false;
3031
3032 /* The following are true of all multisampled surfaces */
3033 assert(surf->samples > 1);
3034 assert(surf->dim == ISL_SURF_DIM_2D);
3035 assert(surf->levels == 1);
3036 assert(surf->logical_level0_px.depth == 1);
3037 assert(isl_format_supports_multisampling(dev->info, surf->format));
3038
3039 enum isl_format mcs_format;
3040 switch (surf->samples) {
3041 case 2: mcs_format = ISL_FORMAT_MCS_2X; break;
3042 case 4: mcs_format = ISL_FORMAT_MCS_4X; break;
3043 case 8: mcs_format = ISL_FORMAT_MCS_8X; break;
3044 case 16: mcs_format = ISL_FORMAT_MCS_16X; break;
3045 default:
3046 unreachable("Invalid sample count");
3047 }
3048
3049 return isl_surf_init(dev, mcs_surf,
3050 .dim = ISL_SURF_DIM_2D,
3051 .format = mcs_format,
3052 .width = surf->logical_level0_px.width,
3053 .height = surf->logical_level0_px.height,
3054 .depth = 1,
3055 .levels = 1,
3056 .array_len = surf->logical_level0_px.array_len,
3057 .samples = 1, /* MCS surfaces are really single-sampled */
3058 .usage = ISL_SURF_USAGE_MCS_BIT,
3059 .tiling_flags = ISL_TILING_ANY_MASK);
3060 }
3061
3062 bool
_isl_surf_info_supports_ccs(const struct isl_device * dev,enum isl_format format,isl_surf_usage_flags_t usage)3063 _isl_surf_info_supports_ccs(const struct isl_device *dev,
3064 enum isl_format format,
3065 isl_surf_usage_flags_t usage)
3066 {
3067 if (!isl_format_supports_ccs_d(dev->info, format) &&
3068 !isl_format_supports_ccs_e(dev->info, format))
3069 return false;
3070
3071 /* CCS is only for color images on Gfx7-11 */
3072 if (ISL_GFX_VER(dev) <= 11 && isl_surf_usage_is_depth_or_stencil(usage))
3073 return false;
3074
3075 if (usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
3076 return false;
3077
3078 /* TODO: Disable for now, as we're not sure about the meaning of
3079 * 3DSTATE_CPSIZE_CONTROL_BUFFER::CPCBCompressionEnable
3080 */
3081 if (isl_surf_usage_is_cpb(usage) && dev->info->ver < 20)
3082 return false;
3083
3084 if (INTEL_DEBUG(DEBUG_NO_CCS))
3085 return false;
3086
3087 return true;
3088 }
3089
3090 bool
isl_surf_supports_ccs(const struct isl_device * dev,const struct isl_surf * surf,const struct isl_surf * hiz_or_mcs_surf)3091 isl_surf_supports_ccs(const struct isl_device *dev,
3092 const struct isl_surf *surf,
3093 const struct isl_surf *hiz_or_mcs_surf)
3094 {
3095 if (!_isl_surf_info_supports_ccs(dev, surf->format, surf->usage))
3096 return false;
3097
3098 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
3099 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
3100 *
3101 * - Support is limited to tiled render targets.
3102 *
3103 * From the BSpec (44930) for Gfx12:
3104 *
3105 * Linear CCS is only allowed for Untyped Buffers but only via HDC
3106 * Data-Port messages.
3107 *
3108 * We never use untyped messages on surfaces created by ISL on Gfx9+ so
3109 * this means linear is out on Gfx12+ as well.
3110 */
3111 if (surf->tiling == ISL_TILING_LINEAR)
3112 return false;
3113
3114 /* From the SKL PRMs, Volume 7: MCS Buffer for Render Target(s),
3115 *
3116 * - Note: Lossless Color Compression can only be applied to Surfaces
3117 * which are TileY, TileYs, or TileYf.
3118 *
3119 * From the ACM PRMs, Volume 9: MCS/CCS Buffers for Render Target(s),
3120 *
3121 * - Note: Lossless Color Compression can only be applied to Surfaces
3122 * which are Linear, Tile4, or Tile64. (TileY/TileYF/TileYS on older
3123 * devices)
3124 *
3125 * It is made clear that X-tiling is no longer supported on SKL+.
3126 */
3127 if (ISL_GFX_VER(dev) >= 9 && surf->tiling == ISL_TILING_X)
3128 return false;
3129
3130 /* TODO: add CCS support for Ys/Yf */
3131 if (isl_tiling_is_std_y(surf->tiling))
3132 return false;
3133
3134 if (ISL_GFX_VER(dev) >= 12) {
3135 if (isl_surf_usage_is_stencil(surf->usage)) {
3136 /* HiZ and MCS aren't allowed with stencil */
3137 assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
3138
3139 /* Multi-sampled stencil cannot have CCS */
3140 if (surf->samples > 1)
3141 return false;
3142
3143 /* Wa_22015614752: There are issues with multiple engines accessing
3144 * the same CCS cacheline in parallel. We need a 64KB alignment
3145 * between image subresources in order to avoid those issues, but as
3146 * can be seen from isl_gfx125_filter_tiling, we can't use Tile64 to
3147 * achieve that for 3D surfaces. We're limited to rely on other
3148 * layout parameters which can't help us to achieve the target
3149 * in all cases. So, we choose to disable CCS.
3150 */
3151 if (intel_needs_workaround(dev->info, 22015614752) &&
3152 (surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
3153 surf->dim == ISL_SURF_DIM_3D) {
3154 assert(surf->tiling == ISL_TILING_4);
3155 return false;
3156 }
3157 } else if (isl_surf_usage_is_depth(surf->usage)) {
3158 const struct isl_surf *hiz_surf = hiz_or_mcs_surf;
3159
3160 /* With depth surfaces, HIZ is required for CCS. */
3161 if (hiz_surf == NULL || hiz_surf->size_B == 0)
3162 return false;
3163
3164 /* Wa_22015614752: There are issues with multiple engines accessing
3165 * the same CCS cacheline in parallel. We need a 64KB alignment
3166 * between image subresources in order to avoid those issues, but as
3167 * can be seen from isl_gfx125_filter_tiling, we can't use Tile64 to
3168 * achieve that for 3D surfaces. We're limited to rely on other
3169 * layout parameters which can't help us to achieve the target
3170 * in all cases. So, we choose to disable CCS.
3171 */
3172 if (intel_needs_workaround(dev->info, 22015614752) &&
3173 (surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
3174 surf->dim == ISL_SURF_DIM_3D) {
3175 assert(surf->tiling == ISL_TILING_4);
3176 return false;
3177 }
3178
3179 assert(hiz_surf->usage & ISL_SURF_USAGE_HIZ_BIT);
3180 assert(hiz_surf->tiling == ISL_TILING_HIZ);
3181 assert(isl_format_is_hiz(hiz_surf->format));
3182 } else if (surf->samples > 1) {
3183 const struct isl_surf *mcs_surf = hiz_or_mcs_surf;
3184
3185 /* With multisampled color, CCS requires MCS */
3186 if (mcs_surf == NULL || mcs_surf->size_B == 0)
3187 return false;
3188
3189 assert(mcs_surf->usage & ISL_SURF_USAGE_MCS_BIT);
3190 assert(isl_format_is_mcs(mcs_surf->format));
3191 } else {
3192 /* Single-sampled color can't have MCS or HiZ */
3193 assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
3194
3195 /* Wa_1406738321: 3D textures need a blit to a new surface
3196 * in order to perform a resolve. For now, just disable CCS on TGL.
3197 */
3198 if (dev->info->verx10 == 120 && surf->dim == ISL_SURF_DIM_3D)
3199 return false;
3200
3201 /* From Bspec 49252, Render Decompression:
3202 *
3203 * "Compressed displayable surfaces must be 16KB aligned and have
3204 * pitches padded to multiple of 4 tiles."
3205 *
3206 * The drm_fourcc.h header doesn't require the aligned address for
3207 * compressed dmabufs, but it does require the aligned pitch.
3208 */
3209 if (isl_surf_usage_is_display(surf->usage)) {
3210 assert(surf->tiling == ISL_TILING_4 ||
3211 surf->tiling == ISL_TILING_Y0);
3212 if (surf->row_pitch_B % 512 != 0)
3213 return false;
3214 }
3215 }
3216
3217 if (intel_needs_workaround(dev->info, 22015614752) &&
3218 (surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
3219 (surf->levels > 1 ||
3220 surf->logical_level0_px.depth > 1 ||
3221 surf->logical_level0_px.array_len > 1)) {
3222 /* There are issues with multiple engines accessing the same CCS
3223 * cacheline in parallel. This can happen if this image has multiple
3224 * subresources. Such conflicts can be avoided with tilings that set
3225 * the subresource alignment to 64K and with miptails disabled. If we
3226 * aren't using such a configuration, disable CCS.
3227 */
3228 assert(surf->miptail_start_level >= surf->levels);
3229 if (surf->tiling != ISL_TILING_64)
3230 return false;
3231 }
3232
3233 /* BSpec 44930: (Gfx12, Gfx12.5)
3234 *
3235 * "Compression of 3D Ys surfaces with 64 or 128 bpp is not supported
3236 * in Gen12. Moreover, "Render Target Fast-clear Enable" command is
3237 * not supported for any 3D Ys surfaces. except when Surface is a
3238 * Procdural Texture."
3239 *
3240 * Since the note applies to MTL, we apply this to TILE64 too.
3241 */
3242 uint32_t format_bpb = isl_format_get_layout(surf->format)->bpb;
3243 if (ISL_GFX_VER(dev) == 12 &&
3244 surf->dim == ISL_SURF_DIM_3D &&
3245 (surf->tiling == ISL_TILING_ICL_Ys ||
3246 isl_tiling_is_64(surf->tiling)) &&
3247 (format_bpb == 64 || format_bpb == 128))
3248 return false;
3249 } else {
3250 /* ISL_GFX_VER(dev) < 12 */
3251 if (surf->samples > 1)
3252 return false;
3253
3254 /* CCS is only for color images on Gfx7-11 */
3255 assert(!isl_surf_usage_is_depth_or_stencil(surf->usage));
3256
3257 /* We're single-sampled color so having HiZ or MCS makes no sense */
3258 assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
3259
3260 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
3261 * work for 3D textures until gfx9 where the layout of 3D textures
3262 * changes to match 2D array textures.
3263 */
3264 if (ISL_GFX_VER(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
3265 return false;
3266
3267 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
3268 * Non-MultiSampler Render Target Restrictions):
3269 *
3270 * "Support is for non-mip-mapped and non-array surface types only."
3271 *
3272 * This restriction is lifted on gfx8+. Technically, it may be possible
3273 * to create a CCS for an arrayed or mipmapped image and only enable
3274 * CCS_D when rendering to the base slice. However, there is no
3275 * documentation tell us what the hardware would do in that case or what
3276 * it does if you walk off the bases slice. (Does it ignore CCS or does
3277 * it start scribbling over random memory?) We play it safe and just
3278 * follow the docs and don't allow CCS_D for arrayed or mip-mapped
3279 * surfaces.
3280 */
3281 if (ISL_GFX_VER(dev) <= 7 &&
3282 (surf->levels > 1 || surf->logical_level0_px.array_len > 1))
3283 return false;
3284 }
3285
3286 return true;
3287 }
3288
3289 bool
isl_surf_get_ccs_surf(const struct isl_device * dev,const struct isl_surf * surf,struct isl_surf * ccs_surf,uint32_t row_pitch_B)3290 isl_surf_get_ccs_surf(const struct isl_device *dev,
3291 const struct isl_surf *surf,
3292 struct isl_surf *ccs_surf,
3293 uint32_t row_pitch_B)
3294 {
3295 if (!isl_surf_supports_ccs(dev, surf, NULL))
3296 return false;
3297
3298 enum isl_format ccs_format;
3299 if (ISL_GFX_VER(dev) >= 9 && ISL_GFX_VER(dev) <= 11) {
3300 switch (isl_format_get_layout(surf->format)->bpb) {
3301 case 32: ccs_format = ISL_FORMAT_GFX9_CCS_32BPP; break;
3302 case 64: ccs_format = ISL_FORMAT_GFX9_CCS_64BPP; break;
3303 case 128: ccs_format = ISL_FORMAT_GFX9_CCS_128BPP; break;
3304 default: unreachable("Unsupported CCS format");
3305 }
3306 } else if (surf->tiling == ISL_TILING_Y0) {
3307 switch (isl_format_get_layout(surf->format)->bpb) {
3308 case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_Y; break;
3309 case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_Y; break;
3310 case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_Y; break;
3311 default: unreachable("Unsupported CCS format");
3312 }
3313 } else if (surf->tiling == ISL_TILING_X) {
3314 switch (isl_format_get_layout(surf->format)->bpb) {
3315 case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_X; break;
3316 case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_X; break;
3317 case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_X; break;
3318 default: unreachable("Unsupported CCS format");
3319 }
3320 } else {
3321 unreachable("Invalid tiling format");
3322 }
3323
3324 return isl_surf_init(dev, ccs_surf,
3325 .dim = surf->dim,
3326 .format = ccs_format,
3327 .width = surf->logical_level0_px.width,
3328 .height = surf->logical_level0_px.height,
3329 .depth = surf->logical_level0_px.depth,
3330 .levels = surf->levels,
3331 .array_len = surf->logical_level0_px.array_len,
3332 .samples = 1,
3333 .row_pitch_B = row_pitch_B,
3334 .usage = ISL_SURF_USAGE_CCS_BIT,
3335 .tiling_flags = ISL_TILING_CCS_BIT);
3336 }
3337
3338 #define isl_genX_call(dev, func, ...) \
3339 switch (ISL_GFX_VERX10(dev)) { \
3340 case 40: \
3341 isl_gfx4_##func(__VA_ARGS__); \
3342 break; \
3343 case 45: \
3344 /* G45 surface state is the same as gfx5 */ \
3345 case 50: \
3346 isl_gfx5_##func(__VA_ARGS__); \
3347 break; \
3348 case 60: \
3349 isl_gfx6_##func(__VA_ARGS__); \
3350 break; \
3351 case 70: \
3352 isl_gfx7_##func(__VA_ARGS__); \
3353 break; \
3354 case 75: \
3355 isl_gfx75_##func(__VA_ARGS__); \
3356 break; \
3357 case 80: \
3358 isl_gfx8_##func(__VA_ARGS__); \
3359 break; \
3360 case 90: \
3361 isl_gfx9_##func(__VA_ARGS__); \
3362 break; \
3363 case 110: \
3364 isl_gfx11_##func(__VA_ARGS__); \
3365 break; \
3366 case 120: \
3367 isl_gfx12_##func(__VA_ARGS__); \
3368 break; \
3369 case 125: \
3370 isl_gfx125_##func(__VA_ARGS__); \
3371 break; \
3372 case 200: \
3373 isl_gfx20_##func(__VA_ARGS__); \
3374 break; \
3375 default: \
3376 assert(!"Unknown hardware generation"); \
3377 }
3378
3379 /**
3380 * A variant of isl_surf_get_image_offset_sa() specific to
3381 * ISL_DIM_LAYOUT_GFX4_2D.
3382 */
3383 static void
get_image_offset_sa_gfx4_2d(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)3384 get_image_offset_sa_gfx4_2d(const struct isl_surf *surf,
3385 uint32_t level, uint32_t logical_array_layer,
3386 uint32_t *x_offset_sa,
3387 uint32_t *y_offset_sa,
3388 uint32_t *z_offset_sa,
3389 uint32_t *array_offset)
3390 {
3391 assert(level < surf->levels);
3392 if (surf->dim == ISL_SURF_DIM_3D)
3393 assert(logical_array_layer < surf->logical_level0_px.depth);
3394 else
3395 assert(logical_array_layer < surf->logical_level0_px.array_len);
3396
3397 const struct isl_extent3d image_align_sa =
3398 isl_surf_get_image_alignment_sa(surf);
3399
3400 const uint32_t W0 = surf->phys_level0_sa.width;
3401 const uint32_t H0 = surf->phys_level0_sa.height;
3402
3403 const uint32_t phys_layer = logical_array_layer *
3404 (surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1);
3405
3406 uint32_t x = 0, y;
3407 if (isl_tiling_is_std_y(surf->tiling) ||
3408 isl_tiling_is_64(surf->tiling)) {
3409 y = 0;
3410 if (surf->dim == ISL_SURF_DIM_3D) {
3411 *z_offset_sa = logical_array_layer;
3412 *array_offset = 0;
3413 } else {
3414 *z_offset_sa = 0;
3415 *array_offset = phys_layer;
3416 }
3417 } else {
3418 y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf);
3419 *z_offset_sa = 0;
3420 *array_offset = 0;
3421 }
3422
3423 for (uint32_t l = 0; l < MIN(level, surf->miptail_start_level); ++l) {
3424 if (l == 1) {
3425 uint32_t W = isl_minify(W0, l);
3426 x += isl_align_npot(W, image_align_sa.w);
3427 } else {
3428 uint32_t H = isl_minify(H0, l);
3429 y += isl_align_npot(H, image_align_sa.h);
3430 }
3431 }
3432
3433 *x_offset_sa = x;
3434 *y_offset_sa = y;
3435
3436 if (level >= surf->miptail_start_level) {
3437 const struct isl_format_layout *fmtl =
3438 isl_format_get_layout(surf->format);
3439
3440 uint32_t tail_offset_x_el, tail_offset_y_el, tail_offset_z_el;
3441 isl_get_miptail_level_offset_el(surf->tiling, surf->dim,
3442 fmtl->bpb,
3443 level - surf->miptail_start_level,
3444 &tail_offset_x_el,
3445 &tail_offset_y_el,
3446 &tail_offset_z_el);
3447 *x_offset_sa += tail_offset_x_el * fmtl->bw;
3448 *y_offset_sa += tail_offset_y_el * fmtl->bh;
3449 *z_offset_sa += tail_offset_z_el * fmtl->bd;
3450 }
3451 }
3452
3453 /**
3454 * A variant of isl_surf_get_image_offset_sa() specific to
3455 * ISL_DIM_LAYOUT_GFX4_3D.
3456 */
3457 static void
get_image_offset_sa_gfx4_3d(const struct isl_surf * surf,uint32_t level,uint32_t logical_z_offset_px,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3458 get_image_offset_sa_gfx4_3d(const struct isl_surf *surf,
3459 uint32_t level, uint32_t logical_z_offset_px,
3460 uint32_t *x_offset_sa,
3461 uint32_t *y_offset_sa)
3462 {
3463 assert(level < surf->levels);
3464 if (surf->dim == ISL_SURF_DIM_3D) {
3465 assert(surf->phys_level0_sa.array_len == 1);
3466 assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
3467 } else {
3468 assert(surf->dim == ISL_SURF_DIM_2D);
3469 assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
3470 assert(surf->phys_level0_sa.array_len == 6);
3471 assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
3472 }
3473
3474 const struct isl_extent3d image_align_sa =
3475 isl_surf_get_image_alignment_sa(surf);
3476
3477 const uint32_t W0 = surf->phys_level0_sa.width;
3478 const uint32_t H0 = surf->phys_level0_sa.height;
3479 const uint32_t D0 = surf->phys_level0_sa.depth;
3480 const uint32_t AL = surf->phys_level0_sa.array_len;
3481
3482 uint32_t x = 0;
3483 uint32_t y = 0;
3484
3485 for (uint32_t l = 0; l < level; ++l) {
3486 const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h);
3487 const uint32_t level_d =
3488 isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
3489 image_align_sa.d);
3490 const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
3491
3492 y += level_h * max_layers_vert;
3493 }
3494
3495 const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w);
3496 const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h);
3497 const uint32_t level_d =
3498 isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
3499 image_align_sa.d);
3500
3501 const uint32_t max_layers_horiz = MIN(level_d, 1u << level);
3502
3503 x += level_w * (logical_z_offset_px % max_layers_horiz);
3504 y += level_h * (logical_z_offset_px / max_layers_horiz);
3505
3506 *x_offset_sa = x;
3507 *y_offset_sa = y;
3508 }
3509
3510 static void
get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3511 get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf *surf,
3512 uint32_t level,
3513 uint32_t logical_array_layer,
3514 uint32_t *x_offset_sa,
3515 uint32_t *y_offset_sa)
3516 {
3517 assert(level < surf->levels);
3518 assert(surf->logical_level0_px.depth == 1);
3519 assert(logical_array_layer < surf->logical_level0_px.array_len);
3520
3521 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3522
3523 const struct isl_extent3d image_align_sa =
3524 isl_surf_get_image_alignment_sa(surf);
3525
3526 struct isl_tile_info tile_info;
3527 isl_surf_get_tile_info(surf, &tile_info);
3528 const struct isl_extent2d tile_extent_sa = {
3529 .w = tile_info.logical_extent_el.w * fmtl->bw,
3530 .h = tile_info.logical_extent_el.h * fmtl->bh,
3531 };
3532 /* Tile size is a multiple of image alignment */
3533 assert(tile_extent_sa.w % image_align_sa.w == 0);
3534 assert(tile_extent_sa.h % image_align_sa.h == 0);
3535
3536 const uint32_t W0 = surf->phys_level0_sa.w;
3537 const uint32_t H0 = surf->phys_level0_sa.h;
3538
3539 /* Each image has the same height as LOD0 because the hardware thinks
3540 * everything is LOD0
3541 */
3542 const uint32_t H = isl_align(H0, image_align_sa.h);
3543
3544 /* Quick sanity check for consistency */
3545 if (surf->phys_level0_sa.array_len > 1)
3546 assert(surf->array_pitch_el_rows == isl_assert_div(H, fmtl->bh));
3547
3548 uint32_t x = 0, y = 0;
3549 for (uint32_t l = 0; l < level; ++l) {
3550 const uint32_t W = isl_minify(W0, l);
3551
3552 const uint32_t w = isl_align(W, tile_extent_sa.w);
3553 const uint32_t h = isl_align(H * surf->phys_level0_sa.a,
3554 tile_extent_sa.h);
3555
3556 if (l == 0) {
3557 y += h;
3558 } else {
3559 x += w;
3560 }
3561 }
3562
3563 y += H * logical_array_layer;
3564
3565 *x_offset_sa = x;
3566 *y_offset_sa = y;
3567 }
3568
3569 /**
3570 * A variant of isl_surf_get_image_offset_sa() specific to
3571 * ISL_DIM_LAYOUT_GFX9_1D.
3572 */
3573 static void
get_image_offset_sa_gfx9_1d(const struct isl_surf * surf,uint32_t level,uint32_t layer,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3574 get_image_offset_sa_gfx9_1d(const struct isl_surf *surf,
3575 uint32_t level, uint32_t layer,
3576 uint32_t *x_offset_sa,
3577 uint32_t *y_offset_sa)
3578 {
3579 assert(level < surf->levels);
3580 assert(layer < surf->phys_level0_sa.array_len);
3581 assert(surf->phys_level0_sa.height == 1);
3582 assert(surf->phys_level0_sa.depth == 1);
3583 assert(surf->samples == 1);
3584
3585 const uint32_t W0 = surf->phys_level0_sa.width;
3586 const struct isl_extent3d image_align_sa =
3587 isl_surf_get_image_alignment_sa(surf);
3588
3589 uint32_t x = 0;
3590
3591 for (uint32_t l = 0; l < level; ++l) {
3592 uint32_t W = isl_minify(W0, l);
3593 uint32_t w = isl_align_npot(W, image_align_sa.w);
3594
3595 x += w;
3596 }
3597
3598 *x_offset_sa = x;
3599 *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf);
3600 }
3601
3602 /**
3603 * Calculate the offset, in units of surface samples, to a subimage in the
3604 * surface.
3605 *
3606 * @invariant level < surface levels
3607 * @invariant logical_array_layer < logical array length of surface
3608 * @invariant logical_z_offset_px < logical depth of surface at level
3609 */
3610 void
isl_surf_get_image_offset_sa(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)3611 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
3612 uint32_t level,
3613 uint32_t logical_array_layer,
3614 uint32_t logical_z_offset_px,
3615 uint32_t *x_offset_sa,
3616 uint32_t *y_offset_sa,
3617 uint32_t *z_offset_sa,
3618 uint32_t *array_offset)
3619 {
3620 assert(level < surf->levels);
3621 assert(logical_array_layer < surf->logical_level0_px.array_len);
3622 assert(logical_z_offset_px
3623 < isl_minify(surf->logical_level0_px.depth, level));
3624
3625 switch (surf->dim_layout) {
3626 case ISL_DIM_LAYOUT_GFX9_1D:
3627 get_image_offset_sa_gfx9_1d(surf, level, logical_array_layer,
3628 x_offset_sa, y_offset_sa);
3629 *z_offset_sa = 0;
3630 *array_offset = 0;
3631 break;
3632 case ISL_DIM_LAYOUT_GFX4_2D:
3633 get_image_offset_sa_gfx4_2d(surf, level, logical_array_layer
3634 + logical_z_offset_px,
3635 x_offset_sa, y_offset_sa,
3636 z_offset_sa, array_offset);
3637 break;
3638 case ISL_DIM_LAYOUT_GFX4_3D:
3639 get_image_offset_sa_gfx4_3d(surf, level, logical_array_layer +
3640 logical_z_offset_px,
3641 x_offset_sa, y_offset_sa);
3642 *z_offset_sa = 0;
3643 *array_offset = 0;
3644 break;
3645 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
3646 get_image_offset_sa_gfx6_stencil_hiz(surf, level, logical_array_layer +
3647 logical_z_offset_px,
3648 x_offset_sa, y_offset_sa);
3649 *z_offset_sa = 0;
3650 *array_offset = 0;
3651 break;
3652
3653 default:
3654 unreachable("not reached");
3655 }
3656 }
3657
3658 void
isl_surf_get_image_offset_el(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint32_t * x_offset_el,uint32_t * y_offset_el,uint32_t * z_offset_el,uint32_t * array_offset)3659 isl_surf_get_image_offset_el(const struct isl_surf *surf,
3660 uint32_t level,
3661 uint32_t logical_array_layer,
3662 uint32_t logical_z_offset_px,
3663 uint32_t *x_offset_el,
3664 uint32_t *y_offset_el,
3665 uint32_t *z_offset_el,
3666 uint32_t *array_offset)
3667 {
3668 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3669
3670 assert(level < surf->levels);
3671 assert(logical_array_layer < surf->logical_level0_px.array_len);
3672 assert(logical_z_offset_px
3673 < isl_minify(surf->logical_level0_px.depth, level));
3674
3675 uint32_t x_offset_sa, y_offset_sa, z_offset_sa;
3676 isl_surf_get_image_offset_sa(surf, level,
3677 logical_array_layer,
3678 logical_z_offset_px,
3679 &x_offset_sa,
3680 &y_offset_sa,
3681 &z_offset_sa,
3682 array_offset);
3683
3684 *x_offset_el = x_offset_sa / fmtl->bw;
3685 *y_offset_el = y_offset_sa / fmtl->bh;
3686 *z_offset_el = z_offset_sa / fmtl->bd;
3687 }
3688
3689 void
isl_surf_get_image_offset_B_tile_sa(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint64_t * offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3690 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
3691 uint32_t level,
3692 uint32_t logical_array_layer,
3693 uint32_t logical_z_offset_px,
3694 uint64_t *offset_B,
3695 uint32_t *x_offset_sa,
3696 uint32_t *y_offset_sa)
3697 {
3698 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3699
3700 uint32_t x_offset_el, y_offset_el;
3701 isl_surf_get_image_offset_B_tile_el(surf, level,
3702 logical_array_layer,
3703 logical_z_offset_px,
3704 offset_B,
3705 &x_offset_el,
3706 &y_offset_el);
3707
3708 if (x_offset_sa) {
3709 *x_offset_sa = x_offset_el * fmtl->bw;
3710 } else {
3711 assert(x_offset_el == 0);
3712 }
3713
3714 if (y_offset_sa) {
3715 *y_offset_sa = y_offset_el * fmtl->bh;
3716 } else {
3717 assert(y_offset_el == 0);
3718 }
3719 }
3720
3721 void
isl_surf_get_image_offset_B_tile_el(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint64_t * offset_B,uint32_t * x_offset_el,uint32_t * y_offset_el)3722 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
3723 uint32_t level,
3724 uint32_t logical_array_layer,
3725 uint32_t logical_z_offset_px,
3726 uint64_t *offset_B,
3727 uint32_t *x_offset_el,
3728 uint32_t *y_offset_el)
3729 {
3730 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3731
3732 uint32_t total_x_offset_el, total_y_offset_el;
3733 uint32_t total_z_offset_el, total_array_offset;
3734 isl_surf_get_image_offset_el(surf, level, logical_array_layer,
3735 logical_z_offset_px,
3736 &total_x_offset_el,
3737 &total_y_offset_el,
3738 &total_z_offset_el,
3739 &total_array_offset);
3740
3741 uint32_t z_offset_el, array_offset;
3742 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
3743 surf->msaa_layout, fmtl->bpb,
3744 surf->samples,
3745 surf->row_pitch_B,
3746 surf->array_pitch_el_rows,
3747 total_x_offset_el,
3748 total_y_offset_el,
3749 total_z_offset_el,
3750 total_array_offset,
3751 offset_B,
3752 x_offset_el,
3753 y_offset_el,
3754 &z_offset_el,
3755 &array_offset);
3756 if (level >= surf->miptail_start_level) {
3757 /* We can do a byte offset to the first level of a miptail but we cannot
3758 * offset into a miptail.
3759 */
3760 assert(level == surf->miptail_start_level);
3761
3762 /* The byte offset will get us to the miptail page. The other offsets
3763 * are to the actual level within the miptail. It is assumed that the
3764 * caller will set up a texture with a miptail and use the hardware to
3765 * handle offseting inside the miptail.
3766 */
3767 *x_offset_el = 0;
3768 *y_offset_el = 0;
3769 } else {
3770 assert(z_offset_el == 0);
3771 assert(array_offset == 0);
3772 }
3773 }
3774
3775 void
isl_surf_get_image_range_B_tile(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint64_t * start_tile_B,uint64_t * end_tile_B)3776 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
3777 uint32_t level,
3778 uint32_t logical_array_layer,
3779 uint32_t logical_z_offset_px,
3780 uint64_t *start_tile_B,
3781 uint64_t *end_tile_B)
3782 {
3783 uint32_t start_x_offset_el, start_y_offset_el;
3784 uint32_t start_z_offset_el, start_array_slice;
3785 isl_surf_get_image_offset_el(surf, level, logical_array_layer,
3786 logical_z_offset_px,
3787 &start_x_offset_el,
3788 &start_y_offset_el,
3789 &start_z_offset_el,
3790 &start_array_slice);
3791
3792 /* Compute the size of the subimage in surface elements */
3793 const uint32_t subimage_w_sa = isl_minify(surf->phys_level0_sa.w, level);
3794 const uint32_t subimage_h_sa = isl_minify(surf->phys_level0_sa.h, level);
3795 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3796 const uint32_t subimage_w_el = isl_align_div_npot(subimage_w_sa, fmtl->bw);
3797 const uint32_t subimage_h_el = isl_align_div_npot(subimage_h_sa, fmtl->bh);
3798
3799 /* Find the last pixel */
3800 uint32_t end_x_offset_el = start_x_offset_el + subimage_w_el - 1;
3801 uint32_t end_y_offset_el = start_y_offset_el + subimage_h_el - 1;
3802
3803 /* We only consider one Z or array slice */
3804 const uint32_t end_z_offset_el = start_z_offset_el;
3805 const uint32_t end_array_slice = start_array_slice;
3806
3807 UNUSED uint32_t x_offset_el, y_offset_el, z_offset_el, array_slice;
3808 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
3809 surf->msaa_layout, fmtl->bpb,
3810 surf->samples,
3811 surf->row_pitch_B,
3812 surf->array_pitch_el_rows,
3813 start_x_offset_el,
3814 start_y_offset_el,
3815 start_z_offset_el,
3816 start_array_slice,
3817 start_tile_B,
3818 &x_offset_el,
3819 &y_offset_el,
3820 &z_offset_el,
3821 &array_slice);
3822
3823 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
3824 surf->msaa_layout, fmtl->bpb,
3825 surf->samples,
3826 surf->row_pitch_B,
3827 surf->array_pitch_el_rows,
3828 end_x_offset_el,
3829 end_y_offset_el,
3830 end_z_offset_el,
3831 end_array_slice,
3832 end_tile_B,
3833 &x_offset_el,
3834 &y_offset_el,
3835 &z_offset_el,
3836 &array_slice);
3837
3838 /* We want the range we return to be exclusive but the tile containing the
3839 * last pixel (what we just calculated) is inclusive. Add one.
3840 */
3841 (*end_tile_B)++;
3842
3843 assert(*end_tile_B <= surf->size_B);
3844 }
3845
3846 void
isl_surf_get_image_surf(const struct isl_device * dev,const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,struct isl_surf * image_surf,uint64_t * offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3847 isl_surf_get_image_surf(const struct isl_device *dev,
3848 const struct isl_surf *surf,
3849 uint32_t level,
3850 uint32_t logical_array_layer,
3851 uint32_t logical_z_offset_px,
3852 struct isl_surf *image_surf,
3853 uint64_t *offset_B,
3854 uint32_t *x_offset_sa,
3855 uint32_t *y_offset_sa)
3856 {
3857 isl_surf_get_image_offset_B_tile_sa(surf,
3858 level,
3859 logical_array_layer,
3860 logical_z_offset_px,
3861 offset_B,
3862 x_offset_sa,
3863 y_offset_sa);
3864
3865 /* Even for cube maps there will be only single face, therefore drop the
3866 * corresponding flag if present.
3867 */
3868 const isl_surf_usage_flags_t usage =
3869 surf->usage & (~ISL_SURF_USAGE_CUBE_BIT);
3870
3871 bool ok UNUSED;
3872 ok = isl_surf_init(dev, image_surf,
3873 .dim = ISL_SURF_DIM_2D,
3874 .format = surf->format,
3875 .width = isl_minify(surf->logical_level0_px.w, level),
3876 .height = isl_minify(surf->logical_level0_px.h, level),
3877 .depth = 1,
3878 .levels = 1,
3879 .array_len = 1,
3880 .samples = surf->samples,
3881 .row_pitch_B = surf->row_pitch_B,
3882 .usage = usage,
3883 .tiling_flags = (1 << surf->tiling));
3884 assert(ok);
3885 }
3886
3887 bool
isl_surf_get_uncompressed_surf(const struct isl_device * dev,const struct isl_surf * _surf,const struct isl_view * _view,struct isl_surf * ucompr_surf,struct isl_view * ucompr_view,uint64_t * offset_B,uint32_t * x_offset_el,uint32_t * y_offset_el)3888 isl_surf_get_uncompressed_surf(const struct isl_device *dev,
3889 const struct isl_surf *_surf,
3890 const struct isl_view *_view,
3891 struct isl_surf *ucompr_surf,
3892 struct isl_view *ucompr_view,
3893 uint64_t *offset_B,
3894 uint32_t *x_offset_el,
3895 uint32_t *y_offset_el)
3896 {
3897 /* Input and output pointers may be the same, save the input contents now. */
3898 const struct isl_surf __surf = *_surf, *surf = &__surf;
3899 const struct isl_view __view = *_view, *view = &__view;
3900 const struct isl_format_layout *fmtl =
3901 isl_format_get_layout(surf->format);
3902 const enum isl_format view_format = view->format;
3903
3904 assert(fmtl->bw > 1 || fmtl->bh > 1 || fmtl->bd > 1);
3905 assert(isl_format_is_compressed(surf->format));
3906 assert(!isl_format_is_compressed(view->format));
3907 assert(isl_format_get_layout(view->format)->bpb == fmtl->bpb);
3908 assert(view->levels == 1);
3909
3910 const uint32_t view_width_px =
3911 isl_minify(surf->logical_level0_px.width, view->base_level);
3912 const uint32_t view_height_px =
3913 isl_minify(surf->logical_level0_px.height, view->base_level);
3914
3915 assert(surf->samples == 1);
3916 const uint32_t view_width_el = isl_align_div_npot(view_width_px, fmtl->bw);
3917 const uint32_t view_height_el = isl_align_div_npot(view_height_px, fmtl->bh);
3918
3919 /* If we ever enable 3D block formats, we'll need to re-think this */
3920 assert(fmtl->bd == 1);
3921
3922 if (isl_tiling_is_std_y(surf->tiling) ||
3923 isl_tiling_is_64(surf->tiling)) {
3924 /* If the requested level is not part of the miptail, we just offset to
3925 * the requested level. Because we're using standard tilings and aren't
3926 * in the miptail, arrays and 3D textures should just work so long as we
3927 * have the right array stride in the end.
3928 *
3929 * If the requested level is in the miptail, we instead offset to the
3930 * base of the miptail. Because offsets into the miptail are fixed by
3931 * the tiling and don't depend on the actual size of the image, we can
3932 * set the level in the view to offset into the miptail regardless of
3933 * the fact minification yields different results for the compressed and
3934 * uncompressed surface.
3935 */
3936 const uint32_t base_level =
3937 MIN(view->base_level, surf->miptail_start_level);
3938
3939 isl_surf_get_image_offset_B_tile_el(surf, base_level, 0, 0,
3940 offset_B, x_offset_el, y_offset_el);
3941 /* Tile64, Ys and Yf should have no intratile X or Y offset */
3942 assert(*x_offset_el == 0 && *y_offset_el == 0);
3943
3944 /* Save off the array pitch */
3945 const uint32_t array_pitch_el_rows = surf->array_pitch_el_rows;
3946
3947 const uint32_t view_depth_px =
3948 isl_minify(surf->logical_level0_px.depth, view->base_level);
3949 const uint32_t view_depth_el =
3950 isl_align_div_npot(view_depth_px, fmtl->bd);
3951
3952 /* We need to compute the size of the uncompressed surface we will
3953 * create. If we're not in the miptail, it is just the view size in
3954 * surface elements. If we are in a miptail, we need a size that will
3955 * minify to the view size in surface elements. This may not be the same
3956 * as the size of base_level, but that's not a problem. Slot offsets are
3957 * fixed in HW (see the tables used in isl_get_miptail_level_offset_el).
3958 */
3959 const uint32_t ucompr_level = view->base_level - base_level;
3960
3961 /* The > 1 check is here to prevent a change in the surface's overall
3962 * dimension (e.g. 2D->3D).
3963 *
3964 * Also having a base_level dimension = 1 doesn´t mean the HW will
3965 * ignore higher mip level. Once the dimension has reached 1, it'll stay
3966 * at 1 in the higher mip levels.
3967 */
3968 struct isl_extent3d ucompr_surf_extent_el = {
3969 .w = view_width_el > 1 ? view_width_el << ucompr_level : 1,
3970 .h = view_height_el > 1 ? view_height_el << ucompr_level : 1,
3971 .d = view_depth_el > 1 ? view_depth_el << ucompr_level : 1,
3972 };
3973
3974 bool ok UNUSED;
3975 ok = isl_surf_init(dev, ucompr_surf,
3976 .dim = surf->dim,
3977 .format = view->format,
3978 .width = ucompr_surf_extent_el.width,
3979 .height = ucompr_surf_extent_el.height,
3980 .depth = ucompr_surf_extent_el.depth,
3981 .levels = ucompr_level + 1,
3982 .array_len = surf->logical_level0_px.array_len,
3983 .samples = surf->samples,
3984 .min_miptail_start_level =
3985 (int) (view->base_level < surf->miptail_start_level),
3986 .row_pitch_B = surf->row_pitch_B,
3987 .usage = surf->usage,
3988 .tiling_flags = (1u << surf->tiling));
3989 assert(ok);
3990
3991 /* Use the array pitch from the original surface. This way 2D arrays
3992 * and 3D textures should work properly, just with one LOD.
3993 */
3994 assert(ucompr_surf->array_pitch_el_rows <= array_pitch_el_rows);
3995 ucompr_surf->array_pitch_el_rows = array_pitch_el_rows;
3996
3997 /* The newly created image represents only the one miplevel so we
3998 * need to adjust the view accordingly. Because we offset it to
3999 * miplevel but used a Z and array slice of 0, the array range can be
4000 * left alone.
4001 */
4002 *ucompr_view = *view;
4003 ucompr_view->base_level -= base_level;
4004 } else {
4005 if (view->array_len > 1) {
4006 /* The Skylake PRM Vol. 2d, "RENDER_SURFACE_STATE::X Offset" says:
4007 *
4008 * "If Surface Array is enabled, this field must be zero."
4009 *
4010 * The PRMs for other hardware have similar text. This is also tricky
4011 * to handle with things like BLORP's SW offsetting because the
4012 * increased surface size required for the offset may result in an
4013 * image height greater than qpitch.
4014 */
4015 if (view->base_level > 0)
4016 return false;
4017
4018 /* On Haswell and earlier, RENDER_SURFACE_STATE doesn't have a QPitch
4019 * field; it only has "array pitch span" which means the QPitch is
4020 * automatically calculated. Since we're smashing the surface format
4021 * (block formats are subtly different) and the number of miplevels,
4022 * that calculation will get thrown off. This means we can't do
4023 * arrays even at LOD0
4024 *
4025 * On Broadwell, we do have a QPitch field which we can control.
4026 * However, HALIGN and VALIGN are specified in pixels and are
4027 * hard-coded to align to exactly the block size of the compressed
4028 * texture. This means that, when reinterpreted as a non-compressed
4029 * the QPitch may be anything but the HW requires it to be properly
4030 * aligned.
4031 */
4032 if (ISL_GFX_VER(dev) < 9)
4033 return false;
4034
4035 *ucompr_surf = *surf;
4036 ucompr_surf->levels = 1;
4037 ucompr_surf->format = view_format;
4038
4039 /* We're making an uncompressed view here. The image dimensions need
4040 * to be scaled down by the block size.
4041 */
4042 assert(ucompr_surf->logical_level0_px.width == view_width_px);
4043 assert(ucompr_surf->logical_level0_px.height == view_height_px);
4044 ucompr_surf->logical_level0_px.width = view_width_el;
4045 ucompr_surf->logical_level0_px.height = view_height_el;
4046 ucompr_surf->phys_level0_sa = isl_surf_get_phys_level0_el(surf);
4047
4048 /* The surface mostly stays as-is; there is no offset */
4049 *offset_B = 0;
4050 *x_offset_el = 0;
4051 *y_offset_el = 0;
4052
4053 /* The view remains the same */
4054 *ucompr_view = *view;
4055 } else {
4056 /* If only one array slice is requested, directly offset to that
4057 * slice. We could, in theory, still use arrays in some cases but
4058 * BLORP isn't prepared for this and everyone who calls this function
4059 * should be prepared to handle an X/Y offset.
4060 */
4061 isl_surf_get_image_offset_B_tile_el(surf,
4062 view->base_level,
4063 surf->dim == ISL_SURF_DIM_3D ?
4064 0 : view->base_array_layer,
4065 surf->dim == ISL_SURF_DIM_3D ?
4066 view->base_array_layer : 0,
4067 offset_B,
4068 x_offset_el,
4069 y_offset_el);
4070
4071 isl_surf_usage_flags_t usage = surf->usage;
4072
4073 /* Even for cube maps there will be only single face, therefore drop
4074 * the corresponding flag if present.
4075 */
4076 usage &= ~ISL_SURF_USAGE_CUBE_BIT;
4077
4078 /* CCS-enabled surfaces can have different layout requirements than
4079 * surfaces without CCS support. So, for accuracy, disable CCS
4080 * support if the original surface lacked it.
4081 */
4082 if (_isl_surf_info_supports_ccs(dev, surf->format, surf->usage) !=
4083 _isl_surf_info_supports_ccs(dev, view_format, usage)) {
4084 assert(_isl_surf_info_supports_ccs(dev, view_format, usage));
4085 usage |= ISL_SURF_USAGE_DISABLE_AUX_BIT;
4086 }
4087
4088 bool ok UNUSED;
4089 ok = isl_surf_init(dev, ucompr_surf,
4090 .dim = ISL_SURF_DIM_2D,
4091 .format = view_format,
4092 .width = view_width_el,
4093 .height = view_height_el,
4094 .depth = 1,
4095 .levels = 1,
4096 .array_len = 1,
4097 .samples = 1,
4098 .row_pitch_B = surf->row_pitch_B,
4099 .usage = usage,
4100 .tiling_flags = (1 << surf->tiling));
4101 assert(ok);
4102
4103 /* The newly created image represents the one subimage we're
4104 * referencing with this view so it only has one array slice and
4105 * miplevel.
4106 */
4107 *ucompr_view = *view;
4108 ucompr_view->base_array_layer = 0;
4109 ucompr_view->base_level = 0;
4110 }
4111 }
4112
4113 return true;
4114 }
4115
4116 void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,uint32_t bpb,uint32_t samples,uint32_t row_pitch_B,uint32_t array_pitch_el_rows,uint32_t total_x_offset_el,uint32_t total_y_offset_el,uint32_t total_z_offset_el,uint32_t total_array_offset,uint64_t * tile_offset_B,uint32_t * x_offset_el,uint32_t * y_offset_el,uint32_t * z_offset_el,uint32_t * array_offset)4117 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
4118 enum isl_surf_dim dim,
4119 enum isl_msaa_layout msaa_layout,
4120 uint32_t bpb,
4121 uint32_t samples,
4122 uint32_t row_pitch_B,
4123 uint32_t array_pitch_el_rows,
4124 uint32_t total_x_offset_el,
4125 uint32_t total_y_offset_el,
4126 uint32_t total_z_offset_el,
4127 uint32_t total_array_offset,
4128 uint64_t *tile_offset_B,
4129 uint32_t *x_offset_el,
4130 uint32_t *y_offset_el,
4131 uint32_t *z_offset_el,
4132 uint32_t *array_offset)
4133 {
4134 if (tiling == ISL_TILING_LINEAR) {
4135 assert(bpb % 8 == 0);
4136 assert(samples == 1);
4137 assert(total_z_offset_el == 0 && total_array_offset == 0);
4138 *tile_offset_B = (uint64_t)total_y_offset_el * row_pitch_B +
4139 (uint64_t)total_x_offset_el * (bpb / 8);
4140 *x_offset_el = 0;
4141 *y_offset_el = 0;
4142 *z_offset_el = 0;
4143 *array_offset = 0;
4144 return;
4145 }
4146
4147 struct isl_tile_info tile_info;
4148 isl_tiling_get_info(tiling, dim, msaa_layout, bpb, samples, &tile_info);
4149
4150 /* Pitches must make sense with the tiling */
4151 assert(row_pitch_B % tile_info.phys_extent_B.width == 0);
4152 if (tile_info.logical_extent_el.d > 1 || tile_info.logical_extent_el.a > 1)
4153 assert(array_pitch_el_rows % tile_info.logical_extent_el.h == 0);
4154
4155 /* For non-power-of-two formats, we need the address to be both tile and
4156 * element-aligned. The easiest way to achieve this is to work with a tile
4157 * that is three times as wide as the regular tile.
4158 *
4159 * The tile info returned by get_tile_info has a logical size that is an
4160 * integer number of tile_info.format_bpb size elements. To scale the
4161 * tile, we scale up the physical width and then treat the logical tile
4162 * size as if it has bpb size elements.
4163 */
4164 const uint32_t tile_el_scale = bpb / tile_info.format_bpb;
4165 tile_info.phys_extent_B.width *= tile_el_scale;
4166
4167 /* Compute the offset into the tile */
4168 *x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w;
4169 *y_offset_el = total_y_offset_el % tile_info.logical_extent_el.h;
4170 *z_offset_el = total_z_offset_el % tile_info.logical_extent_el.d;
4171 *array_offset = total_array_offset % tile_info.logical_extent_el.a;
4172
4173 /* Compute the offset of the tile in units of whole tiles */
4174 uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w;
4175 uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h;
4176 uint32_t z_offset_tl = total_z_offset_el / tile_info.logical_extent_el.d;
4177 uint32_t a_offset_tl = total_array_offset / tile_info.logical_extent_el.a;
4178
4179 /* Compute an array pitch in number of tiles */
4180 uint32_t array_pitch_tl_rows =
4181 array_pitch_el_rows / tile_info.logical_extent_el.h;
4182
4183 /* Add the Z and array offset to the Y offset to get a 2D offset */
4184 y_offset_tl += (z_offset_tl + a_offset_tl) * array_pitch_tl_rows;
4185
4186 *tile_offset_B =
4187 (uint64_t)y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B +
4188 (uint64_t)x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w;
4189 }
4190
4191 uint32_t
isl_surf_get_depth_format(const struct isl_device * dev,const struct isl_surf * surf)4192 isl_surf_get_depth_format(const struct isl_device *dev,
4193 const struct isl_surf *surf)
4194 {
4195 /* Support for separate stencil buffers began in gfx5. Support for
4196 * interleaved depthstencil buffers ceased in gfx7. The intermediate gens,
4197 * those that supported separate and interleaved stencil, were gfx5 and
4198 * gfx6.
4199 *
4200 * For a list of all available formats, see the Sandybridge PRM >> Volume
4201 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
4202 * Format (p321).
4203 */
4204
4205 bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT;
4206
4207 assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT);
4208
4209 if (has_stencil)
4210 assert(ISL_GFX_VER(dev) < 7);
4211
4212 switch (surf->format) {
4213 default:
4214 unreachable("bad isl depth format");
4215 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS:
4216 assert(ISL_GFX_VER(dev) < 7);
4217 return 0; /* D32_FLOAT_S8X24_UINT */
4218 case ISL_FORMAT_R32_FLOAT:
4219 assert(!has_stencil);
4220 return 1; /* D32_FLOAT */
4221 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
4222 if (has_stencil) {
4223 assert(ISL_GFX_VER(dev) < 7);
4224 return 2; /* D24_UNORM_S8_UINT */
4225 } else {
4226 assert(ISL_GFX_VER(dev) >= 5);
4227 return 3; /* D24_UNORM_X8_UINT */
4228 }
4229 case ISL_FORMAT_R16_UNORM:
4230 assert(!has_stencil);
4231 return 5; /* D16_UNORM */
4232 }
4233 }
4234
4235 bool
isl_swizzle_supports_rendering(const struct intel_device_info * devinfo,struct isl_swizzle swizzle)4236 isl_swizzle_supports_rendering(const struct intel_device_info *devinfo,
4237 struct isl_swizzle swizzle)
4238 {
4239 if (devinfo->platform == INTEL_PLATFORM_HSW) {
4240 /* From the Haswell PRM,
4241 * RENDER_SURFACE_STATE::Shader Channel Select Red
4242 *
4243 * "The Shader channel selects also define which shader channels are
4244 * written to which surface channel. If the Shader channel select is
4245 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
4246 * shader channel select is SCS_RED it is written to the surface red
4247 * channel and so on. If more than one shader channel select is set
4248 * to the same surface channel only the first shader channel in RGBA
4249 * order will be written."
4250 */
4251 return true;
4252 } else if (devinfo->ver <= 7) {
4253 /* Ivy Bridge and early doesn't have any swizzling */
4254 return isl_swizzle_is_identity(swizzle);
4255 } else {
4256 /* From the Sky Lake PRM Vol. 2d,
4257 * RENDER_SURFACE_STATE::Shader Channel Select Red
4258 *
4259 * "For Render Target, Red, Green and Blue Shader Channel Selects
4260 * MUST be such that only valid components can be swapped i.e. only
4261 * change the order of components in the pixel. Any other values for
4262 * these Shader Channel Select fields are not valid for Render
4263 * Targets. This also means that there MUST not be multiple shader
4264 * channels mapped to the same RT channel."
4265 *
4266 * From the Sky Lake PRM Vol. 2d,
4267 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
4268 *
4269 * "For Render Target, this field MUST be programmed to
4270 * value = SCS_ALPHA."
4271 *
4272 * Bspec 57023: RENDER_SURFACE_STATE:: Shader Channel Select Red
4273 *
4274 * "Render Target messages do not support swapping of colors with
4275 * alpha. The Red, Green, or Blue Shader Channel Selects do not
4276 * support SCS_ALPHA. The Shader Channel Select Alpha does not support
4277 * SCS_RED, SCS_GREEN, or SCS_BLUE."
4278 */
4279 return (swizzle.r == ISL_CHANNEL_SELECT_RED ||
4280 swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
4281 swizzle.r == ISL_CHANNEL_SELECT_BLUE) &&
4282 (swizzle.g == ISL_CHANNEL_SELECT_RED ||
4283 swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
4284 swizzle.g == ISL_CHANNEL_SELECT_BLUE) &&
4285 (swizzle.b == ISL_CHANNEL_SELECT_RED ||
4286 swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
4287 swizzle.b == ISL_CHANNEL_SELECT_BLUE) &&
4288 swizzle.r != swizzle.g &&
4289 swizzle.r != swizzle.b &&
4290 swizzle.g != swizzle.b &&
4291 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
4292 }
4293 }
4294
4295 static enum isl_channel_select
swizzle_select(enum isl_channel_select chan,struct isl_swizzle swizzle)4296 swizzle_select(enum isl_channel_select chan, struct isl_swizzle swizzle)
4297 {
4298 switch (chan) {
4299 case ISL_CHANNEL_SELECT_ZERO:
4300 case ISL_CHANNEL_SELECT_ONE:
4301 return chan;
4302 case ISL_CHANNEL_SELECT_RED:
4303 return swizzle.r;
4304 case ISL_CHANNEL_SELECT_GREEN:
4305 return swizzle.g;
4306 case ISL_CHANNEL_SELECT_BLUE:
4307 return swizzle.b;
4308 case ISL_CHANNEL_SELECT_ALPHA:
4309 return swizzle.a;
4310 default:
4311 unreachable("Invalid swizzle component");
4312 }
4313 }
4314
4315 /**
4316 * Returns the single swizzle that is equivalent to applying the two given
4317 * swizzles in sequence.
4318 */
4319 struct isl_swizzle
isl_swizzle_compose(struct isl_swizzle first,struct isl_swizzle second)4320 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second)
4321 {
4322 return (struct isl_swizzle) {
4323 .r = swizzle_select(first.r, second),
4324 .g = swizzle_select(first.g, second),
4325 .b = swizzle_select(first.b, second),
4326 .a = swizzle_select(first.a, second),
4327 };
4328 }
4329
4330 /**
4331 * Returns a swizzle that is the pseudo-inverse of this swizzle.
4332 */
4333 struct isl_swizzle
isl_swizzle_invert(struct isl_swizzle swizzle)4334 isl_swizzle_invert(struct isl_swizzle swizzle)
4335 {
4336 /* Default to zero for channels which do not show up in the swizzle */
4337 enum isl_channel_select chans[4] = {
4338 ISL_CHANNEL_SELECT_ZERO,
4339 ISL_CHANNEL_SELECT_ZERO,
4340 ISL_CHANNEL_SELECT_ZERO,
4341 ISL_CHANNEL_SELECT_ZERO,
4342 };
4343
4344 /* We go in ABGR order so that, if there are any duplicates, the first one
4345 * is taken if you look at it in RGBA order. This is what Haswell hardware
4346 * does for render target swizzles.
4347 */
4348 if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
4349 chans[swizzle.a - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_ALPHA;
4350 if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
4351 chans[swizzle.b - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_BLUE;
4352 if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
4353 chans[swizzle.g - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_GREEN;
4354 if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
4355 chans[swizzle.r - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_RED;
4356
4357 return (struct isl_swizzle) { chans[0], chans[1], chans[2], chans[3] };
4358 }
4359
4360 static uint32_t
isl_color_value_channel(union isl_color_value src,enum isl_channel_select chan,uint32_t one)4361 isl_color_value_channel(union isl_color_value src,
4362 enum isl_channel_select chan,
4363 uint32_t one)
4364 {
4365 if (chan == ISL_CHANNEL_SELECT_ZERO)
4366 return 0;
4367 if (chan == ISL_CHANNEL_SELECT_ONE)
4368 return one;
4369
4370 assert(chan >= ISL_CHANNEL_SELECT_RED);
4371 assert(chan < ISL_CHANNEL_SELECT_RED + 4);
4372
4373 return src.u32[chan - ISL_CHANNEL_SELECT_RED];
4374 }
4375
4376 /** Applies an inverse swizzle to a color value */
4377 union isl_color_value
isl_color_value_swizzle(union isl_color_value src,struct isl_swizzle swizzle,bool is_float)4378 isl_color_value_swizzle(union isl_color_value src,
4379 struct isl_swizzle swizzle,
4380 bool is_float)
4381 {
4382 uint32_t one = is_float ? 0x3f800000 : 1;
4383
4384 return (union isl_color_value) { .u32 = {
4385 isl_color_value_channel(src, swizzle.r, one),
4386 isl_color_value_channel(src, swizzle.g, one),
4387 isl_color_value_channel(src, swizzle.b, one),
4388 isl_color_value_channel(src, swizzle.a, one),
4389 } };
4390 }
4391
4392 /** Applies an inverse swizzle to a color value */
4393 union isl_color_value
isl_color_value_swizzle_inv(union isl_color_value src,struct isl_swizzle swizzle)4394 isl_color_value_swizzle_inv(union isl_color_value src,
4395 struct isl_swizzle swizzle)
4396 {
4397 union isl_color_value dst = { .u32 = { 0, } };
4398
4399 /* We assign colors in ABGR order so that the first one will be taken in
4400 * RGBA precedence order. According to the PRM docs for shader channel
4401 * select, this matches Haswell hardware behavior.
4402 */
4403 if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
4404 dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
4405 if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
4406 dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
4407 if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
4408 dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
4409 if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
4410 dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
4411
4412 return dst;
4413 }
4414
4415 uint8_t
isl_format_get_aux_map_encoding(enum isl_format format)4416 isl_format_get_aux_map_encoding(enum isl_format format)
4417 {
4418 switch(format) {
4419 case ISL_FORMAT_R32G32B32A32_FLOAT: return 0x11;
4420 case ISL_FORMAT_R32G32B32X32_FLOAT: return 0x11;
4421 case ISL_FORMAT_R32G32B32A32_SINT: return 0x12;
4422 case ISL_FORMAT_R32G32B32A32_UINT: return 0x13;
4423 case ISL_FORMAT_R16G16B16A16_UNORM: return 0x14;
4424 case ISL_FORMAT_R16G16B16A16_SNORM: return 0x15;
4425 case ISL_FORMAT_R16G16B16A16_SINT: return 0x16;
4426 case ISL_FORMAT_R16G16B16A16_UINT: return 0x17;
4427 case ISL_FORMAT_R16G16B16A16_FLOAT: return 0x10;
4428 case ISL_FORMAT_R16G16B16X16_FLOAT: return 0x10;
4429 case ISL_FORMAT_R32G32_FLOAT: return 0x11;
4430 case ISL_FORMAT_R32G32_SINT: return 0x12;
4431 case ISL_FORMAT_R32G32_UINT: return 0x13;
4432 case ISL_FORMAT_B8G8R8A8_UNORM: return 0xA;
4433 case ISL_FORMAT_B8G8R8X8_UNORM: return 0xA;
4434 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB: return 0xA;
4435 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB: return 0xA;
4436 case ISL_FORMAT_R10G10B10A2_UNORM: return 0x18;
4437 case ISL_FORMAT_R10G10B10A2_UNORM_SRGB: return 0x18;
4438 case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM: return 0x19;
4439 case ISL_FORMAT_R10G10B10A2_UINT: return 0x1A;
4440 case ISL_FORMAT_R8G8B8A8_UNORM: return 0xA;
4441 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB: return 0xA;
4442 case ISL_FORMAT_R8G8B8A8_SNORM: return 0x1B;
4443 case ISL_FORMAT_R8G8B8A8_SINT: return 0x1C;
4444 case ISL_FORMAT_R8G8B8A8_UINT: return 0x1D;
4445 case ISL_FORMAT_R16G16_UNORM: return 0x14;
4446 case ISL_FORMAT_R16G16_SNORM: return 0x15;
4447 case ISL_FORMAT_R16G16_SINT: return 0x16;
4448 case ISL_FORMAT_R16G16_UINT: return 0x17;
4449 case ISL_FORMAT_R16G16_FLOAT: return 0x10;
4450 case ISL_FORMAT_B10G10R10A2_UNORM: return 0x18;
4451 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB: return 0x18;
4452 case ISL_FORMAT_R11G11B10_FLOAT: return 0x1E;
4453 case ISL_FORMAT_R32_SINT: return 0x12;
4454 case ISL_FORMAT_R32_UINT: return 0x13;
4455 case ISL_FORMAT_R32_FLOAT: return 0x11;
4456 case ISL_FORMAT_R24_UNORM_X8_TYPELESS: return 0x13;
4457 case ISL_FORMAT_B5G6R5_UNORM: return 0xA;
4458 case ISL_FORMAT_B5G6R5_UNORM_SRGB: return 0xA;
4459 case ISL_FORMAT_B5G5R5A1_UNORM: return 0xA;
4460 case ISL_FORMAT_B5G5R5A1_UNORM_SRGB: return 0xA;
4461 case ISL_FORMAT_B4G4R4A4_UNORM: return 0xA;
4462 case ISL_FORMAT_B4G4R4A4_UNORM_SRGB: return 0xA;
4463 case ISL_FORMAT_R8G8_UNORM: return 0xA;
4464 case ISL_FORMAT_R8G8_SNORM: return 0x1B;
4465 case ISL_FORMAT_R8G8_SINT: return 0x1C;
4466 case ISL_FORMAT_R8G8_UINT: return 0x1D;
4467 case ISL_FORMAT_R16_UNORM: return 0x14;
4468 case ISL_FORMAT_R16_SNORM: return 0x15;
4469 case ISL_FORMAT_R16_SINT: return 0x16;
4470 case ISL_FORMAT_R16_UINT: return 0x17;
4471 case ISL_FORMAT_R16_FLOAT: return 0x10;
4472 case ISL_FORMAT_B5G5R5X1_UNORM: return 0xA;
4473 case ISL_FORMAT_B5G5R5X1_UNORM_SRGB: return 0xA;
4474 case ISL_FORMAT_A1B5G5R5_UNORM: return 0xA;
4475 case ISL_FORMAT_A4B4G4R4_UNORM: return 0xA;
4476 case ISL_FORMAT_R8_UNORM: return 0xA;
4477 case ISL_FORMAT_R8_SNORM: return 0x1B;
4478 case ISL_FORMAT_R8_SINT: return 0x1C;
4479 case ISL_FORMAT_R8_UINT: return 0x1D;
4480 case ISL_FORMAT_A8_UNORM: return 0xA;
4481 case ISL_FORMAT_PLANAR_420_8: return 0xF;
4482 case ISL_FORMAT_PLANAR_420_10: return 0x7;
4483 case ISL_FORMAT_PLANAR_420_12: return 0x8;
4484 case ISL_FORMAT_PLANAR_420_16: return 0x8;
4485 case ISL_FORMAT_YCRCB_NORMAL: return 0x3;
4486 case ISL_FORMAT_YCRCB_SWAPY: return 0xB;
4487 default:
4488 unreachable("Unsupported aux-map format!");
4489 return 0;
4490 }
4491 }
4492
4493 const char *
isl_aux_op_to_name(enum isl_aux_op op)4494 isl_aux_op_to_name(enum isl_aux_op op)
4495 {
4496 static const char *names[] = {
4497 [ISL_AUX_OP_NONE] = "none",
4498 [ISL_AUX_OP_FAST_CLEAR] = "fast-clear",
4499 [ISL_AUX_OP_FULL_RESOLVE] = "full-resolve",
4500 [ISL_AUX_OP_PARTIAL_RESOLVE] = "partial-resolve",
4501 [ISL_AUX_OP_AMBIGUATE] = "ambiguate",
4502 };
4503 assert(op < ARRAY_SIZE(names));
4504 return names[op];
4505 }
4506
4507 const char *
isl_tiling_to_name(enum isl_tiling tiling)4508 isl_tiling_to_name(enum isl_tiling tiling)
4509 {
4510 static const char *names[] = {
4511 [ISL_TILING_LINEAR] = "linear",
4512 [ISL_TILING_W] = "W",
4513 [ISL_TILING_X] = "X",
4514 [ISL_TILING_Y0] = "Y0",
4515 [ISL_TILING_SKL_Yf] = "SKL-Yf",
4516 [ISL_TILING_SKL_Ys] = "SKL-Ys",
4517 [ISL_TILING_ICL_Yf] = "ICL-Yf",
4518 [ISL_TILING_ICL_Ys] = "ICL-Ys",
4519 [ISL_TILING_4] = "4",
4520 [ISL_TILING_64] = "64",
4521 [ISL_TILING_64_XE2] = "64-Xe2",
4522 [ISL_TILING_HIZ] = "hiz",
4523 [ISL_TILING_CCS] = "ccs",
4524 };
4525 assert(tiling < ARRAY_SIZE(names));
4526 return names[tiling];
4527 }
4528
4529 const char *
isl_aux_usage_to_name(enum isl_aux_usage usage)4530 isl_aux_usage_to_name(enum isl_aux_usage usage)
4531 {
4532 static const char *names[] = {
4533 [ISL_AUX_USAGE_NONE] = "none",
4534 [ISL_AUX_USAGE_HIZ] = "hiz",
4535 [ISL_AUX_USAGE_MCS] = "mcs",
4536 [ISL_AUX_USAGE_CCS_D] = "ccs-d",
4537 [ISL_AUX_USAGE_CCS_E] = "ccs-e",
4538 [ISL_AUX_USAGE_FCV_CCS_E] = "fcv-ccs-e",
4539 [ISL_AUX_USAGE_MC] = "mc",
4540 [ISL_AUX_USAGE_HIZ_CCS_WT] = "hiz-ccs-wt",
4541 [ISL_AUX_USAGE_HIZ_CCS] = "hiz-ccs",
4542 [ISL_AUX_USAGE_MCS_CCS] = "mcs-ccs",
4543 [ISL_AUX_USAGE_STC_CCS] = "stc-ccs",
4544 };
4545 assert(usage < ARRAY_SIZE(names));
4546 return names[usage];
4547 }
4548
4549 const char *
isl_aux_state_to_name(enum isl_aux_state state)4550 isl_aux_state_to_name(enum isl_aux_state state)
4551 {
4552 static const char *names[] = {
4553 [ISL_AUX_STATE_CLEAR] = "clear",
4554 [ISL_AUX_STATE_PARTIAL_CLEAR] = "partial_clear",
4555 [ISL_AUX_STATE_COMPRESSED_CLEAR] = "compressed_clear",
4556 [ISL_AUX_STATE_COMPRESSED_NO_CLEAR] = "compressed_no_clear",
4557 [ISL_AUX_STATE_RESOLVED] = "resolved",
4558 [ISL_AUX_STATE_PASS_THROUGH] = "pass-through",
4559 [ISL_AUX_STATE_AUX_INVALID] = "invalid",
4560 };
4561 assert(state < ARRAY_SIZE(names));
4562 return names[state];
4563 }
4564