1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "vk_format.h"
32
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
35
36 static uint32_t
get_depth_format(struct anv_cmd_buffer * cmd_buffer)37 get_depth_format(struct anv_cmd_buffer *cmd_buffer)
38 {
39 struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
40
41 switch (gfx->depth_att.vk_format) {
42 case VK_FORMAT_D16_UNORM:
43 case VK_FORMAT_D16_UNORM_S8_UINT:
44 return D16_UNORM;
45
46 case VK_FORMAT_X8_D24_UNORM_PACK32:
47 case VK_FORMAT_D24_UNORM_S8_UINT:
48 return D24_UNORM_X8_UINT;
49
50 case VK_FORMAT_D32_SFLOAT:
51 case VK_FORMAT_D32_SFLOAT_S8_UINT:
52 return D32_FLOAT;
53
54 default:
55 return D16_UNORM;
56 }
57 }
58
59 void
genX(cmd_buffer_flush_dynamic_state)60 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
61 {
62 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
63 const struct vk_dynamic_graphics_state *dyn =
64 &cmd_buffer->vk.dynamic_graphics_state;
65
66 if ((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
67 ANV_CMD_DIRTY_RENDER_TARGETS)) ||
68 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
69 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_CULL_MODE) ||
70 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_FRONT_FACE) ||
71 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE) ||
72 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS) ||
73 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_LINE_WIDTH)) {
74 /* Take dynamic primitive topology in to account with
75 * 3DSTATE_SF::MultisampleRasterizationMode
76 */
77 VkPolygonMode dynamic_raster_mode =
78 genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
79 dyn->ia.primitive_topology);
80 uint32_t ms_rast_mode =
81 genX(ms_rasterization_mode)(pipeline, dynamic_raster_mode);
82
83 /* From the Haswell PRM, Volume 2b, documentation for
84 * 3DSTATE_SF, "Antialiasing Enable":
85 *
86 * "This field must be disabled if any of the render targets
87 * have integer (UINT or SINT) surface format."
88 */
89 bool aa_enable = anv_rasterization_aa_mode(dynamic_raster_mode,
90 pipeline->line_mode) &&
91 !cmd_buffer->state.gfx.has_uint_rt;
92
93 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
94 struct GENX(3DSTATE_SF) sf = {
95 GENX(3DSTATE_SF_header),
96 .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
97 .LineWidth = dyn->rs.line.width,
98 .AntialiasingEnable = aa_enable,
99 .CullMode = genX(vk_to_intel_cullmode)[dyn->rs.cull_mode],
100 .FrontWinding = genX(vk_to_intel_front_face)[dyn->rs.front_face],
101 .MultisampleRasterizationMode = ms_rast_mode,
102 .GlobalDepthOffsetEnableSolid = dyn->rs.depth_bias.enable,
103 .GlobalDepthOffsetEnableWireframe = dyn->rs.depth_bias.enable,
104 .GlobalDepthOffsetEnablePoint = dyn->rs.depth_bias.enable,
105 .GlobalDepthOffsetConstant = dyn->rs.depth_bias.constant,
106 .GlobalDepthOffsetScale = dyn->rs.depth_bias.slope,
107 .GlobalDepthOffsetClamp = dyn->rs.depth_bias.clamp,
108 };
109 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
110
111 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx7.sf);
112 }
113
114 if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE) ||
115 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_BLEND_CONSTANTS)) {
116 struct anv_state cc_state =
117 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
118 GENX(COLOR_CALC_STATE_length) * 4,
119 64);
120 struct GENX(COLOR_CALC_STATE) cc = {
121 .BlendConstantColorRed = dyn->cb.blend_constants[0],
122 .BlendConstantColorGreen = dyn->cb.blend_constants[1],
123 .BlendConstantColorBlue = dyn->cb.blend_constants[2],
124 .BlendConstantColorAlpha = dyn->cb.blend_constants[3],
125 .StencilReferenceValue = dyn->ds.stencil.front.reference & 0xff,
126 .BackfaceStencilReferenceValue = dyn->ds.stencil.back.reference & 0xff,
127 };
128 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
129
130 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
131 ccp.ColorCalcStatePointer = cc_state.offset;
132 }
133 }
134
135 if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_LINE_STIPPLE)) {
136 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
137 ls.LineStipplePattern = dyn->rs.line.stipple.pattern;
138 ls.LineStippleInverseRepeatCount =
139 1.0f / MAX2(1, dyn->rs.line.stipple.factor);
140 ls.LineStippleRepeatCount = dyn->rs.line.stipple.factor;
141 }
142 }
143
144 if ((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
145 ANV_CMD_DIRTY_RENDER_TARGETS)) ||
146 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE) ||
147 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE) ||
148 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP) ||
149 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE) ||
150 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_OP) ||
151 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK) ||
152 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK)) {
153 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
154
155 VkImageAspectFlags ds_aspects = 0;
156 if (cmd_buffer->state.gfx.depth_att.vk_format != VK_FORMAT_UNDEFINED)
157 ds_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
158 if (cmd_buffer->state.gfx.stencil_att.vk_format != VK_FORMAT_UNDEFINED)
159 ds_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
160
161 struct vk_depth_stencil_state opt_ds = dyn->ds;
162 vk_optimize_depth_stencil_state(&opt_ds, ds_aspects, true);
163
164 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
165 .DoubleSidedStencilEnable = true,
166
167 .StencilTestMask = opt_ds.stencil.front.compare_mask & 0xff,
168 .StencilWriteMask = opt_ds.stencil.front.write_mask & 0xff,
169
170 .BackfaceStencilTestMask = opt_ds.stencil.back.compare_mask & 0xff,
171 .BackfaceStencilWriteMask = opt_ds.stencil.back.write_mask & 0xff,
172
173 .DepthTestEnable = opt_ds.depth.test_enable,
174 .DepthBufferWriteEnable = opt_ds.depth.write_enable,
175 .DepthTestFunction = genX(vk_to_intel_compare_op)[opt_ds.depth.compare_op],
176 .StencilTestEnable = opt_ds.stencil.test_enable,
177 .StencilBufferWriteEnable = opt_ds.stencil.write_enable,
178 .StencilFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.front.op.fail],
179 .StencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.front.op.pass],
180 .StencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.front.op.depth_fail],
181 .StencilTestFunction = genX(vk_to_intel_compare_op)[opt_ds.stencil.front.op.compare],
182 .BackfaceStencilFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.back.op.fail],
183 .BackfaceStencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.back.op.pass],
184 .BackfaceStencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[opt_ds.stencil.back.op.depth_fail],
185 .BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[opt_ds.stencil.back.op.compare],
186 };
187 GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
188
189 struct anv_state ds_state =
190 anv_cmd_buffer_emit_dynamic(cmd_buffer, depth_stencil_dw,
191 sizeof(depth_stencil_dw), 64);
192
193 anv_batch_emit(&cmd_buffer->batch,
194 GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
195 dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
196 }
197 }
198
199 if (cmd_buffer->state.gfx.index_buffer &&
200 ((cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
201 ANV_CMD_DIRTY_INDEX_BUFFER)) ||
202 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE))) {
203 struct anv_buffer *buffer = cmd_buffer->state.gfx.index_buffer;
204 uint32_t offset = cmd_buffer->state.gfx.index_offset;
205
206 #if GFX_VERx10 == 75
207 anv_batch_emit(&cmd_buffer->batch, GFX75_3DSTATE_VF, vf) {
208 vf.IndexedDrawCutIndexEnable = dyn->ia.primitive_restart_enable;
209 vf.CutIndex = cmd_buffer->state.gfx.restart_index;
210 }
211 #endif
212
213 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
214 #if GFX_VERx10 != 75
215 ib.CutIndexEnable = dyn->ia.primitive_restart_enable;
216 #endif
217 ib.IndexFormat = cmd_buffer->state.gfx.index_type;
218 ib.MOCS = anv_mocs(cmd_buffer->device,
219 buffer->address.bo,
220 ISL_SURF_USAGE_INDEX_BUFFER_BIT);
221
222 ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
223 ib.BufferEndingAddress = anv_address_add(buffer->address,
224 buffer->vk.size);
225 }
226 }
227
228 /* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
229 * threads or if we have dirty dynamic primitive topology state and
230 * need to toggle 3DSTATE_WM::MultisampleRasterizationMode dynamically.
231 */
232 if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
233 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
234 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
235 VkPolygonMode dynamic_raster_mode =
236 genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
237 dyn->ia.primitive_topology);
238
239 uint32_t dwords[GENX(3DSTATE_WM_length)];
240 struct GENX(3DSTATE_WM) wm = {
241 GENX(3DSTATE_WM_header),
242
243 .ThreadDispatchEnable = anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
244 (pipeline->force_fragment_thread_dispatch ||
245 !anv_cmd_buffer_all_color_write_masked(cmd_buffer)),
246 .MultisampleRasterizationMode =
247 genX(ms_rasterization_mode)(pipeline,
248 dynamic_raster_mode),
249 };
250 GENX(3DSTATE_WM_pack)(NULL, dwords, &wm);
251
252 anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm);
253 }
254
255 if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_RENDER_TARGETS) ||
256 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS)) {
257 const uint32_t samples = MAX2(1, cmd_buffer->state.gfx.samples);
258 const struct vk_sample_locations_state *sl = dyn->ms.sample_locations;
259 genX(emit_multisample)(&cmd_buffer->batch, samples,
260 sl->per_pixel == samples ? sl : NULL);
261 }
262
263 if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
264 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
265 BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
266 const uint8_t color_writes = dyn->cb.color_write_enables;
267
268 /* Blend states of each RT */
269 uint32_t blend_dws[GENX(BLEND_STATE_length) +
270 MAX_RTS * GENX(BLEND_STATE_ENTRY_length)];
271 uint32_t *dws = blend_dws;
272 memset(blend_dws, 0, sizeof(blend_dws));
273
274 /* Skip this part */
275 dws += GENX(BLEND_STATE_length);
276
277 for (uint32_t i = 0; i < MAX_RTS; i++) {
278 /* Disable anything above the current number of color attachments. */
279 bool write_disabled = i >= cmd_buffer->state.gfx.color_att_count ||
280 (color_writes & BITFIELD_BIT(i)) == 0;
281 struct GENX(BLEND_STATE_ENTRY) entry = {
282 .WriteDisableAlpha = write_disabled ||
283 (pipeline->color_comp_writes[i] &
284 VK_COLOR_COMPONENT_A_BIT) == 0,
285 .WriteDisableRed = write_disabled ||
286 (pipeline->color_comp_writes[i] &
287 VK_COLOR_COMPONENT_R_BIT) == 0,
288 .WriteDisableGreen = write_disabled ||
289 (pipeline->color_comp_writes[i] &
290 VK_COLOR_COMPONENT_G_BIT) == 0,
291 .WriteDisableBlue = write_disabled ||
292 (pipeline->color_comp_writes[i] &
293 VK_COLOR_COMPONENT_B_BIT) == 0,
294 .LogicOpFunction = genX(vk_to_intel_logic_op)[dyn->cb.logic_op],
295 };
296 GENX(BLEND_STATE_ENTRY_pack)(NULL, dws, &entry);
297 dws += GENX(BLEND_STATE_ENTRY_length);
298 }
299
300 uint32_t num_dwords = GENX(BLEND_STATE_length) +
301 GENX(BLEND_STATE_ENTRY_length) * MAX_RTS;
302
303 struct anv_state blend_states =
304 anv_cmd_buffer_merge_dynamic(cmd_buffer, blend_dws,
305 pipeline->gfx7.blend_state, num_dwords, 64);
306 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
307 bsp.BlendStatePointer = blend_states.offset;
308 }
309 }
310
311 /* When we're done, there is no more dirty gfx state. */
312 vk_dynamic_graphics_state_clear_dirty(&cmd_buffer->vk.dynamic_graphics_state);
313 cmd_buffer->state.gfx.dirty = 0;
314 }
315
316 void
genX(cmd_buffer_enable_pma_fix)317 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
318 bool enable)
319 {
320 /* The NP PMA fix doesn't exist on gfx7 */
321 }
322