xref: /aosp_15_r20/external/mesa3d/src/nouveau/codegen/nv50_ir_lowering_helper.cpp (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright 2018 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Karol Herbst <[email protected]>
23  */
24 
25 #include "nv50_ir_lowering_helper.h"
26 
27 namespace nv50_ir {
28 
29 bool
visit(Instruction * insn)30 LoweringHelper::visit(Instruction *insn)
31 {
32    switch (insn->op) {
33    case OP_ABS:
34       return handleABS(insn);
35    case OP_CVT:
36       return handleCVT(insn);
37    case OP_MAX:
38    case OP_MIN:
39       return handleMAXMIN(insn);
40    case OP_MOV:
41       return handleMOV(insn);
42    case OP_NEG:
43       return handleNEG(insn);
44    case OP_SAT:
45       return handleSAT(insn);
46    case OP_SLCT:
47       return handleSLCT(insn->asCmp());
48    case OP_AND:
49    case OP_NOT:
50    case OP_OR:
51    case OP_XOR:
52       return handleLogOp(insn);
53    default:
54       return true;
55    }
56 }
57 
58 bool
handleABS(Instruction * insn)59 LoweringHelper::handleABS(Instruction *insn)
60 {
61    DataType dTy = insn->dType;
62    if (!(dTy == TYPE_U64 || dTy == TYPE_S64))
63       return true;
64 
65    bld.setPosition(insn, false);
66 
67    Value *neg = bld.getSSA(8);
68    Value *negComp[2], *srcComp[2];
69    Value *lo = bld.getSSA(), *hi = bld.getSSA();
70    bld.mkOp2(OP_SUB, dTy, neg, bld.mkImm((uint64_t)0), insn->getSrc(0));
71    bld.mkSplit(negComp, 4, neg);
72    bld.mkSplit(srcComp, 4, insn->getSrc(0));
73    bld.mkCmp(OP_SLCT, CC_LT, TYPE_S32, lo, TYPE_S32, negComp[0], srcComp[0], srcComp[1]);
74    bld.mkCmp(OP_SLCT, CC_LT, TYPE_S32, hi, TYPE_S32, negComp[1], srcComp[1], srcComp[1]);
75    insn->op = OP_MERGE;
76    insn->setSrc(0, lo);
77    insn->setSrc(1, hi);
78 
79    return true;
80 }
81 
82 bool
handleCVT(Instruction * insn)83 LoweringHelper::handleCVT(Instruction *insn)
84 {
85    DataType dTy = insn->dType;
86    DataType sTy = insn->sType;
87 
88    bld.setPosition(insn, true);
89 
90    /* We can't convert from 32bit floating point to 8bit integer and from 64bit
91     * floating point to any integer smaller than 32bit, hence add an instruction
92     * to convert to a 32bit integer first.
93     */
94    if (((typeSizeof(dTy) == 1) && isFloatType(sTy)) ||
95        ((typeSizeof(dTy) <= 2) && sTy == TYPE_F64)) {
96       Value *tmp = insn->getDef(0);
97       DataType tmpTy = (isSignedIntType(dTy)) ? TYPE_S32 : TYPE_U32;
98 
99       insn->setType(tmpTy, sTy);
100       insn->setDef(0, bld.getSSA());
101       bld.mkCvt(OP_CVT, dTy, tmp, tmpTy, insn->getDef(0))->saturate = 1;
102 
103       return true;
104    }
105 
106    bld.setPosition(insn, false);
107 
108    /* We can't convert from a 64 bit integer to any integer smaller than 64 bit
109     * directly, hence split the value first and then cvt / mov to the target
110     * type.
111     */
112    if (isIntType(dTy) && typeSizeof(dTy) <= 4 &&
113        isIntType(sTy) && typeSizeof(sTy) == 8) {
114       DataType tmpTy = (isSignedIntType(dTy)) ? TYPE_S32 : TYPE_U32;
115       Value *src[2];
116 
117       bld.mkSplit(src, 4, insn->getSrc(0));
118       insn->setSrc(0, src[0]);
119 
120       /* For a 32 bit integer, we just need to mov the value to it's
121        * destination. */
122       if (typeSizeof(dTy) == 4) {
123          insn->op = OP_MOV;
124       } else { /* We're smaller than 32 bit, hence convert. */
125          insn->op = OP_CVT;
126          insn->setType(dTy, tmpTy);
127       }
128 
129       return true;
130    }
131 
132    /* We can't convert to signed 64 bit integrers, hence shift the upper word
133     * and merge. For sources smaller than 32 bit, convert to 32 bit first.
134     */
135    if (dTy == TYPE_S64 && isSignedIntType(sTy) && typeSizeof(sTy) <= 4) {
136       Value *tmpExtbf;
137       Value *tmpShr = bld.getSSA();
138 
139       if (typeSizeof(sTy) < 4) {
140          unsigned int interval = typeSizeof(sTy) == 1 ? 0x800 : 0x1000;
141          tmpExtbf = bld.getSSA();
142          bld.mkOp2(OP_EXTBF, TYPE_S32, tmpExtbf, insn->getSrc(0),
143                    bld.loadImm(bld.getSSA(), interval));
144          insn->setSrc(0, tmpExtbf);
145       } else {
146          tmpExtbf = insn->getSrc(0);
147       }
148 
149       bld.mkOp2(OP_SHR, TYPE_S32, tmpShr, tmpExtbf, bld.loadImm(bld.getSSA(), 31));
150 
151       insn->op = OP_MERGE;
152       insn->setSrc(1, tmpShr);
153 
154       return true;
155    }
156 
157    if (dTy == TYPE_U64 && isUnsignedIntType(sTy) && typeSizeof(sTy) <= 4) {
158       insn->op = OP_MERGE;
159       insn->setSrc(1, bld.loadImm(bld.getSSA(), 0));
160 
161       return true;
162    }
163 
164    return true;
165 }
166 
167 bool
handleMAXMIN(Instruction * insn)168 LoweringHelper::handleMAXMIN(Instruction *insn)
169 {
170    DataType dTy = insn->dType;
171    if (!(dTy == TYPE_U64 || dTy == TYPE_S64))
172       return true;
173 
174    DataType sTy = typeOfSize(4, false, isSignedIntType(dTy));
175    bld.setPosition(insn, false);
176 
177    Value *flag = bld.getSSA(1, FILE_FLAGS);
178    Value *src0[2];
179    Value *src1[2];
180    Value *def[2];
181 
182    bld.mkSplit(src0, 4, insn->getSrc(0));
183    bld.mkSplit(src1, 4, insn->getSrc(1));
184 
185    def[0] = bld.getSSA();
186    def[1] = bld.getSSA();
187 
188    Instruction *hi = bld.mkOp2(insn->op, sTy, def[1], src0[1], src1[1]);
189    hi->subOp = NV50_IR_SUBOP_MINMAX_HIGH;
190    hi->setFlagsDef(1, flag);
191 
192    Instruction *lo = bld.mkOp2(insn->op, sTy, def[0], src0[0], src1[0]);
193    lo->subOp = NV50_IR_SUBOP_MINMAX_LOW;
194    lo->setFlagsSrc(2, flag);
195 
196    insn->op = OP_MERGE;
197    insn->setSrc(0, def[0]);
198    insn->setSrc(1, def[1]);
199 
200    return true;
201 }
202 
203 bool
handleMOV(Instruction * insn)204 LoweringHelper::handleMOV(Instruction *insn)
205 {
206    DataType dTy = insn->dType;
207 
208    if (typeSizeof(dTy) != 8)
209       return true;
210 
211    Storage &reg = insn->getSrc(0)->reg;
212 
213    if (reg.file != FILE_IMMEDIATE)
214       return true;
215 
216    bld.setPosition(insn, false);
217 
218    Value *hi = bld.getSSA();
219    Value *lo = bld.getSSA();
220 
221    bld.loadImm(lo, (uint32_t)(reg.data.u64 & 0xffffffff));
222    bld.loadImm(hi, (uint32_t)(reg.data.u64 >> 32));
223 
224    insn->op = OP_MERGE;
225    insn->setSrc(0, lo);
226    insn->setSrc(1, hi);
227 
228    return true;
229 }
230 
231 bool
handleNEG(Instruction * insn)232 LoweringHelper::handleNEG(Instruction *insn)
233 {
234    if (typeSizeof(insn->dType) != 8 || isFloatType(insn->dType))
235       return true;
236 
237    bld.setPosition(insn, false);
238 
239    insn->op = OP_SUB;
240    insn->setSrc(1, insn->getSrc(0));
241    insn->setSrc(0, bld.mkImm((uint64_t)0));
242    return true;
243 }
244 
245 bool
handleSAT(Instruction * insn)246 LoweringHelper::handleSAT(Instruction *insn)
247 {
248    DataType dTy = insn->dType;
249 
250    if (typeSizeof(dTy) != 8 || !isFloatType(dTy))
251       return true;
252 
253    bld.setPosition(insn, false);
254 
255    Value *tmp = bld.mkOp2v(OP_MAX, dTy, bld.getSSA(8), insn->getSrc(0), bld.loadImm(bld.getSSA(8), 0.0));
256    insn->op = OP_MIN;
257    insn->setSrc(0, tmp);
258    insn->setSrc(1, bld.loadImm(bld.getSSA(8), 1.0));
259    return true;
260 }
261 
262 bool
handleSLCT(CmpInstruction * insn)263 LoweringHelper::handleSLCT(CmpInstruction *insn)
264 {
265    DataType dTy = insn->dType;
266    DataType sTy = insn->sType;
267 
268    if (typeSizeof(dTy) != 8 || typeSizeof(sTy) == 8)
269       return true;
270 
271    CondCode cc = insn->getCondition();
272    DataType hdTy = typeOfSize(4, isFloatType(dTy), isSignedIntType(dTy));
273    bld.setPosition(insn, false);
274 
275    Value *src0[2];
276    Value *src1[2];
277    Value *def[2];
278 
279    bld.mkSplit(src0, 4, insn->getSrc(0));
280    bld.mkSplit(src1, 4, insn->getSrc(1));
281 
282    def[0] = bld.getSSA();
283    def[1] = bld.getSSA();
284 
285    bld.mkCmp(OP_SLCT, cc, hdTy, def[0], sTy, src0[0], src1[0], insn->getSrc(2));
286    bld.mkCmp(OP_SLCT, cc, hdTy, def[1], sTy, src0[1], src1[1], insn->getSrc(2));
287 
288    insn->op = OP_MERGE;
289    insn->setSrc(0, def[0]);
290    insn->setSrc(1, def[1]);
291    insn->setSrc(2, NULL);
292 
293    return true;
294 }
295 
296 bool
handleLogOp(Instruction * insn)297 LoweringHelper::handleLogOp(Instruction *insn)
298 {
299    DataType dTy = insn->dType;
300    DataType sTy = typeOfSize(4, isFloatType(dTy), isSignedIntType(dTy));
301 
302    if (typeSizeof(dTy) != 8)
303       return true;
304 
305    bld.setPosition(insn, false);
306 
307    Value *src0[2];
308    Value *src1[2];
309    Value *def0 = bld.getSSA();
310    Value *def1 = bld.getSSA();
311 
312    bld.mkSplit(src0, 4, insn->getSrc(0));
313    if (insn->srcExists(1))
314       bld.mkSplit(src1, 4, insn->getSrc(1));
315 
316    Instruction *lo = bld.mkOp1(insn->op, sTy, def0, src0[0]);
317    Instruction *hi = bld.mkOp1(insn->op, sTy, def1, src0[1]);
318    if (insn->srcExists(1)) {
319       lo->setSrc(1, src1[0]);
320       hi->setSrc(1, src1[1]);
321    }
322 
323    insn->op = OP_MERGE;
324    insn->setSrc(0, def0);
325    insn->setSrc(1, def1);
326 
327    return true;
328 }
329 
330 } // namespace nv50_ir
331