1 /******************************************************************************* 2 Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 #ifndef _cl006c_h_ 24 #define _cl006c_h_ 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include "nvtypes.h" 31 32 /* class NV04_CHANNEL_DMA */ 33 #define NV04_CHANNEL_DMA (0x0000006C) 34 #define NV06C_NOTIFIERS_MAXCOUNT 1 35 /* NvNotification[] fields and values */ 36 #define NV06C_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) 37 #define NV06C_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) 38 /* pio method data structure */ 39 typedef volatile struct _cl006c_tag0 { 40 NvV32 Reserved00[0x7c0]; 41 } Nv06cTypedef, Nv04ChannelDma; 42 #define NV06C_TYPEDEF Nv04ChannelDma 43 /* pio flow control data structure */ 44 typedef volatile struct _cl006c_tag1 { 45 NvV32 Ignored00[0x010]; 46 NvU32 Put; /* put offset, write only 0040-0043*/ 47 NvU32 Get; /* get offset, read only 0044-0047*/ 48 NvV32 Ignored01[0x002]; 49 NvU32 StallNotifier; /* Set stall notifier 0050-0053*/ 50 NvU32 StallChannel; /* Stall the channel 0054-0057*/ 51 NvV32 Ignored02[0x3EA]; 52 } Nv04ControlDma; 53 /* obsolete stuff */ 54 #define NV4_CHANNEL_DMA (0x0000006C) 55 #define Nv4ChannelDma Nv04ChannelDma 56 #define nv4ChannelDma Nv04ChannelDma 57 #define Nv4ControlDma Nv04ControlDma 58 59 /* dma method descriptor format */ 60 #define NV06C_METHOD_ADDRESS 12:2 61 #define NV06C_METHOD_SUBCHANNEL 15:13 62 #define NV06C_METHOD_COUNT 28:18 63 #define NV06C_OPCODE 31:29 64 #define NV06C_OPCODE_METHOD (0x00000000) 65 #define NV06C_OPCODE_NONINC_METHOD (0x00000002) 66 /* dma data format */ 67 #define NV06C_DATA 31:0 68 /* dma jump format */ 69 #define NV06C_OPCODE_JUMP (0x00000001) 70 #define NV06C_JUMP_OFFSET 28:2 71 72 #ifdef __cplusplus 73 }; /* extern "C" */ 74 #endif 75 76 #endif /* _cl006c_h_ */ 77