1 /******************************************************************************* 2 Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 #ifndef _cl406e_h_ 24 #define _cl406e_h_ 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include "nvtypes.h" 31 32 /* class NV40_CHANNEL_DMA */ 33 #define NV40_CHANNEL_DMA (0x0000406E) 34 35 /* event values */ 36 #define NV406E_NOTIFIERS_RC (0) 37 #define NV406E_NOTIFIERS_SW (1) 38 #define NV406E_NOTIFIERS_MAXCOUNT (2) 39 40 /* NvNotification[] fields and values */ 41 #define NV406E_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) 42 #define NV406E_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) 43 /* pio method data structure */ 44 typedef volatile struct _cl406e_tag0 { 45 NvV32 Reserved00[0x7c0]; 46 } Nv406eTypedef, Nv40ChannelDma; 47 #define NV406E_TYPEDEF Nv40ChannelDma 48 /* pio flow control data structure */ 49 typedef volatile struct _cl406e_tag1 { 50 NvV32 Ignored00[0x010]; 51 NvU32 Put; /* put offset, write only 0040-0043*/ 52 NvU32 Get; /* get offset, read only 0044-0047*/ 53 NvU32 Reference; /* reference value, read only 0048-004b*/ 54 NvU32 Ignored01[0x1]; 55 NvU32 SetReference; /* set reference value 0050-0053*/ 56 NvU32 TopLevelGet; /* top level get offset, read only 0054-0057*/ 57 NvU32 Ignored02[0x2]; 58 NvU32 SetContextDmaSemaphore; /* set sema ctxdma, write only 0060-0063*/ 59 NvU32 SetSemaphoreOffset; /* set sema offset, write only 0064-0067*/ 60 NvU32 SetSemaphoreAcquire; /* set sema acquire, write only 0068-006b*/ 61 NvU32 SetSemaphoreRelease; /* set sema release, write only 006c-006f*/ 62 NvV32 Ignored03[0x3e4]; 63 } Nv406eControl, Nv40ControlDma; 64 /* fields and values */ 65 #define NV406E_NUMBER_OF_SUBCHANNELS (8) 66 #define NV406E_SET_OBJECT (0x00000000) 67 #define NV406E_SET_REFERENCE (0x00000050) 68 #define NV406E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060) 69 #define NV406E_SEMAPHORE_OFFSET (0x00000064) 70 #define NV406E_SEMAPHORE_ACQUIRE (0x00000068) 71 #define NV406E_SEMAPHORE_RELEASE (0x0000006c) 72 73 /* dma method descriptor format */ 74 #define NV406E_DMA_METHOD_ADDRESS 12:2 75 #define NV406E_DMA_METHOD_SUBCHANNEL 15:13 76 #define NV406E_DMA_METHOD_COUNT 28:18 77 78 /* dma opcode format */ 79 #define NV406E_DMA_OPCODE 31:29 80 #define NV406E_DMA_OPCODE_METHOD (0x00000000) 81 #define NV406E_DMA_OPCODE_NONINC_METHOD (0x00000002) 82 /* dma jump format */ 83 #define NV406E_DMA_OPCODE_JUMP (0x00000001) 84 #define NV406E_DMA_JUMP_OFFSET 28:2 85 86 /* dma opcode2 format */ 87 #define NV406E_DMA_OPCODE2 1:0 88 #define NV406E_DMA_OPCODE2_NONE (0x00000000) 89 /* dma jump_long format */ 90 #define NV406E_DMA_OPCODE2_JUMP_LONG (0x00000001) 91 #define NV406E_DMA_JUMP_LONG_OFFSET 31:2 92 /* dma call format */ 93 #define NV406E_DMA_OPCODE2_CALL (0x00000002) 94 #define NV406E_DMA_CALL_OFFSET 31:2 95 96 /* dma opcode3 format */ 97 #define NV406E_DMA_OPCODE3 17:16 98 #define NV406E_DMA_OPCODE3_NONE (0x00000000) 99 /* dma return format */ 100 #define NV406E_DMA_RETURN (0x00020000) 101 #define NV406E_DMA_OPCODE3_RETURN (0x00000002) 102 103 /* dma data format */ 104 #define NV406E_DMA_DATA 31:0 105 106 /* dma nop format */ 107 #define NV406E_DMA_NOP (0x00000000) 108 109 /* dma set subdevice mask format */ 110 #define NV406E_DMA_SET_SUBDEVICE_MASK (0x00010000) 111 #define NV406E_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 112 #define NV406E_DMA_OPCODE3_SET_SUBDEVICE_MASK (0x00000001) 113 114 #ifdef __cplusplus 115 }; /* extern "C" */ 116 #endif 117 118 #endif /* _cl406e_h_ */ 119